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| intel ? 82801eb i/o controller hub 5 (ich5) / intel ? 82801er i/o controller hub 5 r (ich5r) datasheet april 2003 document number: 252516-001
2 intel ? 82801eb ich5 / 82801er ich5r datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? 82801eb i/o controller hub 5 (ich5) / intel ? 82801er i/o controller hub 5 r (ich5r) chipset component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are a vailable on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. i 2 c is a two-wire communications bus/protocol developed by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, including philips electronics n.v. and north american philips corporation. alert on lan is a result of the intel-ibm advanced manageability alliance and a trademark of ibm. intel, intel speedstep and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in t he united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2002?2003, intel corporation intel ? 82801eb ich5 / 82801er ich5r datasheet 3 contents intel ? ich5/ich5r features pci bus interface ? new: supports pci revision 2.3 specification at 33 mhz ? 6 available pci req/gnt pairs ? one pci req/gnt pair can be given higher arbitration priority (intended for external 1394 host controller) ? support for 44-bit addressing on pci using dac protocol integrated lan controller ? new: integrated asf management controller ? wfm 2.0 and ieee 802.3 compliant ? lan connect interface (lci) ? 10/100 mbit/sec ethernet support new: integrated serial ata host controllers ? independent dma operation on two ports. ? data transfer rates up to 1.5 gb/s (150 mb/s). ? raid level 0 support (ich5r only) integrated ide controller ? supports ?native mode? register and interrupts ? independent timing of up to 4 drives ? ultra ata/100/66/33, bmide and pio modes ? tri-state modes to enable swap bay usb 2.0 ? new: includes 4 uhci host controllers, increasing the number of external ports to eight ? includes 1 ehci host controller that supports all eight ports ? includes 1 usb 2.0 high-speed debug port ? supports wake-up from sleeping states s1?s5 ? supports legacy keyboard/mouse software ac-link for audio and telephony codecs ? support for 3 ac ?97 2.3 codecs. ? independent bus master logic for 8 channels (pcm in/out, pcm2 in, mic 1 input, mic 2 input, modem in/out, s/pdif out) ? support for up to six channels of pcm audio output (full ac3 decode) ? supports wake-up events interrupt controller ? supports up to 8 pci interrupt pins ? supports pci 2.3 message signaled interrupts ? two cascaded 82c59 with 15 interrupts ? integrated i/o apic capability with 24 interrupts ? supports front side bus interrupt delivery high-precision event timers ? advanced operating system interrupt scheduling new: 1.5 v operation with 3.3 v i/o ? 5v tolerant buffers on ide, pci, usb over- current and legacy signals timers based on 82c54 ? system timer, refresh request, speaker tone output new: integrated 1.5 v voltage regulator (intvr) for the suspend wells power management logic ? new: acpi 2.0 compliant ? acpi-defined power states (c1, s3?s5) ? acpi power management timer ? pci pme# support ? smi# generation ? all registers readable/restorable for proper resume from 0 v suspend states ? support for apm-based legacy power management for non-acpi implementations external glue integration ? integrated pull-up, pull-down and series termination resistors on ide, processor i/f ? integrated pull-down and series resistors on usb flash bios i/f supports bios memory size up to 8 mbytes low pin count (lpc) i/f ? supports two master/dma devices. ? support for security devices connected to lpc. enhanced dma controller ? two cascaded 8237 dma controllers ? pci dma: supports pc/pci ? includes two pc/pci req#/gnt# pairs ? supports lpc dma ? supports dma collection buffer to provide type- f dma performance for all dma channels real-time clock ? 256-byte battery-backed cmos ram ? integrated oscillator components ? lower power dc/dc converter implementation system tco reduction circuits ? timers to generate smi# and reset upon detection of system hang ? timers to detect improper processor reset ? integrated processor frequency strap logic ? supports ability to disable external devices smbus ? new: provides independent manageability bus through smlink interface. ? supports smbus 2.0 specification ? host interface allows processor to communicate via smbus ? slave interface allows an internal or external microcontroller to access system resources ? compatible with most 2-wire components that are also i 2 c compatible gpio ? ttl, open-drain, inversion package 31x31 mm 460 mbga the intel ? ich5 / ich5r may contain design defects or errors known as errata which may cause the products to deviate from published specifications. current characterized errata are available on request. 4 intel ? 82801eb ich5 / 82801er ich5r datasheet contents system block diagram intel ? 82801eb ich5 or intel ? 82801er ich5r usb 2.0 (supports 8 usb ports) system management (tco) ide-primary gpio smbus 2.0/i 2 c ide-secondary power management pci bus ... clock generators s l o t s l o t agp mch lan connect ac?97 codec(s) m e m o r y processor lan flash bios other asics (optional) lpc i/f super i/o sata (2 ports) intel ? 82801eb ich5 / 82801er ich5r datasheet 5 contents contents 1 introduction ............................................................................................................................... ...39 1.1 about this manual........................................................................................................... ...39 1.2 overview.................................................................................................................... .........42 2 signal description .......................................................................................................................49 2.1 hub interface to host controller .........................................................................................51 2.2 link to lan connect......................................................................................................... ..51 2.3 eeprom interface ............................................................................................................ .51 2.4 flash bios interface ........................................................................................................ ..52 2.5 pci interface............................................................................................................... ........52 2.6 serial ata interface........................................................................................................ ....54 2.7 ide interface............................................................................................................... ........55 2.8 lpc interface............................................................................................................... .......56 2.9 interrupt interface ......................................................................................................... ......57 2.10 usb interface .............................................................................................................. .......58 2.11 power management interface.............................................................................................59 2.12 processor interface........................................................................................................ .....60 2.13 smbus interface ............................................................................................................ .....61 2.14 system management interface...........................................................................................61 2.15 real time clock interface .................................................................................................. 62 2.16 other clocks ............................................................................................................... ........62 2.17 miscellaneous signals ...................................................................................................... ..62 2.18 ac-link .................................................................................................................... ...........63 2.19 general purpose i/o ........................................................................................................ ...63 2.20 power and ground........................................................................................................... ...65 2.21 pin straps ................................................................................................................. ..........66 2.21.1 functional straps ...................................................................................................66 2.21.2 external rtc circuitry ...........................................................................................67 2.21.3 power sequencing requirements .........................................................................67 2.21.3.1 v5ref / vcc3_3 sequencing requirements .........................................67 2.21.3.2 3.3 v/1.5 v standby power sequencing requirements ........................68 2.21.4 test signals ...........................................................................................................68 2.21.4.1 test mode selection ..............................................................................68 3intel ? ich5 power planes and pin states ..................................................................................69 3.1 power planes................................................................................................................ ......69 3.2 integrated pull-ups and pull-downs ...................................................................................70 3.3 ide integrated series termination resistors .....................................................................71 3.4 output and i/o signals planes and states .........................................................................71 3.5 power planes for input signals...........................................................................................75 4intel ? ich5 and system clock domains ....................................................................................77 5 functional description ................................................................................................................79 5.1 hub interface to pci bridge (d30:f0).................................................................................79 5.1.1 pci bus interface...................................................................................................79 5.1.2 pci-to-pci bridge model .......................................................................................80 6 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 5.1.3 idsel to device number mapping........................................................................ 80 5.1.4 serr# functionality.............................................................................................. 80 5.1.5 parity error detection ............................................................................................ 82 5.1.6 standard pci bus configuration mechanism ........................................................ 83 5.1.6.1 type 0 to type 0 forwarding ................................................................. 83 5.1.6.2 type 1 to type 0 conversion................................................................. 83 5.1.7 pci dual address cycle (dac) support................................................................ 84 5.2 lan controller (b1:d8:f0).................................................................................................. 8 4 5.2.1 lan controller architectural overview .................................................................. 85 5.2.1.1 parallel subsystem overview ................................................................ 86 5.2.1.2 fifo subsystem overview .................................................................... 87 5.2.1.3 serial csma/cd unit overview............................................................. 87 5.2.2 lan controller pci bus interface .......................................................................... 88 5.2.2.1 bus slave operation .............................................................................. 88 5.2.2.2 bus master operation ............................................................................ 90 5.2.2.3 pci power management........................................................................ 93 5.2.2.4 pci reset signal.................................................................................... 94 5.2.2.5 wake-up events .................................................................................... 95 5.2.2.6 wake on lan* (preboot wake-up) ....................................................... 96 5.2.3 serial eeprom interface ...................................................................................... 96 5.2.4 csma/cd unit....................................................................................................... 97 5.2.4.1 full duplex ............................................................................................. 97 5.2.4.2 flow control........................................................................................... 97 5.2.4.3 address filtering modifications .............................................................. 97 5.2.4.4 vlan support ........................................................................................ 98 5.2.5 media management interface ................................................................................ 98 5.2.6 tco functionality .................................................................................................. 98 5.2.6.1 advanced tco mode ............................................................................ 98 5.3 alert standard format (asf) ............................................................................................ 100 5.3.1 asf management solution features/capabilities ............................................... 101 5.3.2 asf hardware support........................................................................................ 102 5.3.2.1 82562em/ex........................................................................................ 102 5.3.2.2 eeprom (256x16, 1 mhz).................................................................. 102 5.3.2.3 legacy sensor smbus devices........................................................... 102 5.3.2.4 remote control smbus devices ......................................................... 102 5.3.2.5 asf sensor smbus devices ............................................................... 102 5.3.3 asf software support ......................................................................................... 102 5.4 lpc bridge (w/ system and management functions) (d31:f0)....................................... 103 5.4.1 lpc interface....................................................................................................... 103 5.4.1.1 lpc cycle types ................................................................................. 104 5.4.1.2 start field definition............................................................................. 104 5.4.1.3 cycle type / direction (cyctype + dir) ........................................... 105 5.4.1.4 size ..................................................................................................... 105 5.4.1.5 sync ................................................................................................... 106 5.4.1.6 sync time-out ................................................................................... 106 5.4.1.7 sync error indication.......................................................................... 106 5.4.1.8 lframe# usage ................................................................................. 107 5.4.1.9 i/o cycles ............................................................................................ 108 5.4.1.10 bus master cycles ............................................................................... 108 5.4.1.11 lpc power management..................................................................... 108 5.4.1.12 configuration and intel ? ich5 implications ......................................... 108 intel ? 82801eb ich5 / 82801er ich5r datasheet 7 contents 5.5 dma operation (d31:f0) ..................................................................................................109 5.5.1 channel priority ...................................................................................................110 5.5.1.1 fixed priority ........................................................................................110 5.5.1.2 rotating priority ...................................................................................110 5.5.2 address compatibility mode ................................................................................110 5.5.3 summary of dma transfer sizes ........................................................................111 5.5.3.1 address shifting when programmed for 16-bit i/o count by words .............................................................................111 5.5.4 autoinitialize.........................................................................................................111 5.5.5 software commands ...........................................................................................112 5.5.5.1 clear byte pointer flip-flop.................................................................112 5.5.5.2 dma master clear ...............................................................................112 5.5.5.3 clear mask register ............................................................................112 5.6 pci dma ..................................................................................................................... ......113 5.6.1 pci dma expansion protocol ..............................................................................113 5.6.2 pci dma expansion cycles ................................................................................114 5.6.3 dma addresses ...................................................................................................115 5.6.4 dma data generation .........................................................................................115 5.6.5 dma byte enable generation..............................................................................115 5.6.6 dma cycle termination .......................................................................................116 5.6.7 lpc dma .............................................................................................................116 5.6.8 asserting dma requests.....................................................................................116 5.6.9 abandoning dma requests ................................................................................117 5.6.10 general flow of dma transfers ..........................................................................117 5.6.11 terminal count ....................................................................................................118 5.6.12 verify mode..........................................................................................................118 5.6.13 dma request deassertion ..................................................................................118 5.6.14 sync field / ldrq# rules .................................................................................119 5.7 8254 timers (d31:f0).......................................................................................................1 20 5.7.1 timer programming .............................................................................................120 5.7.2 reading from the interval timer ..........................................................................121 5.7.2.1 simple read ........................................................................................122 5.7.2.2 counter latch command.....................................................................122 5.7.2.3 read back command..........................................................................122 5.8 8259 interrupt controllers (pic) (d31:f0) ........................................................................123 5.8.1 interrupt handling ................................................................................................124 5.8.1.1 generating interrupts ...........................................................................124 5.8.1.2 acknowledging interrupts.....................................................................124 5.8.1.3 hardware/software interrupt sequence...............................................125 5.8.2 initialization command words (icwx) .................................................................125 5.8.2.1 icw1 ....................................................................................................125 5.8.2.2 icw2 ....................................................................................................126 5.8.2.3 icw3 ....................................................................................................126 5.8.2.4 icw4 ....................................................................................................126 5.8.3 operation command words (ocw) ....................................................................126 5.8.4 modes of operation .............................................................................................126 5.8.4.1 fully nested mode ...............................................................................126 5.8.4.2 special fully-nested mode ..................................................................127 5.8.4.3 automatic rotation mode (equal priority devices) ..............................127 5.8.4.4 specific rotation mode (specific priority)............................................127 5.8.4.5 poll mode .............................................................................................127 8 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 5.8.4.6 cascade mode..................................................................................... 128 5.8.4.7 edge and level triggered mode.......................................................... 128 5.8.4.8 end of interrupt operations.................................................................. 128 5.8.4.9 normal end of interrupt........................................................................ 128 5.8.4.10 automatic end of interrupt mode ......................................................... 128 5.8.5 masking interrupts ............................................................................................... 129 5.8.5.1 masking on an individual interrupt request......................................... 129 5.8.5.2 special mask mode.............................................................................. 129 5.8.6 steering pci interrupts ........................................................................................ 129 5.9 advanced interrupt controller (apic) (d31:f0)................................................................ 130 5.9.1 interrupt handling ................................................................................................ 130 5.9.2 interrupt mapping................................................................................................. 130 5.9.3 pci message-based interrupts............................................................................ 131 5.9.3.1 registers and bits associated with pci interrupt delivery .................. 132 5.9.4 front side bus interrupt delivery......................................................................... 133 5.9.4.1 edge-triggered operation ................................................................... 133 5.9.4.2 level-triggered operation ................................................................... 133 5.9.4.3 registers associated with front side bus interrupt delivery............... 133 5.9.4.4 interrupt message format.................................................................... 133 5.10 serial interrupt (d31:f0) .................................................................................................. .135 5.10.1 start frame.......................................................................................................... 135 5.10.2 data frames ........................................................................................................ 136 5.10.3 stop frame .......................................................................................................... 136 5.10.4 specific interrupts not supported via serirq ................................................... 136 5.10.5 data frame format ............................................................................................. 137 5.11 real time clock (d31:f0) ................................................................................................ 137 5.11.1 update cycles ..................................................................................................... 138 5.11.2 interrupts.............................................................................................................. 1 38 5.11.3 lockable ram ranges ........................................................................................ 139 5.11.4 century rollover .................................................................................................. 139 5.11.5 clearing battery-backed rtc ram .................................................................... 139 5.12 processor interface (d31:f0) ........................................................................................... 141 5.12.1 processor interface signals................................................................................. 141 5.12.1.1 a20m# (mask a20) .............................................................................. 141 5.12.1.2 init# (initialization) .............................................................................. 141 5.12.1.3 ferr#/ignne# (numeric coprocessor error / ignore numeric error) .......................................................................... 142 5.12.1.4 nmi (non-maskable interrupt) ............................................................. 143 5.12.1.5 stop clock request and cpu sleep (stpclk# and cpuslp#) .................................................................. 143 5.12.1.6 cpu power good (cpupwrgood) .................................................. 143 5.12.2 dual-processor issues......................................................................................... 143 5.12.2.1 signal differences................................................................................ 143 5.12.2.2 power management............................................................................. 144 5.12.3 speed strapping for processor............................................................................ 144 5.13 power management (d31:f0) .......................................................................................... 146 5.13.1 features............................................................................................................... 14 6 5.13.2 intel ? ich5 and system power states ................................................................ 146 5.13.3 system power planes.......................................................................................... 148 5.13.4 intel ? ich5 power planes ................................................................................... 148 5.13.5 smi#/sci generation........................................................................................... 148 intel ? 82801eb ich5 / 82801er ich5r datasheet 9 contents 5.13.6 dynamic processor clock control .......................................................................150 5.13.6.1 throttling using stpclk#...................................................................151 5.13.6.2 transition rules among s0/cx and throttling states .........................151 5.13.7 sleep states ........................................................................................................151 5.13.7.1 sleep state overview ..........................................................................151 5.13.7.2 initiating sleep state ............................................................................152 5.13.7.3 exiting sleep states.............................................................................152 5.13.7.4 sx-g3-sx, handling power failures ....................................................154 5.13.8 thermal management..........................................................................................155 5.13.8.1 thrm# signal......................................................................................155 5.13.8.2 thrm# initiated passive cooling ........................................................155 5.13.8.3 thrm# override software bit .............................................................155 5.13.8.4 processor initiated passive cooling (via programmed duty cycle on stpclk#) .......................................156 5.13.8.5 active cooling ......................................................................................156 5.13.9 event input signals and their usage ..................................................................156 5.13.9.1 pwrbtn# (power button) ..................................................................156 5.13.9.2 ri# (ring indicator)..............................................................................157 5.13.9.3 pme# (pci power management event) ..............................................158 5.13.9.4 sys_reset# signal...........................................................................158 5.13.9.5 thrmtrip# signal .............................................................................158 5.13.10 alt access mode................................................................................................159 5.13.10.1 write only registers with read paths in alt access mode ............................................................................159 5.13.10.2 pic reserved bits................................................................................161 5.13.10.3 read only registers with write paths in alt access mode ............................................................................161 5.13.11 system power supplies, planes, and signals .....................................................161 5.13.11.1 power plane control with slp_s3#, slp_s4# and slp_s5#.......................................................................161 5.13.11.2 slp_s4# and suspend-to-ram sequencing .....................................162 5.13.11.3 pwrok signal ....................................................................................162 5.13.11.4 vrmpwrgd signal ............................................................................162 5.13.11.5 controlling leakage and power consumption during low-power states.....................................................................163 5.13.12 clock generators .................................................................................................163 5.13.13 legacy power management theory of operation ...............................................164 5.13.13.1 apm power management ....................................................................164 5.14 system management (d31:f0).........................................................................................164 5.14.1 theory of operation .............................................................................................165 5.14.1.1 detecting a system lockup .................................................................165 5.14.1.2 handling an intruder ............................................................................165 5.14.1.3 detecting improper flash bios programming ....................................165 5.14.1.4 handling an ecc error or other memory error ...................................166 5.14.2 heartbeat and event reporting via smbus ........................................................166 5.15 general purpose i/o ........................................................................................................ .170 5.15.1 gpio mapping .....................................................................................................170 5.15.2 power wells .........................................................................................................173 5.15.3 smi# and sci routing .........................................................................................173 5.16 ide controller (d31:f1) .................................................................................................... 174 5.16.1 pio transfers ......................................................................................................174 5.16.1.1 ide port decode ..................................................................................174 10 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 5.16.1.2 ide legacy mode and native mode .................................................... 175 5.16.1.3 pio ide timing modes ........................................................................ 176 5.16.1.4 iordy masking ................................................................................... 176 5.16.1.5 pio 32-bit ide data port accesses..................................................... 176 5.16.1.6 pio ide data port prefetching and posting ........................................ 177 5.16.2 bus master function............................................................................................ 177 5.16.2.1 physical region descriptor format ..................................................... 177 5.16.2.2 line buffer............................................................................................ 178 5.16.2.3 bus master ide timings ...................................................................... 178 5.16.2.4 interrupts.............................................................................................. 178 5.16.2.5 bus master ide operation ................................................................... 179 5.16.2.6 error conditions ................................................................................... 180 5.16.2.7 8237-like protocol ............................................................................... 180 5.16.3 ultra ata/33 protocol .......................................................................................... 181 5.16.3.1 signal descriptions .............................................................................. 181 5.16.3.2 operation ............................................................................................. 182 5.16.3.3 crc calculation .................................................................................. 182 5.16.4 ultra ata/66 protocol .......................................................................................... 183 5.16.5 ultra ata/100 protocol ........................................................................................ 183 5.16.6 ultra ata/33/66/100 timing ................................................................................ 183 5.16.7 ide swap bay...................................................................................................... 184 5.16.8 smi trapping (apm) ............................................................................................ 184 5.17 sata host controller (d31:f2) ........................................................................................ 185 5.17.1 theory of operation............................................................................................. 185 5.17.1.1 standard ata emulation ..................................................................... 185 5.17.1.2 48-bit lba operation ........................................................................... 185 5.17.2 hot swap operation ............................................................................................ 186 5.17.3 intel ? raid technology configuration (intel ? 82801er ich5r only)................ 186 5.17.3.1 intel ? raid technology option rom.................................................. 186 5.17.4 power management operation............................................................................ 186 5.17.4.1 power state mappings......................................................................... 186 5.17.4.2 power state transitions....................................................................... 187 5.17.4.3 smi trapping (apm) ............................................................................ 188 5.17.5 sata interrupts ................................................................................................... 188 5.18 high-precision event timers ............................................................................................ 188 5.18.1 timer accuracy.................................................................................................... 189 5.18.2 interrupt mapping................................................................................................. 189 5.18.3 periodic vs. non-periodic modes......................................................................... 189 5.18.4 enabling the timers............................................................................................. 191 5.18.5 interrupt levels .................................................................................................... 191 5.18.6 handling interrupts .............................................................................................. 191 5.18.7 issues related to 64-bit timers with 32-bit processors...................................... 191 5.19 usb uhci host controllers (d29:f0, f1, f2, and f3) ..................................................... 192 5.19.1 data structures in main memory ......................................................................... 192 5.19.1.1 frame list pointer................................................................................ 192 5.19.1.2 transfer descriptor (td) ...................................................................... 193 5.19.1.3 queue head (qh)................................................................................ 197 5.19.2 data transfers to/from main memory .................................................................. 198 5.19.2.1 executing the schedule ....................................................................... 198 5.19.2.2 processing transfer descriptors.......................................................... 199 5.19.2.3 command register, status register, and td status bit interaction ............................................................... 200 intel ? 82801eb ich5 / 82801er ich5r datasheet 11 contents 5.19.2.4 transfer queuing .................................................................................200 5.19.3 data encoding and bit stuffing ............................................................................204 5.19.4 bus protocol ........................................................................................................204 5.19.4.1 bit ordering..........................................................................................204 5.19.4.2 sync field ..........................................................................................204 5.19.4.3 packet field formats ...........................................................................205 5.19.4.4 address fields .....................................................................................206 5.19.4.5 frame number field ............................................................................206 5.19.4.6 data field.............................................................................................206 5.19.4.7 cyclic redundancy check (crc)........................................................206 5.19.5 packet formats....................................................................................................207 5.19.5.1 token packets .....................................................................................207 5.19.5.2 start of frame packets ........................................................................207 5.19.5.3 data packets........................................................................................208 5.19.5.4 handshake packets .............................................................................208 5.19.5.5 handshake responses........................................................................209 5.19.6 usb interrupts .....................................................................................................209 5.19.6.1 transaction based interrupts...............................................................209 5.19.6.2 non-transaction based interrupts .......................................................211 5.19.7 usb power management ....................................................................................212 5.19.8 usb legacy keyboard operation........................................................................212 5.20 usb ehci host controller (d29:f7).................................................................................215 5.20.1 ehc initialization .................................................................................................215 5.20.1.1 power on .............................................................................................215 5.20.1.2 bios initialization.................................................................................215 5.20.1.3 driver initialization................................................................................216 5.20.1.4 ehc resets .........................................................................................216 5.20.2 data structures in main memory .........................................................................216 5.20.3 usb 2.0 enhanced host controller dma ............................................................216 5.20.3.1 periodic list execution.........................................................................216 5.20.3.2 asynchronous list execution...............................................................218 5.20.4 data encoding and bit stuffing ............................................................................219 5.20.5 packet formats....................................................................................................219 5.20.6 usb 2.0 interrupts and error conditions .............................................................220 5.20.6.1 aborts on usb 2.0-initiated memory reads ........................................220 5.20.7 usb 2.0 power management ..............................................................................221 5.20.7.1 pause feature .....................................................................................221 5.20.7.2 suspend feature .................................................................................221 5.20.7.3 acpi device states .............................................................................221 5.20.7.4 acpi system states ............................................................................222 5.20.8 interaction with uhci host controllers ................................................................222 5.20.8.1 port-routing logic ...............................................................................223 5.20.8.2 device connects..................................................................................224 5.20.8.3 device disconnects .............................................................................225 5.20.8.4 effect of resets on port-routing logic ................................................225 5.20.9 usb 2.0 legacy keyboard operation..................................................................225 5.20.10 usb 2.0 based debug port .................................................................................226 5.20.10.1 theory of operation ............................................................................226 5.21 smbus controller (d31:f3) ..............................................................................................231 5.21.1 host controller .....................................................................................................231 5.21.1.1 command protocols ............................................................................232 5.21.1.2 i 2 c behavior.........................................................................................242 12 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 5.21.2 bus arbitration ..................................................................................................... 243 5.21.3 bus timing........................................................................................................... 243 5.21.3.1 clock stretching................................................................................... 243 5.21.3.2 bus time out (intel ? ich5 as smbus master) .................................... 243 5.21.4 interrupts / smi# .................................................................................................. 244 5.21.5 smbalert# ....................................................................................................... 245 5.21.6 smbus crc generation and checking............................................................... 245 5.21.7 smbus slave interface ........................................................................................ 245 5.21.7.1 format of slave write cycle ................................................................ 246 5.21.7.2 format of read command .................................................................. 248 5.21.7.3 format of host notify command ......................................................... 250 5.22 ac ?97 controller (audio d31:f5, modem d31:f6) .......................................................... 251 5.22.1 pci power management...................................................................................... 253 5.22.2 ac-link overview ................................................................................................ 253 5.22.2.1 ac-link output frame (sdout) ......................................................... 256 5.22.2.2 output slot 0: tag phase..................................................................... 256 5.22.2.3 output slot 1: command address port................................................ 256 5.22.2.4 output slot 2: command data port ..................................................... 257 5.22.2.5 output slot 3: pcm playback left channel ......................................... 257 5.22.2.6 output slot 4: pcm playback right channel....................................... 257 5.22.2.7 output slot 5: modem codec............................................................... 257 5.22.2.8 output slot 6: pcm playback center front channel........................... 257 5.22.2.9 output slots 7?8: pcm playback left and right rear channels..................................................................... 257 5.22.2.10 output slot 9: playback sub woofer channel ..................................... 258 5.22.2.11 output slots 10?11: reserved............................................................. 258 5.22.2.12 output slot 12: i/o control................................................................... 258 5.22.2.13 ac-link input frame (sdin)................................................................ 258 5.22.2.14 input slot 0: tag phase ....................................................................... 259 5.22.2.15 input slot 1: status address port / slot request bits .......................... 259 5.22.2.16 input slot 2: status data port .............................................................. 260 5.22.2.17 input slot 3: pcm record left channel............................................... 260 5.22.2.18 input slot 4: pcm record right channel ............................................ 260 5.22.2.19 input slot 5: modem line ..................................................................... 260 5.22.2.20 input slot 6: optional dedicated microphone record data......................................................................................... 261 5.22.2.21 input slots 7?11: reserved.................................................................. 261 5.22.2.22 input slot 12: i/o status....................................................................... 261 5.22.2.23 register access ................................................................................... 261 5.22.3 ac-link low power mode ................................................................................... 262 5.22.3.1 external wake event ........................................................................... 263 5.22.4 ac ?97 cold reset ............................................................................................... 264 5.22.5 ac ?97 warm reset ............................................................................................. 264 5.22.6 system reset ...................................................................................................... 264 5.22.7 hardware assist to determine ac_sdin used per codec ................................. 265 5.22.8 software mapping of ac_sdin to dma engine .................................................. 265 6 register and memory mapping ................................................................................................ 267 6.1 pci devices and functions .............................................................................................. 268 6.2 pci configuration map ..................................................................................................... 26 9 6.3 i/o map ..................................................................................................................... ........ 269 6.3.1 fixed i/o address ranges................................................................................... 269 intel ? 82801eb ich5 / 82801er ich5r datasheet 13 contents 6.3.2 variable i/o decode ranges ...............................................................................272 6.4 memory map .................................................................................................................. ...273 6.4.1 boot-block update scheme.................................................................................274 7 lan controller registers (b1:d8:f0) ......................................................................................275 7.1 pci configuration registers (lan controller?b1:d8:f0) .............................................................................................275 7.1.1 vid?vendor identification register (lan controller?b1:d8:f0) ................................................................................276 7.1.2 did?device identification register (lan controller?b1:d8:f0) ................................................................................276 7.1.3 pcicmd?pci command register (lan controller?b1:d8:f0) ................................................................................277 7.1.4 pcists?pci status register (lan controller?b1:d8:f0) ................................................................................278 7.1.5 rid?revision identification register (lan controller?b1:d8:f0) ................................................................................279 7.1.6 scc?sub-class code register (lan controller?b1:d8:f0) ................................................................................279 7.1.7 bcc?base-class code register (lan controller?b1:d8:f0) ................................................................................279 7.1.8 cls?cache line size register (lan controller?b1:d8:f0) ................................................................................280 7.1.9 pmlt?primary master latency timer register (lan controller?b1:d8:f0) ................................................................................280 7.1.10 headtyp?header type register (lan controller?b1:d8:f0) ................................................................................280 7.1.11 csr_mem_base ? csr memory-mapped base address register (lan controller?b1:d8:f0)..................................................................281 7.1.12 csr_io_base ? csr i/o-mapped base address register (lan controller?b1:d8:f0) ................................................................................281 7.1.13 svid ? subsystem vendor identification register (lan controller?b1:d8:f0) ................................................................................281 7.1.14 sid ? subsystem identification register (lan controller?b1:d8:f0) ................................................................................282 7.1.15 cap_ptr ? capabilities pointer register (lan controller?b1:d8:f0) ................................................................................282 7.1.16 int_ln ? interrupt line register (lan controller?b1:d8:f0) ................................................................................282 7.1.17 int_pn ? interrupt pin register (lan controller?b1:d8:f0) ................................................................................283 7.1.18 min_gnt ? minimum grant register (lan controller?b1:d8:f0) ................................................................................283 7.1.19 max_lat ? maximum latency register (lan controller?b1:d8:f0) ................................................................................283 7.1.20 cap_id ? capability identification register (lan controller?b1:d8:f0) ................................................................................283 7.1.21 nxt_ptr ? next item pointer register (lan controller?b1:d8:f0) ................................................................................284 7.1.22 pm_cap ? power management capabilities register (lan controller?b1:d8:f0) ................................................................................284 14 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 7.1.23 pmcsr ? power management control/status register (lan controller?b1:d8:f0) ................................................................................ 285 7.1.24 pcidata ? pci power management data register (lan controller?b1:d8:f0) ................................................................................ 286 7.2 lan control / status registers (csr) (lan controller?b1:d8:f0) ............................................................................................. 287 7.2.1 scb_sta?system control block status word register (lan controller?b1:d8:f0) ................................................................................ 288 7.2.2 scb_cmd?system control block command word register (lan controller?b1:d8:f0).................................................................. 289 7.2.3 scb_genpnt?system control block general pointer register (lan controller?b1:d8:f0).................................................................. 291 7.2.4 port?port interface register (lan controller?b1:d8:f0) ................................................................................ 291 7.2.5 eeprom_cntl?eeprom control register (lan controller?b1:d8:f0) ................................................................................ 292 7.2.6 mdi_cntl?management data interface (mdi) control register (lan controller?b1:d8:f0).................................................................. 293 7.2.7 rec_dma_bc?receive dma byte count register (lan controller?b1:d8:f0) ................................................................................ 293 7.2.8 erec_intr?early receive interrupt register (lan controller?b1:d8:f0) ................................................................................ 294 7.2.9 flow_cntl?flow control register (lan controller?b1:d8:f0) ................................................................................ 295 7.2.10 pmdr?power management driver register (lan controller?b1:d8:f0) ................................................................................ 296 7.2.11 gencntl?general control register (lan controller?b1:d8:f0) ................................................................................ 297 7.2.12 gensta?general status register (lan controller?b1:d8:f0) ................................................................................ 297 7.2.13 smb_pci?smb via pci register (lan controller?b1:d8:f0) ................................................................................ 298 7.2.14 statistical counters (lan controller?b1:d8:f0) ................................................................................ 299 8 hub interface to pci bridge registers (d30:f0) ..................................................................... 301 8.1 pci configuration registers (d30:f0) .............................................................................. 301 8.1.1 vid?vendor identification register (hub-pci?d30:f0) ............................................................................................ 302 8.1.2 did?device identification register (hub-pci?d30:f0) ............................................................................................ 302 8.1.3 pcicmd?pci command register (hub-pci?d30:f0) ............................................................................................ 303 8.1.4 pcists?pci status register (hub-pci?d30:f0) ............................................................................................ 304 8.1.5 rid?revision identification register (hub-pci?d30:f0) ............................................................................................ 305 8.1.6 scc?sub-class code register (hub-pci?d30:f0) ............................................................................................ 305 8.1.7 bcc?base-class code register (hub-pci?d30:f0) ............................................................................................ 305 intel ? 82801eb ich5 / 82801er ich5r datasheet 15 contents 8.1.8 pmlt?primary master latency timer register (hub-pci?d30:f0) ............................................................................................305 8.1.9 headtyp?header type register (hub-pci?d30:f0) ............................................................................................306 8.1.10 pbus_num?primary bus number register (hub-pci?d30:f0) ............................................................................................306 8.1.11 sbus_num?secondary bus number register (hub-pci?d30:f0) ............................................................................................306 8.1.12 sub_bus_num?subordinate bus number register (hub-pci?d30:f0) ............................................................................................306 8.1.13 smlt?secondary master latency timer register (hub-pci?d30:f0) ............................................................................................307 8.1.14 iobase?i/o base register (hub-pci?d30:f0) ............................................................................................307 8.1.15 iolim?i/o limit register (hub-pci?d30:f0) ............................................................................................307 8.1.16 secsts?secondary status register (hub-pci?d30:f0) ............................................................................................308 8.1.17 membase?memory base register (hub-pci?d30:f0) ............................................................................................309 8.1.18 memlim?memory limit register (hub-pci?d30:f0) ............................................................................................309 8.1.19 pref_mem_base?prefetchable memory base register (hub-pci?d30:f0) ............................................................................................309 8.1.20 pref_mem_mlt?prefetchable memory limit register (hub-pci?d30:f0) ............................................................................................310 8.1.21 iobase_hi?i/o base upper 16 bits register (hub-pci?d30:f0) ............................................................................................310 8.1.22 iolim_hi?i/o limit upper 16 bits register (hub-pci?d30:f0) ............................................................................................310 8.1.23 int_ln?interrupt line register (hub-pci?d30:f0) ............................................................................................310 8.1.24 bridge_cnt?bridge control register (hub-pci?d30:f0) ............................................................................................311 8.1.25 hi1_cmd?hub interface 1 command control register (hub-pci?d30:f0) ............................................................................................312 8.1.26 device_hide?secondary pci device hiding register (hub-pci?d30:f0) ............................................................................................313 8.1.27 cnf?policy configuration register (hub-pci?d30:f0) ............................................................................................314 8.1.28 mtt?multi-transaction timer register (hub-pci?d30:f0) ............................................................................................315 8.1.29 pci_mast_sts?pci master status register (hub-pci?d30:f0) ............................................................................................315 8.1.30 err_cmd?error command register (hub-pci?d30:f0) ............................................................................................316 8.1.31 err_sts?error status register (hub-pci?d30:f0) ............................................................................................316 16 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 9 lpc interface bridge registers (d31:f0) ................................................................................ 317 9.1 pci configuration registers (lpc i/f?d31:f0) .............................................................. 317 9.1.1 vid?vendor identification register (lpc i/f?d31:f0)............................................................................................... 318 9.1.2 did?device identification register (lpc i/f?d31:f0)............................................................................................... 318 9.1.3 pcicmd?pci command register (lpc i/f?d31:f0)............................................................................................... 319 9.1.4 pcists?pci status register (lpc i/f?d31:f0)............................................................................................... 320 9.1.5 rid?revision identification register (lpc i/f?d31:f0)............................................................................................... 321 9.1.6 pi?programming interface register (lpc i/f?d31:f0)............................................................................................... 321 9.1.7 scc?sub class code register (lpc i/f?d31:f0)............................................................................................... 321 9.1.8 bcc?base class code register (lpc i/f?d31:f0)............................................................................................... 321 9.1.9 headtyp?header type register (lpc i/f?d31:f0)............................................................................................... 322 9.1.10 pmbase?acpi base address register (lpc i/f?d31:f0)............................................................................................... 322 9.1.11 acpi_cntl?acpi control register (lpc i/f ? d31:f0)............................................................................................. 323 9.1.12 bios_cntl?bios control register (lpc i/f?d31:f0)............................................................................................... 324 9.1.13 tco_cntl ? tco control register (lpc i/f ? d31:f0)............................................................................................. 324 9.1.14 gpio_base?gpio base address register (lpc i/f?d31:f0)............................................................................................... 325 9.1.15 gpio_cntl?gpio control register (lpc i/f?d31:f0)............................................................................................... 325 9.1.16 pirq[n]_rout?pirq[a,b,c,d] routing control register (lpc i/f?d31:f0)............................................................................................... 326 9.1.17 sirq_cntl?serial irq control register (lpc i/f?d31:f0)............................................................................................... 327 9.1.18 pirq[n]_rout?pirq[e,f,g,h] routing control register (lpc i/f?d31:f0)............................................................................................... 328 9.1.19 d31_err_cfg?device 31 error configuration register (lpc i/f?d31:f0)............................................................................................... 328 9.1.20 d31_err_sts?device 31 error status register (lpc i/f?d31:f0)............................................................................................... 329 9.1.21 pci_dma_cfg?pci dma configuration register (lpc i/f?d31:f0)............................................................................................... 329 9.1.22 gen_cntl ? general control register (lpc i/f ? d31:f0)............................................................................................. 330 9.1.23 gen_sta?general status register (lpc i/f?d31:f0)............................................................................................... 332 9.1.24 back_cntl?backed up control register (lpc i/f?d31:f0)............................................................................................... 333 9.1.25 rtc_conf?real time clock configuration register (lpc i/f?d31:f0)............................................................................................... 334 intel ? 82801eb ich5 / 82801er ich5r datasheet 17 contents 9.1.26 com_dec?lpc i/f communication port decode ranges register (lpc i/f?d31:f0).................................................................................335 9.1.27 lpcfdd_dec?lpc i/f fdd and lpt decode ranges register (lpc i/f?d31:f0).................................................................................335 9.1.28 fb_dec_en1?flash bios decode enable 1 register (lpc i/f?d31:f0) ...............................................................................................336 9.1.29 gen1_dec?lpc i/f generic decode range 1 register (lpc i/f?d31:f0) ...............................................................................................337 9.1.30 lpc_en?lpc i/f enables register (lpc i/f?d31:f0) ...............................................................................................337 9.1.31 fb_sel1?flash bios select 1 register (lpc i/f?d31:f0) ...............................................................................................339 9.1.32 gen2_dec?lpc i/f generic decode range 2 register (lpc i/f?d31:f0) ...............................................................................................340 9.1.33 fb_sel2?flash bios select 2 register (lpc i/f?d31:f0) ...............................................................................................340 9.1.34 fb_dec_en2?flash bios decode enable 2 register (lpc i/f?d31:f0) ...............................................................................................341 9.1.35 func_dis?function disable register (lpc i/f?d31:f0) ...............................................................................................342 9.2 dma i/o registers (lpc i/f?d31:f0) .............................................................................344 9.2.1 dmabase_ca?dma base and current address registers (lpc i/f?d31:f0) ...............................................................................................345 9.2.2 dmabase_cc?dma base and current count registers (lpc i/f?d31:f0) ...............................................................................................346 9.2.3 dmamem_lp?dma memory low page registers (lpc i/f?d31:f0) ...............................................................................................346 9.2.4 dmacmd?dma command register (lpc i/f?d31:f0) ...............................................................................................347 9.2.5 dmasta?dma status register (lpc i/f?d31:f0) ...............................................................................................347 9.2.6 dma_wrsmsk?dma write single mask register (lpc i/f?d31:f0) ...............................................................................................348 9.2.7 dmach_mode?dma channel mode register (lpc i/f?d31:f0) ...............................................................................................349 9.2.8 dma clear byte pointer register (lpc i/f?d31:f0) ...............................................................................................349 9.2.9 dma master clear register (lpc i/f?d31:f0) ...............................................................................................350 9.2.10 dma_clmsk?dma clear mask register (lpc i/f?d31:f0) ...............................................................................................350 9.2.11 dma_wrmsk?dma write all mask register (lpc i/f?d31:f0) ...............................................................................................350 9.3 timer i/o registers (lpc i/f?d31:f0)............................................................................351 9.3.1 tcw?timer control word register (lpc i/f?d31:f0) ...............................................................................................352 9.3.1.1 rdbk_cmd?read back command (lpc i/f?d31:f0) ...............................................................................353 9.3.1.2 ltch_cmd?counter latch command (lpc i/f?d31:f0) ...............................................................................353 9.3.2 sbyte_fmt?interval timer status byte format register (lpc i/f?d31:f0) ...............................................................................................354 18 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 9.3.3 counter access ports register (lpc i/f?d31:f0)............................................................................................... 355 9.4 8259 interrupt controller (pic) registers (lpc i/f?d31:f0)............................................................................................................ 355 9.4.1 interrupt controller i/o map (lpc i/f?d31:f0) ................................................. 355 9.4.2 icw1?initialization command word 1 register (lpc i/f?d31:f0)............................................................................................... 356 9.4.3 icw2?initialization command word 2 register (lpc i/f?d31:f0)............................................................................................... 357 9.4.4 icw3?master controller initialization command word 3 register (lpc i/f?d31:f0) ................................................................................ 357 9.4.5 icw3?slave controller initialization command word 3 register (lpc i/f?d31:f0) ................................................................................ 358 9.4.6 icw4?initialization command word 4 register (lpc i/f?d31:f0)............................................................................................... 358 9.4.7 ocw1?operational control word 1 (interrupt mask) register (lpc i/f?d31:f0) ................................................................................ 359 9.4.8 ocw2?operational control word 2 register (lpc i/f?d31:f0)............................................................................................... 359 9.4.9 ocw3?operational control word 3 register (lpc i/f?d31:f0)............................................................................................... 360 9.4.10 elcr1?master controller edge/level triggered register (lpc i/f?d31:f0)............................................................................................... 361 9.4.11 elcr2?slave controller edge/level triggered register (lpc i/f?d31:f0)............................................................................................... 362 9.5 advanced interrupt controller (apic)(d31:f0)................................................................. 363 9.5.1 apic register map (lpc i/f?d31:f0)............................................................................................... 363 9.5.2 ind?index register (lpc i/f?d31:f0)............................................................................................... 363 9.5.3 dat?data register (lpc i/f?d31:f0)............................................................................................... 364 9.5.4 irqpa?irq pin assertion register (lpc i/f?d31:f0)............................................................................................... 364 9.5.5 eoir?eoi register (lpc i/f?d31:f0)............................................................................................... 365 9.5.6 id?identification register (lpc i/f?d31:f0)............................................................................................... 365 9.5.7 ver?version register (lpc i/f?d31:f0)............................................................................................... 366 9.5.8 redir_tbl?redirection table (lpc i/f?d31:f0)............................................................................................... 367 9.6 real time clock registers (lpc i/f?d31:f0) ................................................................ 369 9.6.1 i/o register address map (lpc i/f?d31:f0) .................................................... 369 9.6.2 rtc_rega?register a (lpc i/f?d31:f0)............................................................................................... 370 9.6.3 rtc_regb?register b (general configuration) (lpc i/f?d31:f0)............................................................................................... 371 9.6.4 rtc_regc?register c (flag register) (lpc i/f?d31:f0)............................................................................................... 372 9.6.5 rtc_regd?register d (flag register) (lpc i/f?d31:f0)............................................................................................... 372 intel ? 82801eb ich5 / 82801er ich5r datasheet 19 contents 9.7 processor interface registers (lpc i/f?d31:f0) ...........................................................373 9.7.1 nmi_sc?nmi status and control register (lpc i/f?d31:f0) ...............................................................................................373 9.7.2 nmi_en?nmi enable (and real time clock index) register (lpc i/f?d31:f0) ...............................................................................................374 9.7.3 port92?fast a20 and init register (lpc i/f?d31:f0) ...............................................................................................374 9.7.4 coproc_err?coprocessor error register (lpc i/f?d31:f0) ...............................................................................................375 9.7.5 rst_cnt?reset control register (lpc i/f?d31:f0) ...............................................................................................375 9.8 power management pci configuration registers (pm?d31:f0)...................................................................................................................3 76 9.8.1 gen_pmcon_1?general pm configuration 1 register (pm?d31:f0)......................................................................................................377 9.8.2 gen_pmcon_2?general pm configuration 2 register (pm?d31:f0)......................................................................................................378 9.8.3 gen_pmcon_3?general pm configuration 3 register (pm?d31:f0)......................................................................................................379 9.8.4 stpclk_del?stop clock delay register (pm?d31:f0)......................................................................................................380 9.8.5 usb_tdd?usb transient disconnect detect (pm?d31:f0)......................................................................................................380 9.8.6 sata_rd_cfg?sata raid configuration (pm?d31:f0) - (intel ? 82801er ich5r only) ...................................................380 9.8.7 gpi_rout?gpi routing control register (pm?d31:f0)......................................................................................................381 9.8.8 trp_fwd_en?io monitor trap forwarding enable register (pm?d31:f0) .......................................................................................382 9.8.9 mon[n]_trp_rng?i/o monitor [4:7] trap range register for devices 4?7 (pm?d31:f0)............................................................................383 9.8.10 mon_trp_msk?i/o monitor trap range mask register for devices 4?7 (pm?d31:f0)............................................................................383 9.9 apm i/o decode .............................................................................................................. .384 9.9.1 apm_cnt?advanced power management control port register ...............................................................................................................384 9.9.2 apm_sts?advanced power management status port register ...............................................................................................................384 9.10 power management i/o registers....................................................................................385 9.10.1 pm1_sts?power management 1 status register ............................................386 9.10.2 pm1_en?power management 1 enable register .............................................388 9.10.3 pm1_cnt?power management 1 control.........................................................389 9.10.4 pm1_tmr?power management 1 timer register ............................................390 9.10.5 proc_cnt?processor control register ..........................................................390 9.10.6 gpe0_sts?general purpose event 0 status register.....................................392 9.10.7 gpe0_en?general purpose event 0 enables register ....................................394 9.10.8 smi_en?smi control and enable register .......................................................396 9.10.9 smi_sts?smi status register ..........................................................................398 9.10.10 alt_gp_smi_en?alternate gpi smi enable register.....................................400 9.10.11 alt_gp_smi_sts?alternate gpi smi status register....................................400 9.10.12 mon_smi?device monitor smi status and enable register ............................400 9.10.13 devact_sts ? device activity status register...............................................401 20 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 9.10.14 devtrap_en?device trap enable register ................................................... 402 9.11 system management tco registers (d31:f0)................................................................ 403 9.11.1 tco_rld?tco timer reload and current value register.............................. 403 9.11.2 tco_tmr?tco timer initial value register .................................................... 404 9.11.3 tco_dat_in?tco data in register ................................................................ 404 9.11.4 tco_dat_out?tco data out register ......................................................... 404 9.11.5 tco1_sts?tco1 status register ................................................................... 405 9.11.6 tco2_sts?tco2 status register ................................................................... 406 9.11.7 tco1_cnt?tco1 control register.................................................................. 407 9.11.8 tco2_cnt?tco2 control register.................................................................. 408 9.11.9 tco_message1 and tco_message2 registers.......................................... 408 9.11.10 tco_wdsts?tco watchdog status register ................................................ 408 9.11.11 sw_irq_gen?software irq generation register .......................................... 409 9.12 general purpose i/o registers (d31:f0) ......................................................................... 409 9.12.1 gpio_use_sel?gpio use select register .................................................... 410 9.12.2 gp_io_sel?gpio input/output select register .............................................. 410 9.12.3 gp_lvl?gpio level for input or output register ............................................ 411 9.12.4 gpo_blink?gpo blink enable register ......................................................... 411 9.12.5 gpi_inv?gpio signal invert register............................................................... 412 9.12.6 gpio_use_sel2?gpio use select 2 register ............................................... 412 9.12.7 gp_io_sel2?gpio input/output select 2 register ......................................... 413 9.12.8 gp_lvl2?gpio level for input or output 2 register ....................................... 414 10 ide controller registers (d31:f1) ............................................................................................ 415 10.1 pci configuration registers (ide?d31:f1) .................................................................... 415 10.1.1 vid?vendor identification register (ide?d31:f0) ..................................................................................................... 416 10.1.2 did?device identification register (ide?d31:f0) ..................................................................................................... 416 10.1.3 pcicmd?pci command register (ide?d31:f1) ..................................................................................................... 417 10.1.4 pcists ? pci status register (ide?d31:f1) ..................................................................................................... 418 10.1.5 rid?revision identification register (ide?d31:f1) ..................................................................................................... 419 10.1.6 pi?programming interface register (ide?d31:f1) ..................................................................................................... 419 10.1.7 scc?sub class code register (ide?d31:f1) ..................................................................................................... 419 10.1.8 bcc?base class code register (ide?d31:f1) ..................................................................................................... 420 10.1.9 pmlt?primary master latency timer register (ide?d31:f1) ..................................................................................................... 420 10.1.10 pcmd_bar?primary command block base address register (ide?d31:f1)....................................................................................... 420 10.1.11 pcnl_bar?primary control block base address register (ide?d31:f1) ..................................................................................................... 421 10.1.12 scmd_bar?secondary command block base address register (ide d31:f1) ......................................................................................... 421 10.1.13 scnl_bar?secondary control block base address register (ide d31:f1) ......................................................................................... 421 intel ? 82801eb ich5 / 82801er ich5r datasheet 21 contents 10.1.14 bm_base ? bus master base address register (ide?d31:f1) .....................................................................................................422 10.1.15 ide_svid ? subsystem vendor identification (ide?d31:f1) .....................................................................................................422 10.1.16 ide_sid ? subsystem identification register (ide?d31:f1) .....................................................................................................422 10.1.17 intr_ln?interrupt line register (ide?d31:f1) .....................................................................................................423 10.1.18 intr_pn?interrupt pin register (ide?d31:f1) .....................................................................................................423 10.1.19 ide_tim ? ide timing register (ide?d31:f1) .....................................................................................................424 10.1.20 slv_idetim?slave (drive 1) ide timing register (ide?d31:f1) .....................................................................................................425 10.1.21 sdma_cnt?synchronous dma control register (ide?d31:f1) .....................................................................................................427 10.1.22 sdma_tim?synchronous dma timing register (ide?d31:f1) .....................................................................................................428 10.1.23 ide_config?ide i/o configuration register (ide?d31:f1) .....................................................................................................429 10.2 bus master ide i/o registers (ide?d31:f1) ..................................................................430 10.2.1 bmic[p,s]?bus master ide command register (ide?d31:f1) .....................................................................................................431 10.2.2 bmis[p,s]?bus master ide status register (ide?d31:f1) .....................................................................................................432 10.2.3 bmid[p,s]?bus master ide descriptor table pointer register (ide?d31:f1).......................................................................................432 11 sata controller registers (d31:f2) ........................................................................................433 11.1 pci configuration registers (sata?d31:f2)...................................................................433 11.1.1 vid?vendor identification register (sata?d31:f2)..................................................................................................434 11.1.2 did?device identification register (sata?d31:f2)..................................................................................................434 11.1.3 pcicmd?pci command register (sata?d31:f2) ...................................................................................................435 11.1.4 pcists ? pci status register (sata?d31:f2) ...................................................................................................436 11.1.5 rid?revision identification register (sata?d31:f2)..................................................................................................437 11.1.6 pi?programming interface register (sata?d31:f2) ...................................................................................................437 11.1.7 scc?sub class code register (sata?d31:f2) ...................................................................................................437 11.1.8 bcc?base class code register (sata?d31:f2) ...................................................................................................438 11.1.9 pmlt?primary master latency timer register (sata?d31:f2) ...................................................................................................438 11.1.10 pcmd_bar?primary command block base address register (sata?d31:f2) .....................................................................................438 11.1.11 pcnl_bar?primary control block base address register (sata?d31:f2) ...................................................................................................439 22 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 11.1.12 scmd_bar?secondary command block base address register (ide d31:f1) ......................................................................................... 439 11.1.13 scnl_bar?secondary control block base address register (ide d31:f1) ......................................................................................... 439 11.1.14 bar ? legacy bus master base address register (sata?d31:f2) ................................................................................................... 440 11.1.15 svid?subsystem vendor identification register (sata?d31:f2) ................................................................................................... 440 11.1.16 sid?subsystem identification register (sata?d31:f2) ................................................................................................... 440 11.1.17 cap?capabilities pointer register (sata?d31:f2) ................................................................................................... 441 11.1.18 int_ln?interrupt line register (sata?d31:f2) ................................................................................................... 441 11.1.19 int_pn?interrupt pin register (sata?d31:f2) ................................................................................................... 441 11.1.20 ide_tim ? ide timing register (sata?d31:f2) ................................................................................................... 442 11.1.21 sidetim?slave ide timing register (sata?d31:f2) ................................................................................................... 444 11.1.22 sdma_cnt?synchronous dma control register (sata?d31:f2) ................................................................................................... 445 11.1.23 sdma_tim?synchronous dma timing register (sata?d31:f2) ................................................................................................... 446 11.1.24 ide_config?ide i/o configuration register (sata?d31:f2) ................................................................................................... 447 11.1.25 pid?pci power management capability identification register (sata?d31:f2)..................................................................................... 448 11.1.26 pc?pci power management capabilities register (sata?d31:f2) ................................................................................................... 448 11.1.27 pmcs?pci power management control and status register (sata?d31:f2)..................................................................................... 449 11.1.28 mid?message signaled interrupt identifiers register (sata?d31:f2) ................................................................................................... 449 11.1.29 mc?message signaled interrupt message control register (sata?d31:f2)..................................................................................... 450 11.1.30 ma?message signaled interrupt message address register (sata?d31:f2)..................................................................................... 450 11.1.31 md?message signaled interrupt message data register (sata?d31:f2) ................................................................................................... 450 11.1.32 map?address map register (sata?d31:f2) ................................................................................................... 451 11.1.33 pcs?port control and status register (sata?d31:f2) ................................................................................................... 451 11.1.34 sri?sata registers index (sata?d31:f2) ................................................................................................... 452 11.1.35 srd?sata registers data (sata?d31:f2) ................................................................................................... 452 11.1.36 sira?sata initialization register a (sata?d31:f2) ....................................... 452 11.1.37 sirb ? sata initialization register b (sata?d31:f2) ..................................... 453 11.1.38 pmr0 ? power management register port 0 (sata?d31:f2) ................................................................................................... 453 intel ? 82801eb ich5 / 82801er ich5r datasheet 23 contents 11.1.39 pmr1 ? power management register port 1 (sata?d31:f2) ...................................................................................................453 11.1.40 bfcs?bist fis control/status register (sata?d31:f2) ...................................................................................................454 11.1.41 bftd1?bist fis transmit data1 register (sata?d31:f2) ...................................................................................................455 11.1.42 bftd2?bist fis transmit data2 register (sata?d31:f2) ...................................................................................................455 11.2 bus master ide i/o registers (d31:f2) ...........................................................................456 11.2.1 bmic[p,s]?bus master ide command register (d31:f2)...............................................................................................................457 11.2.2 bmis[p,s]?bus master ide status register (d31:f2)...............................................................................................................458 11.2.3 bmid[p,s]?bus master ide descriptor table pointer register (d31:f2) ................................................................................................459 12 uhci controllers registers ......................................................................................................461 12.1 pci configuration registers (usb?d29:f0/f1/f2/f3) .................................................................................................461 12.1.1 vid?vendor identification register (usb?d29:f0/f1/f2/f3) ....................................................................................462 12.1.2 did?device identification register (usb?d29:f0/f1/f2/f3) ....................................................................................462 12.1.3 pcicmd?pci command register (usb?d29:f0/f1/f2/f3) ....................................................................................462 12.1.4 pcists?pci status register (usb?d29:f0/f1/f2/f3) ....................................................................................463 12.1.5 rid?revision identification register (usb?d29:f0/f1/f2/f3) ....................................................................................463 12.1.6 pi?programming interface register (usb?d29:f0/f1/f2/f3) ....................................................................................464 12.1.7 scc?sub class code register (usb?d29:f0/f1/f2/f3) ....................................................................................464 12.1.8 bcc?base class code register (usb?d29:f0/f1/f2/f3) ....................................................................................464 12.1.9 headtyp?header type register (usb?d29:f0/f1/f2/f3) ....................................................................................465 12.1.10 base?base address register (usb?d29:f0/f1/f2/f3) ....................................................................................465 12.1.11 svid ? subsystem vendor identification register (usb?d29:f0/f1/f2/f3) ....................................................................................466 12.1.12 sid ? subsystem identification register (usb?d29:f0/f1/f2/f3) ....................................................................................466 12.1.13 int_ln?interrupt line register (usb?d29:f0/f1/f2/f3) ....................................................................................466 12.1.14 int_pn?interrupt pin register (usb?d29:f0/f1/f2/f3) ....................................................................................467 12.1.15 usb_relnum?serial bus release number register (usb?d29:f0/f1/f2/f3) ....................................................................................467 12.1.16 usb_legkey?usb legacy keyboard/mouse control register (usb?d29:f0/f1/f2/f3)......................................................................468 24 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 12.1.17 usb_res?usb resume enable register (usb?d29:f0/f1/f2/f3) .................................................................................... 470 12.2 usb i/o registers .......................................................................................................... .. 470 12.2.1 usbcmd?usb command register .................................................................. 471 12.2.2 usbsts?usb status register.......................................................................... 474 12.2.3 usbintr?usb interrupt enable register ......................................................... 475 12.2.4 frnum?frame number register...................................................................... 475 12.2.5 frbaseadd?frame list base address register ............................................ 476 12.2.6 sofmod?start of frame modify register ........................................................ 476 12.2.7 portsc[0,1]?port status and control register ............................................... 477 13 ehci controller registers (d29:f7) ......................................................................................... 479 13.1 usb ehci configuration registers (usb ehci?d29:f7) ....................................................................................................... 479 13.1.1 vid?vendor identification register (usb ehci?d29:f7) .......................................................................................... 480 13.1.2 did?device identification register (usb ehci?d29:f7) .......................................................................................... 480 13.1.3 pcicmd?pci command register (usb ehci?d29:f7) .......................................................................................... 481 13.1.4 pcists?pci status register (usb ehci?d29:f7) .......................................................................................... 482 13.1.5 rid?revision identification register (usb ehci?d29:f7) .......................................................................................... 483 13.1.6 pi?programming interface register (usb ehci?d29:f7) .......................................................................................... 483 13.1.7 scc?sub class code register (usb ehci?d29:f7) .......................................................................................... 483 13.1.8 bcc?base class code register (usb ehci?d29:f7) .......................................................................................... 483 13.1.9 pmlt?primary master latency timer register (usb ehci?d29:f7) .......................................................................................... 484 13.1.10 mem_base?memory base address register (usb ehci?d29:f7) .......................................................................................... 484 13.1.11 svid?usb ehci subsystem vendor id register (usb ehci?d29:f7) .......................................................................................... 484 13.1.12 sid?usb ehci subsystem id register (usb ehci?d29:f7) .......................................................................................... 485 13.1.13 cap_ptr?capabilities pointer register (usb ehci?d29:f7) .......................................................................................... 485 13.1.14 int_ln?interrupt line register (usb ehci?d29:f7) .......................................................................................... 485 13.1.15 int_pn?interrupt pin register (usb ehci?d29:f7) .......................................................................................... 485 13.1.16 pwr_capid?pci power management capability id register (usb ehci?d29:f7)............................................................................ 486 13.1.17 nxt_ptr1?next item pointer #1 register (usb ehci?d29:f7) .......................................................................................... 486 13.1.18 pwr_cap?power management capabilities register (usb ehci?d29:f7) .......................................................................................... 487 13.1.19 pwr_cntl_sts?power management control/status register (usb ehci?d29:f7)............................................................................ 488 intel ? 82801eb ich5 / 82801er ich5r datasheet 25 contents 13.1.20 debug_capid?debug port capability id register (usb ehci?d29:f7) ..........................................................................................488 13.1.21 nxt_ptr2?next item pointer #2 register (usb ehci?d29:f7) ..........................................................................................489 13.1.22 debug_base?debug port base offset register (usb ehci?d29:f7) ..........................................................................................489 13.1.23 usb_relnum?usb release number register (usb ehci?d29:f7) ..........................................................................................489 13.1.24 fl_adj?frame length adjustment register (usb ehci?d29:f7) ..........................................................................................490 13.1.25 pwake_cap?port wake capability register (usb ehci?d29:f7) ..........................................................................................491 13.1.26 leg_ext_cap?usb ehci legacy support extended capability register (usb ehci?d29:f7) ...........................................................491 13.1.27 leg_ext_cs?usb ehci legacy support extended control / status register (usb ehci?d29:f7) ..................................................492 13.1.28 special_smi?intel specific usb 2.0 smi register (usb ehci?d29:f7) ..........................................................................................493 13.1.29 access_cntl?access control register (usb ehci?d29:f7) ..........................................................................................495 13.2 memory-mapped i/o registers.........................................................................................496 13.2.1 caplength?capability registers length register .........................................496 13.2.2 hciversion?host controller interface version number register ...............................................................................................................497 13.2.3 hcsparams?host controller structural parameters.......................................497 13.2.4 hccparams?host controller capability parameters register ...............................................................................................................498 13.2.5 usb2.0_cmd?usb 2.0 command register .....................................................500 13.2.6 usb2.0_sts?usb 2.0 status register .............................................................502 13.2.7 usb2.0_intr?usb 2.0 interrupt enable register ............................................504 13.2.8 frindex?frame index register .......................................................................505 13.2.9 ctrldssegment?control data structure segment register ...............................................................................................................506 13.2.10 periodiclistbase?periodic frame list base address register ...............................................................................................................506 13.2.11 asynclistaddr?current asynchronous list address register ...............................................................................................................507 13.2.12 configflag?configure flag register ............................................................507 13.2.13 portsc?port n status and control register ...................................................508 13.2.14 cntl_sts?control/status register..................................................................512 13.2.15 usbpid?usb pids register .............................................................................514 13.2.16 databuf[7:0]?data buffer bytes[7:0] register ................................................514 13.2.17 config?configuration register........................................................................514 14 smbus controller registers (d31:f3) .....................................................................................515 14.1 pci configuration registers (smbus?d31:f3)..............................................................515 14.1.1 vid?vendor identification register (smbus?d31:f3) ..............................................................................................515 14.1.2 did?device identification register (smbus?d31:f3) ..............................................................................................516 14.1.3 pcicmd?pci command register (smbus?d31:f3) ..............................................................................................516 26 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 14.1.4 pcists?pci status register (smbus?d31:f3) .............................................................................................. 517 14.1.5 rid?revision identification register (smbus?d31:f3) .............................................................................................. 517 14.1.6 scc?sub class code register (smbus?d31:f3) .............................................................................................. 518 14.1.7 bcc?base class code register (smbus?d31:f3) .............................................................................................. 518 14.1.8 smb_base?smbus base address register (smbus?d31:f3) .............................................................................................. 518 14.1.9 svid ? subsystem vendor identification register (smbus?d31:f2/f4) ......................................................................................... 518 14.1.10 sid ? subsystem identification register (smbus?d31:f2/f4) ......................................................................................... 519 14.1.11 int_ln?interrupt line register (smbus?d31:f3) .............................................................................................. 519 14.1.12 int_pn?interrupt pin register (smbus?d31:f3) .............................................................................................. 519 14.1.13 hostc?host configuration register (smbus?d31:f3) .............................................................................................. 520 14.2 smbus i/o registers ........................................................................................................ 521 14.2.1 hst_sts?host status register (smbus?d31:f3) .............................................................................................. 522 14.2.2 hst_cnt?host control register (smbus?d31:f3) .............................................................................................. 523 14.2.3 hst_cmd?host command register (smbus?d31:f3) .............................................................................................. 525 14.2.4 xmit_slva?transmit slave address register (smbus?d31:f3) .............................................................................................. 525 14.2.5 hst_d0?host data 0 register (smbus?d31:f3) .............................................................................................. 525 14.2.6 hst_d1?host data 1 register (smbus?d31:f3) .............................................................................................. 525 14.2.7 host_block_db?host block data byte register (smbus?d31:f3) .............................................................................................. 526 14.2.8 pec?packet error check (pec) register (smbus?d31:f3) .............................................................................................. 526 14.2.9 rcv_slva?receive slave address register (smbus?d31:f3) .............................................................................................. 527 14.2.10 slv_data?receive slave data register (smbus?d31:f3) .............................................................................................. 527 14.2.11 aux_sts?auxiliary status register (smbus?d31:f3) .............................................................................................. 527 14.2.12 aux_ctl?auxiliary control register (smbus?d31:f3) .............................................................................................. 528 14.2.13 smlink_pin_ctl?smlink pin control register (smbus?d31:f3) .............................................................................................. 528 14.2.14 smbus_pin_ctl?smbus pin control register (smbus?d31:f3) .............................................................................................. 529 14.2.15 slv_sts?slave status register (smbus?d31:f3) .............................................................................................. 529 intel ? 82801eb ich5 / 82801er ich5r datasheet 27 contents 14.2.16 slv_cmd?slave command register (smbus?d31:f3) ..............................................................................................530 14.2.17 notify_daddr?notify device address register (smbus?d31:f3) ..............................................................................................530 14.2.18 notify_dlow?notify data low byte register (smbus?d31:f3) ..............................................................................................531 14.2.19 notify_dhigh?notify data high byte register (smbus?d31:f3) ..............................................................................................531 15 ac ?97 audio controller registers (d31:f5) ...........................................................................533 15.1 ac ?97 audio pci configuration space (audio? d31:f5) ..............................................................................................................53 3 15.1.1 vid?vendor identification register (audio?d31:f5) ..................................................................................................534 15.1.2 did?device identification register (audio?d31:f5) ..................................................................................................534 15.1.3 pcicmd?pci command register (audio?d31:f5) ..................................................................................................535 15.1.4 pcists?pci status register (audio?d31:f5) ..................................................................................................536 15.1.5 rid?revision identification register (audio?d31:f5) ..................................................................................................537 15.1.6 pi?programming interface register (audio?d31:f5) ..................................................................................................537 15.1.7 scc?sub class code register (audio?d31:f5) ..................................................................................................537 15.1.8 bcc?base class code register (audio?d31:f5) ..................................................................................................537 15.1.9 headtyp?header type register (audio?d31:f5) ..................................................................................................538 15.1.10 nambar?native audio mixer base address register (audio?d31:f5) ..................................................................................................538 15.1.11 nabmbar?native audio bus mastering base address register (audio?d31:f5) ...................................................................................539 15.1.12 mmbar?mixer base address register (audio?d31:f5) ..................................................................................................539 15.1.13 mbbar?bus master base address register (audio?d31:f5) ..................................................................................................540 15.1.14 svid?subsystem vendor identification register (audio?d31:f5) ..................................................................................................540 15.1.15 sid?subsystem identification register (audio?d31:f5) ..................................................................................................541 15.1.16 cap_ptr?capabilities pointer register (audio?d31:f5) ..................................................................................................541 15.1.17 int_ln?interrupt line register (audio?d31:f5) ..................................................................................................541 15.1.18 int_pn?interrupt pin register (audio?d31:f5) ..................................................................................................542 15.1.19 pcid?programmable codec identification register (audio?d31:f5) ..................................................................................................542 15.1.20 cfg?configuration register (audio?d31:f5) ..................................................................................................543 28 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 15.1.21 pid?pci power management capability identification register (audio?d31:f5) ................................................................................... 543 15.1.22 pc?power management capabilities register (audio?d31:f5).................................................................................................. 544 15.1.23 pcs?power management control and status register (audio?d31:f5).................................................................................................. 545 15.2 ac ?97 audio i/o space (d31:f5)..................................................................................... 546 15.2.1 x_bdbar?buffer descriptor base address register (audio?d31:f5).................................................................................................. 549 15.2.2 x_civ?current index value register (audio?d31:f5).................................................................................................. 550 15.2.3 x_lvi?last valid index register (audio?d31:f5).................................................................................................. 550 15.2.4 x_sr?status register (audio?d31:f5).................................................................................................. 551 15.2.5 x_picb?position in current buffer register (audio?d31:f5).................................................................................................. 552 15.2.6 x_piv?prefetched index value register (audio?d31:f5).................................................................................................. 552 15.2.7 x_cr?control register (audio?d31:f5).................................................................................................. 553 15.2.8 glob_cnt?global control register (audio?d31:f5).................................................................................................. 554 15.2.9 glob_sta?global status register (audio?d31:f5).................................................................................................. 556 15.2.10 cas?codec access semaphore register (audio?d31:f5).................................................................................................. 558 15.2.11 sdm?sdata_in map register (audio?d31:f5).................................................................................................. 558 16 ac ?97 modem controller registers (d31:f6) ......................................................................... 559 16.1 ac ?97 modem pci configuration space (d31:f6) .......................................................... 559 16.1.1 vid?vendor identification register (modem?d31:f6) ............................................................................................... 560 16.1.2 did?device identification register (modem?d31:f6) ............................................................................................... 560 16.1.3 pcicmd?pci command register (modem?d31:f6) ............................................................................................... 561 16.1.4 pcists?pci status register (modem?d31:f6) ............................................................................................... 562 16.1.5 rid?revision identification register (modem?d31:f6) ............................................................................................... 562 16.1.6 pi?programming interface register (modem?d31:f6) ............................................................................................... 563 16.1.7 scc?sub class code register (modem?d31:f6) ............................................................................................... 563 16.1.8 bcc?base class code register (modem?d31:f6) ............................................................................................... 563 16.1.9 headtyp?header type register (modem?d31:f6) ............................................................................................... 563 16.1.10 mmbar?modem mixer base address register (modem?d31:f6) ............................................................................................... 564 intel ? 82801eb ich5 / 82801er ich5r datasheet 29 contents 16.1.11 mbar?modem base address register (modem?d31:f6) ...............................................................................................564 16.1.12 svid?subsystem vendor identification register (modem?d31:f6) ...............................................................................................565 16.1.13 sid?subsystem identification register (modem?d31:f6) ...............................................................................................565 16.1.14 cap_ptr?capabilities pointer register (modem?d31:f6) ...............................................................................................565 16.1.15 int_ln?interrupt line register (modem?d31:f6) ...............................................................................................566 16.1.16 int_pin?interrupt pin register (modem?d31:f6) ...............................................................................................566 16.1.17 pid?pci power management capability identification register (modem?d31:f6).................................................................................566 16.1.18 pc?power management capabilities register (modem?d31:f6) ...............................................................................................567 16.1.19 pcs?power management control and status register (modem?d31:f6) ...............................................................................................567 16.2 ac ?97 modem i/o space (d31:f6) ..................................................................................568 16.2.1 x_bdbar?buffer descriptor list base address register (modem?d31:f6) ...............................................................................................570 16.2.2 x_civ?current index value register (modem?d31:f6) ...............................................................................................570 16.2.3 x_lvi?last valid index register (modem?d31:f6) ...............................................................................................571 16.2.4 x_sr?status register (modem?d31:f6) ...............................................................................................572 16.2.5 x_picb?position in current buffer register (modem?d31:f6) ...............................................................................................573 16.2.6 x_piv?prefetch index value register (modem?d31:f6) ...............................................................................................573 16.2.7 x_cr?control register (modem?d31:f6) ...............................................................................................574 16.2.8 glob_cnt?global control register (modem?d31:f6) ...............................................................................................575 16.2.9 glob_sta?global status register (modem?d31:f6) ...............................................................................................576 16.2.10 cas?codec access semaphore register (modem?d31:f6) ...............................................................................................578 17 high-precision event timer registers ....................................................................................579 17.1 gcap_id?general capabilities and identification register ...........................................581 17.2 gen_conf?general configuration register.................................................................581 17.3 gintr_sta?general interrupt status register .............................................................582 17.4 main_cnt?main counter value register......................................................................582 17.5 timn_conf?timer n configuration and capabilities register .........................................................................................................5 83 17.6 timn_comp?timer n comparator value register ........................................................585 30 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 18 ballout definition ....................................................................................................................... 587 19 electrical characteristics .......................................................................................................... 599 19.1 thermal specifications ..................................................................................................... 599 19.2 dc characteristics......................................................................................................... ... 599 19.3 ac characteristics ......................................................................................................... ... 606 19.4 timing diagrams............................................................................................................ ... 619 20 package information ................................................................................................................. 629 21 testability ............................................................................................................................... .... 631 21.1 test mode description...................................................................................................... 631 21.2 tri-state mode ............................................................................................................. ..... 632 21.3 xor chain mode............................................................................................................. .632 21.3.1 xor chain testability algorithm example .......................................................... 632 aregister index ............................................................................................................................ 639 b register bit index ...................................................................................................................... 661 intel ? 82801eb ich5 / 82801er ich5r datasheet 31 contents figures n system block diagram ......................................................................................................... ....... 4 1 intel ? ich5 interface signals block diagram .............................................................................50 2 example external rtc circuit .................................................................................................. ..67 3 example v5ref sequencing circuit ..........................................................................................67 4 conceptual system clock diagram ............................................................................................78 5 primary device status register error reporting logic...............................................................81 6 secondary status register error reporting logic......................................................................81 7 nmi# generation logic......................................................................................................... ......82 8 integrated lan controller block diagram...................................................................................85 9 64-word eeprom read instruction waveform.........................................................................96 10 lpc interface diagram ........................................................................................................ .....103 11 typical timing for lframe#................................................................................................... .107 12 abort mechanism.............................................................................................................. ........107 13 intel ? ich5 dma controller ......................................................................................................109 14 dma serial channel passing protocol .....................................................................................113 15 dma request assertion through ldrq# .................................................................................116 16 coprocessor error timing diagram ..........................................................................................142 17 signal strapping ............................................................................................................. ..........145 18 physical region descriptor table entry ...................................................................................178 19 sata power states ............................................................................................................ ......187 20 transfer descriptor .......................................................................................................... .........193 21 example queue conditions ..................................................................................................... .201 22 usb data encoding............................................................................................................ ......204 23 usb legacy keyboard flow diagram ......................................................................................213 24 intel ? ich5-usb port connections .........................................................................................223 25 intel ? ich5-based audio codec ?97 specification, version 2.3 ...............................................252 26 ac ?97 2.3 controller-codec connection..................................................................................254 27 ac-link protocol............................................................................................................. ..........255 28 ac-link powerdown timing ..................................................................................................... 262 29 sdin wake signaling .......................................................................................................... .....263 1 intel ? ich5 ballout (topview?left side)...................................................................................588 2 intel ? ich5 ballout (topview?right side) ................................................................................589 3 clock timing .................................................................................................................. ...........619 4 valid delay from rising clock edge .........................................................................................619 5 setup and hold times .......................................................................................................... ....619 6 float delay................................................................................................................... .............620 7 pulse width................................................................................................................... ............620 8 output enable delay........................................................................................................... ......620 9 ide pio mode.................................................................................................................. .........621 10 ide multiword dma ............................................................................................................ ......621 11 ultra ata mode (drive initiating a burst read) ........................................................................622 12 ultra ata mode (sustained burst) ...........................................................................................62 2 13 ultra ata mode (pausing a dma burst) ..................................................................................623 14 ultra ata mode (terminating a dma burst) ............................................................................623 15 usb rise and fall times...................................................................................................... ....623 16 usb jitter................................................................................................................... ...............624 17 usb eop width................................................................................................................ ........624 18 smbus transaction ............................................................................................................ ......624 19 smbus timeout ................................................................................................................ ........625 32 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 20 power sequencing and reset signal timings ......................................................................... 625 21 g3 (mechanical off) to s0 timings ......................................................................................... 62 6 22 s0 to s1 to s0 timing ....................................................................................................... ....... 626 23 s0 to s5 to s0 timings ....................................................................................................... ...... 627 24 ac?97 data input and output timings ...................................................................................... 627 25 intel ? ich5 package (top and side views) ............................................................................. 629 26 intel ? ich5 package (bottom view) ......................................................................................... 630 27 test mode entry (xor chain example)................................................................................... 631 28 example xor chain circuitry .................................................................................................. 632 intel ? 82801eb ich5 / 82801er ich5r datasheet 33 contents tables 1 industry specifications....................................................................................................... .........39 2 pci devices and functions ..................................................................................................... ...42 3 hub interface signals ......................................................................................................... ........51 4 lan connect interface signals................................................................................................. ..51 5 eeprom interface signals ...................................................................................................... ..51 6 flash bios interface signals.................................................................................................. ....52 7 pci interface signals ......................................................................................................... .........52 8 serial ata interface signals.................................................................................................. .....54 9 ide interface signals ......................................................................................................... .........55 10 lpc interface signals ........................................................................................................ .........56 11 interrupt signals............................................................................................................ ..............57 12 usb interface signals........................................................................................................ .........58 13 power management interface signals........................................................................................59 14 processor interface signals.................................................................................................. ......60 15 sm bus interface signals ..................................................................................................... ......61 16 system management interface signals ......................................................................................61 17 real time clock interface .................................................................................................... ......62 18 other clocks ................................................................................................................. ..............62 19 miscellaneous signals ........................................................................................................ ........62 20 ac-link signals .............................................................................................................. ............63 21 general purpose i/o signals .................................................................................................. ....63 22 power and ground signals..................................................................................................... ....65 23 functional strap definitions................................................................................................. .......66 24 test mode selection .......................................................................................................... .........68 25 intel ? ich5 power planes ..........................................................................................................69 26 integrated pull-up and pull-down resistors ..............................................................................70 27 ide series termination resistors............................................................................................. ..71 28 power plane and states for output and i/o signal ...................................................................72 29 power plane for input signals ................................................................................................ ....75 30 intel ? ich5 and system clock domains ....................................................................................77 31 type 0 configuration cycle device number translation............................................................83 32 advanced tco functionality ................................................................................................... ...98 33 lpc cycle types supported .................................................................................................... 104 34 start field bit definitions .................................................................................................. ........104 35 cycle type bit definitions................................................................................................... ......105 36 transfer size bit definition ................................................................................................. ......105 37 sync bit definition.......................................................................................................... .........106 38 intel ? ich5 response to sync failures....................................................................................106 39 dma transfer size ............................................................................................................ .......111 40 address shifting in 16-bit i/o dma transfers ..........................................................................111 41 dma cycle vs. i/o address .................................................................................................... ..115 42 pci data bus vs. dma i/o port size ........................................................................................115 43 dma i/o cycle width vs. be[3:0]# ...........................................................................................11 5 44 counter operating modes ...................................................................................................... ..121 45 interrupt controller core connections ......................................................................................12 3 46 interrupt status registers ................................................................................................... ......124 47 content of interrupt vector byte ............................................................................................. ..124 48 apic interrupt mapping ....................................................................................................... .....130 49 interrupt message address format ..........................................................................................134 34 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 50 interrupt message data format................................................................................................ 134 51 stop frame explanation ....................................................................................................... .... 136 52 data frame format ............................................................................................................ ...... 137 53 configuration bits reset by rtcrst# assertion .................................................................... 140 54 init# going active ........................................................................................................... ........ 142 55 nmi sources .................................................................................................................. ........... 143 56 dp signal differences ........................................................................................................ ...... 143 57 frequency strap behavior based on exit state ....................................................................... 144 58 frequency strap bit mapping .................................................................................................. .145 59 general power states for systems using intel ? ich5 ............................................................. 146 60 state transition rules for intel ? ich5 ...................................................................................... 147 61 system power plane ........................................................................................................... ..... 148 62 causes of smi# and sci ....................................................................................................... ... 149 63 sleep types.................................................................................................................. ............ 152 64 causes of wake events ........................................................................................................ ... 153 65 gpi wake events .............................................................................................................. ....... 153 66 transitions due to power failure ............................................................................................. 154 67 transitions due to power button .............................................................................................. 156 68 transitions due to ri# signal ................................................................................................ ... 157 69 write only registers with read paths in alt access mode ................................................... 159 70 pic reserved bits return values ............................................................................................ 16 1 71 register write accesses in alt access mode ........................................................................ 161 72 intel ? ich5 clock inputs........................................................................................................... 16 3 73 heartbeat message data....................................................................................................... ... 169 74 gpio implementation .......................................................................................................... ..... 170 75 ide legacy i/o ports: command block registers (cs1x# chip select).................................. 175 76 ide transaction timings (pci clocks) .................................................................................... 176 77 interrupt/active bit interaction definition .................................................................................. 180 78 ultraata/33 control signal redefinitions................................................................................. 181 79 sata msi vs. pci irq actions ................................................................................................ 1 88 80 legacy routing............................................................................................................... .......... 189 81 frame list pointer bit description ........................................................................................... .192 82 td link pointer .............................................................................................................. ........... 193 83 td control and status ........................................................................................................ ...... 194 84 td token..................................................................................................................... ............. 196 85 td buffer pointer ............................................................................................................ .......... 196 86 queue head block ............................................................................................................. ...... 197 87 queue head link pointer ...................................................................................................... ... 197 88 queue element link pointer................................................................................................... .. 197 89 command register, status register and td status bit interaction ......................................... 200 90 queue advance criteria ....................................................................................................... .... 202 91 usb schedule list traversal decision table ........................................................................... 203 92 pid format ................................................................................................................... ............ 205 93 pid types .................................................................................................................... ............. 205 94 address field................................................................................................................ ............ 206 95 endpoint field............................................................................................................... ............ 206 96 token format ................................................................................................................. .......... 207 97 sof packet ................................................................................................................... ........... 207 98 data packet format........................................................................................................... ....... 208 99 bits maintained in low power states ....................................................................................... 212 intel ? 82801eb ich5 / 82801er ich5r datasheet 35 contents 100 usb legacy keyboard state transitions .................................................................................214 101 uhci vs. ehci............................................................................................................... ...........215 102 debug port behavior ......................................................................................................... .......227 103 quick protocol .............................................................................................................. ............232 104 send / receive byte protocol without pec ..............................................................................232 105 send/receive byte protocol with pec .....................................................................................233 106 write byte/word protocol without pec.....................................................................................233 107 write byte/word protocol with pec..........................................................................................2 34 108 read byte/word protocol without pec ....................................................................................235 109 read byte/word protocol with pec .........................................................................................235 110 process call protocol without pec........................................................................................... 236 111 process call protocol with pec.............................................................................................. ..237 112 block read/write protocol without pec ...................................................................................238 113 block read/write protocol with pec ........................................................................................23 9 114 i 2 c block read ................................................................................................................... ......240 115 block write?block read process call protocol with/without pec............................................241 116 enable for smbalert# ........................................................................................................ ...244 117 enables for smbus slave write and smbus host events........................................................244 118 enables for the host notify command .....................................................................................244 119 slave write cycle format .................................................................................................... .....246 120 slave write registers ....................................................................................................... ........246 121 command types ............................................................................................................... .......247 122 read cycle format........................................................................................................... ........248 123 data values for slave read registers .....................................................................................249 124 host notify format.......................................................................................................... ..........250 125 features supported by intel ? ich5 ..........................................................................................251 126 ac ?97 signals .............................................................................................................. ............254 127 input slot 1 bit definitions................................................................................................ .........260 128 output tag slot 0........................................................................................................... ...........262 129 ac-link state during pcirst#................................................................................................ ..264 130 pci devices and functions ................................................................................................... ...268 131 fixed i/o ranges decoded by intel ? ich5 ..............................................................................270 132 variable i/o decode ranges .................................................................................................. ..272 133 memory decode ranges from processor perspective.............................................................273 134 lan controller pci register address map (lan controller?b1:d8:f0).................................275 135 configuration of subsystem id and subsystem vendor id via eeprom................................282 136 data register structure ..................................................................................................... .......286 137 intel ? ich5 integrated lan controller csr space register address map .............................287 138 self-test results format .................................................................................................... ......292 139 statistical counters........................................................................................................ ...........299 140 hub interface pci register address map (hub-pci?d30:f0) ...............................................301 141 lpc interface pci register address map (lpc i/f?d31:f0) .................................................317 142 dma registers............................................................................................................... ...........344 143 pic registers (lpc i/f?d31:f0).............................................................................................3 55 144 apic direct registers (lpc i/f?d31:f0)................................................................................363 145 apic indirect registers (lpc i/f?d31:f0) .............................................................................363 146 rtc i/o registers (lpc i/f?d31:f0) .....................................................................................369 147 rtc (standard) ram bank (lpc i/f?d31:f0) .......................................................................369 148 processor interface pci register address map (lpc i/f?d31:f0) ........................................373 149 power management pci register address map (pm?d31:f0)..............................................376 36 intel ? 82801eb ich5 / 82801er ich5r datasheet contents 150 apm register map ............................................................................................................ ....... 384 151 acpi and legacy i/o register map ......................................................................................... 385 152 tco i/o register address map................................................................................................ 403 153 registers to control gpio address map.................................................................................. 409 154 ide controller pci register address map (ide-d31:f1) ......................................................... 415 155 bus master ide i/o registers ................................................................................................ .. 430 156 sata controller pci register address map (sata?d31:f2) ................................................. 433 157 sata indexed registers ...................................................................................................... .... 452 158 bus master ide i/o register address map .............................................................................. 456 159 uhci controller pci register address map (usb?d29:f0/f1/f2/f3) ................................... 461 160 usb i/o registers ........................................................................................................... ......... 470 161 run/stop, debug bit interaction swdbg (bit 5), run/stop (bit 0) operation ......................... 473 162 usb ehci pci register address map (usb ehci?d29:f7) ................................................. 479 163 enhanced host controller capability registers ....................................................................... 496 164 enhanced host controller operational register address map ................................................ 499 165 debug port register address map........................................................................................... 51 2 166 smbus controller pci register address map (smbus?d31:f3) .......................................... 515 167 smbus i/o register address map............................................................................................ 52 1 168 ac ?97 audio pci register address map (audio?d31:f5) ..................................................... 533 169 intel ? ich5 audio mixer register configuration...................................................................... 546 170 native audio bus master control registers ............................................................................. 548 171 ac ?97 modem pci register address map (modem?d31:f6) ............................................... 559 172 intel ? ich5 modem mixer register configuration .................................................................... 568 173 modem registers ............................................................................................................. ........ 569 174 memory-mapped registers ..................................................................................................... .579 175 intel ? ich5 ballout by signal name ......................................................................................... 590 176 intel ? ich5 ballout by ball number .......................................................................................... 594 177 dc current characteristics.................................................................................................. ..... 599 178 dc characteristic input signal association .............................................................................. 600 179 dc input characteristics.................................................................................................... ....... 601 180 dc characteristic output signal association ........................................................................... 603 181 dc output characteristics ................................................................................................... ..... 604 182 other dc characteristics.................................................................................................... ...... 605 183 clock timings ............................................................................................................... ............ 606 184 pci interface timing........................................................................................................ ......... 608 185 ide pio and multiword dma modetiming ............................................................................... 609 186 ultra ata timing (mode 0, mode 1, mode 2) ........................................................................... 610 187 ultra ata timing (mode 3, mode 4, mode 5) ........................................................................... 612 188 universal serial bus timing ................................................................................................. .... 614 189 sata interface timings...................................................................................................... ...... 615 190 smbus timing ................................................................................................................ .......... 615 192 lpc timing.................................................................................................................. ............. 616 193 miscellaneous timings ....................................................................................................... ...... 616 191 ac?97 timing ................................................................................................................ ............ 616 194 power sequencing and reset signal timings ......................................................................... 617 195 power management timings .................................................................................................... 618 196 test mode selection......................................................................................................... ........ 631 197 xor test pattern example .................................................................................................... .. 632 198 xor chain #1 (rtcrst# asserted for 4 pci clocks while pwrok active) ......................... 633 199 xor chain #2 (rtcrst# asserted for 5 pci clocks while pwrok active) ......................... 634 intel ? 82801eb ich5 / 82801er ich5r datasheet 37 contents 200 xor chain #3 (rtcrst# asserted for 6 pci clocks while pwrok active) .........................635 201 xor chain #4-1 (rtcrst# asserted for 7 pci clocks while pwrok active)......................636 203 xor chain #6 (rtcrst# asserted for 52 pci clocks while pwrok active) .......................637 202 xor chain #4-2 (rtcrst# asserted for 7 pci clocks while pwrok active)......................637 204 intel ? ich5 pci configuration registers ..................................................................................639 205 intel ? ich5 fixed i/o registers ................................................................................................650 206 intel ? ich5 variable i/o registers ...........................................................................................655 38 intel ? 82801eb ich5 / 82801er ich5r datasheet contents revision history revision description date -001 initial release april 2003 intel ? 82801eb ich5 / 82801er ich5r datasheet 39 introduction introduction 1 1.1 about this manual this manual is intended for original equipment manufacturers and bios vendors creating intel ? 82801eb ich5 and intel ? 82801er ich5 r (ich5r)-based products. throughout this manual, all references to ich5 refer to both ich5 and ich5r components, unless specifically noted otherwise. this manual assumes a working knowledge of the vocabulary and principles of usb, ide, sata, ac ?97, smbus, pci, acpi and lpc. although some details of these features are described within this manual, refer to the individual industry specifications listed in table 1 for the complete details. table 1. industry specifications specification location low pin count interface specification, revision 1.1 (lpc) http://developer.intel.com/design/chipsets/ industry/lpc.htm audio codec ?97 component specification, version 2.3 (also known as ac ?97 v2.3 specification ) http://www.intel.com/labs/media/audio/ index.htm#97spec23 wired for management baseline version 2.0 (wfm) http://www.intel.com/labs/manage/wfm/ wfmspecs.htm system management bus (smbus) specification, version 2.0 http://www.smbus.org/specs/ pci local bus specification, revision 2.3 (pci) http://www.pcisig.com/specifications/ conventional pci-to-pci bridge architecture specification, revision 1.1 http://www.pcisig.com/specifications/ conventional pci power management specification, revision 1.1 http://www.pcisig.com/specifications/ conventional universal serial bus revision 2.0 specification (usb) http://www.usb.org/developers/docs/ advanced configuration and power interface, version 2.0b (acpi) http://www.acpi.info/spec.htm enhanced host controller interface specification for universal serial bus, revision 1.0 (ehci) http://developer.intel.com/technology/usb/ ehcispec.htm sata 1.0a specification (serial ata) http://www.serialata.org/collateral/ index.shtml alert standard format (asf) specification, version 1.03 http://www.dmtf.org/standards/ standard_alert.php ieee 802.3 http://standards.ieee.org at attachment - 6 with packet interface (ata/atapi - 6) http://t13.org (t13 1410d) power management network device class reference specification, revision 1.0 40 intel ? 82801eb ich5 / 82801er ich5r datasheet introduction chapter 1. introduction chapter 1 introduces the ich5 and provides information on manual organization. chapter 2. signal description chapter 2 provides a detailed description of each ich5 signal. signals are arranged according to interface and details are provided as to the drive characteristics (input/output, open drain, etc.) of all signals. chapter 3. intel ? ich5 power planes and pin states chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset. chapter 4. intel ? ich5 and system clock domains chapter 4 provides a list of each clock domain associated with the ich5 in an ich5-based system. chapter 5. functional description chapter 5 provides a detailed description of the functions in the ich5. all pci buses, devices and functions in this manual are abbreviated using the following nomenclature; bus:device:function. this manual abbreviates buses as b0 and b1, devices as d8, d29, d30 and d31 and functions as f0, f1, f2, f3, f4, f5, f6 and f7. for example device 31 function 5 is abbreviated as d31:f5, bus 1 device 8 function 0 is abbreviated as b1:d8:f0. generally, the bus number will not be used, and can be considered to be bus 0. note that the ich5?s external pci bus is typically bus 1, but may be assigned a different number depending upon system configuration. chapter 6. register and memory mappings chapter 6 provides an overview of the registers, fixed i/o ranges, variable i/o ranges and memory ranges decoded by the ich5. chapter 7. lan controller registers chapter 7 provides a detailed description of all registers that reside in the ich5?s integrated lan controller. the integrated lan controller resides on the ich5?s external pci bus (typically bus 1) at device 8, function 0 (b1:d8:f0). chapter 8. hub interface to pci bridge registers chapter 8 provides a detailed description of all registers that reside in the hub interface to pci bridge. this bridge resides at device 30, function 0 (d30:f0). chapter 9. lpc bridge registers chapter 9 provides a detailed description of all registers that reside in the lpc bridge. this bridge resides at device 31, function 0 (d31:f0). this function contains registers for many different units within the ich5 including dma, timers, interrupts, processor interface, gpio, power management, system management and rtc. chapter 10. ide controller registers chapter 10 provides a detailed description of all registers that reside in the ide controller. this controller resides at device 31, function 1 (d31:f1). chapter 11. sata controller registers chapter 11 provides a detailed description of all registers that reside in the sata controller. this controller resides at device 31, function 2 (d31:f2). chapter 12. uhci controller registers chapter 12 provides a detailed description of all registers that reside in the four uhci host controllers. these controllers reside at device 29, functions 0, 1, 2, and 3 (d29:f0/f1/f2/f3). intel ? 82801eb ich5 / 82801er ich5r datasheet 41 introduction chapter 13. ehci controller registers chapter 13 provides a detailed description of all registers that reside in the ehci host controller. this controller resides at device 29, function 7 (d29:f7). chapter 14. smbus controller registers chapter 14 provides a detailed description of all registers that reside in the smbus controller. this controller resides at device 31, function 3 (d31:f3). chapter 15. ac ?97 audio controller registers chapter 15 provides a detailed description of all registers that reside in the audio controller. this controller resides at device 31, function 5 (d31:f5). note that this chapter of the datasheet does not include the native audio mixer registers. accesses to the mixer registers are forwarded over the ac-link to the codec where the registers reside. chapter 16. ac ?97 modem controller registers chapter 16 provides a detailed description of all registers that reside in the modem controller. this controller resides at device 31, function 6 (d31:f6). note that this chapter of the datasheet does not include the modem mixer registers. accesses to the mixer registers are forwarded over the ac- link to the codec where the registers reside. chapter 17. high-precision event timers registers chapter 17 provides a detailed description of all registers that reside in the multimedia timer memory mapped register space. chapter 18. ballout definition chapter 18 provides a table of each signal and its ball assignment in the 460 mbga package. chapter 19. electrical characteristics chapter 19 provides all ac and dc characteristics including detailed timing diagrams. chapter 20. package information chapter 20 provides drawings of the physical dimensions and characteristics of the 460-mbga package. chapter 21. testability chapter 21 provides detail about the implementation of test modes provided in the ich5. index this manual ends with indexes of registers and register bits. 42 intel ? 82801eb ich5 / 82801er ich5r datasheet introduction 1.2 overview the ich5 provides extensive i/o support. functions and capabilities include: ? pci local bus specification, revision 2.3 with support for 33 mhz pci operations. ? pci slots (supports up to 6 req/gnt pairs) ? acpi power management logic support ? enhanced dma controller, interrupt controller, and timer functions ? integrated ide controller supports ultra ata100/66/33 ? integrated sata controller ? usb host interface with support for eight usb ports; four uhci host controllers; one ehci high-speed usb 2.0 host controller ? integrated lan controller ? integrated asf controller ? system management bus (smbus) specification, version 2.0 with additional support for i 2 c devices ? supports audio codec ?97 component specification, version 2.3 (also known as ac ?97 v2.3 specification ) link for audio and telephony codecs (up to seven channels) ? low pin count (lpc) interface ? firmware hub (fwh) interface support the ich5 incorporates a variety of pci functions that are divided into four logical devices (b0:d30, b0:d31, b0:d29 and b1:d8). d30 is the hub interface-to-pci bridge, d31 contains the pci-to-lpc bridge, ide controller, sata controller, smbus controller and the ac ?97 audio and modem controller functions and d29 contains the four usb uhci controllers and one usb ehci controller. b1:d8 is the integrated lan controller. notes: 1. the pci to lpc bridge contains registers that control lpc, power management, system management, gpio, processor interface, rtc, interrupts, timers, dma. table 2. pci devices and functions bus:device:function function description bus 0:device 30:function 0 hub interface to pci bridge bus 0:device 31:function 0 pci to lpc bridge 1 bus 0:device 31:function 1 ide controller bus 0:device 31:function 2 new: sata controller bus 0:device 31:function 3 smbus controller bus 0:device 31:function 5 ac?97 audio controller bus 0:device 31:function 6 ac?97 modem controller bus 0:device 29:function 0 usb uhci controller #1 bus 0:device 29:function 1 usb uhci controller #2 bus 0:device 29:function 2 usb uhci controller #3 bus 0:device 29:function 3 new: usb uhci controller #4 bus 0:device 29:function 7 usb 2.0 ehci controller bus n:device 8:function 0 lan controller intel ? 82801eb ich5 / 82801er ich5r datasheet 43 introduction the following sub-sections provide an overview of the ich5 capabilities. hub architecture the chipset?s hub interface architecture ensures that the i/o subsystem; both pci and the integrated i/o features (sata, ide, ac ?97, usb, etc.), receive the bandwidth necessary for peak performance. pci interface the ich5 pci interface provides a 33 mhz, revision 2.3 compliant implementation. all pci signals are 5-v tolerant, except pme#. the ich5 integrates a pci arbiter that supports up to six external pci bus masters in addition to the internal ich5 requests. ide interface (bus master capability and synchronous dma mode) the fast ide interface supports up to four ide devices providing an interface for ide hard disks and atapi devices. each ide device can have independent timings. the ide interface supports pio ide transfers up to 16 mbytes/sec and ultra ata transfers up 100 mbytes/sec. it does not consume any isa dma resources. the ide interface integrates 16x32-bit buffers for optimal transfers. the ich5?s ide system contains two independent ide signal channels. they can be electrically isolated independently. they can be configured to the standard primary and secondary channels (four devices). there are integrated series resistors on the data and control lines (see section 5.16 for details). sata controller the sata controller supports two sata devices providing an interface for sata hard disks and atapi devices. the sata interface supports pio ide transfers up to 16 mb/s and serial ata transfers up to 1.5 gb/s (150 mb/s). the ich5?s sata system contains two independent sata signal ports. they can be electrically isolated independently. each sata device can have independent timings. they can be configured to the standard primary and secondary channels. low pin count (lpc) interface the ich5 implements an lpc interface as described in the low pin count interface specification, revision 1.1 . the low pin count (lpc) bridge function of the ich5 resides in pci device 31:function 0. in addition to the lpc bridge interface function, d31:f0 contains other functional units including dma, interrupt controllers, timers, power management, system management, gpio, and rtc. 44 intel ? 82801eb ich5 / 82801er ich5r datasheet introduction compatibility modules (dma controller, timer/counters, interrupt controller) the dma controller incorporates the logic of two 82c37 dma controllers, with seven independently programmable channels. channels 0?3 are hardwired to 8-bit, count-by-byte transfers, and channels 5?7 are hardwired to 16-bit, count-by-word transfers. any two of the seven dma channels can be programmed to support fast type-f transfers. the ich5 supports two types of dma (lpc and pc/pci). dma via lpc is similar to isa dma. lpc dma and pc/pci dma use the ich5?s dma controller. the pc/pci protocol allows pci-based peripherals to initiate dma cycles by encoding requests and grants via two pc/pci req#/gnt# pairs. lpc dma is handled through the use of the ldrq# lines from peripherals and special encoding on lad[3:0] from the host. single, demand, verify, and increment modes are supported on the lpc interface. channels 0?3 are 8 bit channels. channels 5?7 are 16 bit channels. channel 4 is reserved as a generic bus master request. the timer/counter block contains three counters that are equivalent in function to those found in one 82c54 programmable interval timer. these three counters are combined to provide the system timer function, and speaker tone. the 14.31818 mhz oscillator input provides the clock source for these three counters. the ich5 provides an isa-compatible programmable interrupt controller (pic) that incorporates the functionality of two 82c59 interrupt controllers. the two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. in addition, the ich5 supports a serial interrupt scheme. all of the registers in these modules can be read and restored. this is required to save and restore system state after power has been removed and restored to the platform. advanced programmable interrupt controller (apic) in addition to the standard isa-compatible pic described in the previous section, the ich5 incorporates the advanced programmable interrupt controller (apic). universal serial bus (usb) controller the ich5 contains an enhanced host controller interface specification for universal serial bus, revision 1.0 -compliant host controller that supports usb high-speed signaling. high-speed usb 2.0 allows data transfers up to 480 mb/s which is 40 times faster than full-speed usb. the ich5 also contains four universal host controller interface (uhci) controllers that support usb full- speed and low-speed signaling. the ich5 supports eight usb 2.0 ports. all eight ports are high-speed, full-speed, and low-speed capable. ich5?s port-routing logic determines whether a usb port is controlled by one of the uhci controllers or by the ehci controller. see section 5.19 and section 5.20 for details. intel ? 82801eb ich5 / 82801er ich5r datasheet 45 introduction lan controller the ich5?s integrated lan controller includes a 32-bit pci controller that provides enhanced scatter-gather bus mastering capabilities and enables the lan controller to perform high speed data transfers over the pci bus. its bus master capabilities enable the component to process high- level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. two large transmit and receive fifos of 3 kb each help prevent data underruns and overruns while waiting for bus accesses. this enables the integrated lan controller to transmit data with minimum interframe spacing (ifs). the lan controller can operate in either full duplex or half duplex mode. in full duplex mode the lan controller adheres with the ieee 802.3x flow control specification . half duplex performance is enhanced by a proprietary collision reduction mechanism. see section 5.2 for details. rtc the ich5 contains a motorola mc146818a-compatible real-time clock with 256 bytes of battery- backed ram. the real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. the rtc operates on a 32.768 khz crystal and a separate 3 v lithium battery. the rtc also supports two lockable memory ranges. by setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. this prevents unauthorized reading of passwords or other system security information. the rtc also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance. gpio various general purpose inputs and outputs are provided for custom system design. the number of inputs and outputs varies depending on ich5 configuration. enhanced power management the ich5?s power management functions include enhanced clock control, local and global monitoring support for 14 individual devices, and various low-power (suspend) states (e.g., suspend-to-dram and suspend-to-disk). a hardware-based thermal management circuit permits software-independent entrance to low-power states. the ich5 contains full support for the advanced configuration and power interface (acpi) specification, revision 2.0b . system management bus (smbus 2.0) the ich5 contains an smbus host interface that allows the processor to communicate with smbus slaves. this interface is compatible with most i 2 c devices. special i 2 c commands are implemented. the ich5?s smbus host controller provides a mechanism for the processor to initiate communications with smbus peripherals (slaves). also, the ich5 supports slave functionality, including the host notify protocol. hence, the host controller supports eight command protocols of the smbus interface (see system management bus (smbus) specification, version 2.0 ): quick command, send byte, receive byte, write byte/word, read byte/word, process call, block read/write, and host notify. 46 intel ? 82801eb ich5 / 82801er ich5r datasheet introduction manageability the ich5 integrates several functions designed to manage the system and lower the total cost of ownership (tco) of the system. these system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller. ? tco timer. the ich5?s integrated programmable tco timer is used to detect system locks. the first expiration of the timer generates an smi# that the system can use to recover from a software lock. the second expiration of the timer causes a system reset to recover from a hardware lock. ? processor present indicator. the ich5 looks for the processor to fetch the first instruction after reset. if the processor does not fetch the first instruction, the ich5 can reboot the system. ? ecc error reporting. when detecting an ecc error, the host controller has the ability to send one of several messages to the ich5. the host controller can instruct the ich5 to generate either an smi#, nmi, serr#, or tco interrupt. ? function disable. the ich5 provides the ability to disable the following functions: ac ?97 modem, ac ?97 audio, ide, sata, lan, usb, uhci, ehci, or smbus. once disabled, these functions no longer decode i/o, memory, or pci configuration space. also, no interrupts or power management events are generated from the disable functions. ? intruder detect. the ich5 provides an input signal (intruder#) that can be attached to a switch that is activated by the system case being opened. the ich5 can be programmed to generate an smi# or tco interrupt due to an active intruder# signal. ? smbus 2.0. the ich5 integrates an smbus controller that provides an interface to manage peripherals (e.g., serial presence detection (spd) and thermal sensors) with host notify capabilities. intel ? 82801eb ich5 / 82801er ich5r datasheet 47 introduction ac ?97 2.3 controller the ac ?97 v2.3 specification defines a digital interface that can be used to attach an audio codec (ac), a modem codec (mc), an audio/modem codec (amc) or a combination of acs and mc. the ac ?97 v2.3 specification defines the interface between the system logic and the audio or modem codec, known as the ac-link . by using an audio codec, the ac-link allows for cost-effective, high-quality, integrated audio on intel?s chipset-based platform. in addition, an ac ?97 soft modem can be implemented with the use of a modem codec. several system options exist when implementing ac ?97. the ich5-integrated digital link allows several external codecs to be connected to the ich5. the system designer can provide audio with an audio codec, a modem with a modem codec, or an integrated audio/modem codec. the digital link is expanded to support three audio codecs or two audio codecs and one modem codec. the modem implementations for different countries must be taken into consideration, because telephone systems may vary. by using a split design, the audio codecs can be on-board and the modem codec can be placed on a riser. the digital link in the ich5 supports the ac ?97 v2.3 specification , so it supports three codecs with independent pci functions for audio and modem. microphone input and left and right audio channels are supported for a high quality, two-speaker audio solution. wake on ring from suspend also is supported with the appropriate modem codec. the ich5 expands the audio capability with support for up to six channels of pcm audio output (full ac3 decode). six-channel audio consists of front left, front right, back left, back right, center, and subwoofer, for a complete surround-sound effect. ich5 has expanded support for three audio codecs on the ac-link. alert standard format (asf) controller the alert standard format specification, version 1.03 supported by the ich5, defines asf alerting capabilities including system health information such as bios messages, post alerts, os failure notifications, and heartbeat signals to indicate the system is up and running on the network. also included are environmental notifications such as thermal, voltage and fan alerts, which send proactive warnings that something is wrong with the hardware. in addition, asset security is provided by messages such as ?cover tamper? and ?cpu missing? that notify an it manager of potential system break-ins and processor or memory theft. 48 intel ? 82801eb ich5 / 82801er ich5r datasheet introduction this page is intentionally left blank. intel ? 82801eb ich5 / 82801er ich5r datasheet 49 signal description signal description 2 this chapter provides a detailed description of each signal. the signals are arranged in functional groups according to their associated interface. the ?#? symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is not present, the signal is asserted when at the high voltage level. the following notations are used to describe the signal type: i input pin o output pin od open drain output pin. i/o bi-directional input / output pin. 50 intel ? 82801eb ich5 / 82801er ich5r datasheet signal description figure 1. intel ? ich5 interface signals block diagram thrm# thrmtrip# sys_reset# slp_s3# slp_s4# slp_s5# pw rok pw rbtn# ri# rsmrst# sus_stat# / lpcpd# susclk lan_rst# vrmpwrgd ad[31:0] c /be [3:0]# devsel# frame# ird y# trdy# stop# par perr# req[3:0]# req5# / re q b # / g pio 1 req4# / g pio 40 gnt[3:0]# gnt5# / g ntb # / g pio 17 gnt4# / g pio 48 pciclk pcirst# plock# serr# pme# pci interface pdcs1# sdcs1# pdcs3# sdcs3# pda[2:0] sda[2:0] pdd[15:0] sdd[15:0] pddreq sddreq pddack# sddack# pdior# (pdwstb / prdmardy#) sdior# (sdwstb / srdmardy#) pdiow# (pd s to p) sdiow# (sd s to p) piordy (pdrstb / pw dmardy#) siordy (sdrstb / sw dmardy#) ide interface power mgmt. interrupt interface a20m # cpuslp# ferr# ig nn e # in it# intr nmi smi# stpclk# rcin# a20gate cpupwrgd processor interface usb serirq p ir q [d:a]# pir q [h :e ] / g p io [5:2] irq[15:14] usbp0p?usb7p usbp0n?usb7n o c[3:0]# oc4# / g p io 9 oc5# / g pio 10 oc6# / g pio 14 oc7# / g pio 15 usbrbias# usbrbias rtcx1 rtcx2 clk14 clk48 clk66 clk100p, clk100n rtc clocks misc. signals in tvr m e n spkr rtcrst# tp[0] tp[1] tp[2] general purpose i/o gpio[34,33,28:27,25:24] gpio[41:40, 15:0] gpio[49:48, 23:16] eeprom interface ee_shclk ee_din ee_dout ee_cs intr ud e r# smlink[1:0] linkalert# hi[11:0] hi_stbs hi_stbf hicomp hi_vswing hub interface lpc interface smbus interface ac_rst# ac_sync ac_bit_clk ac_sdout ac_sdin[2:0] ac- link firm ware hub system mgnt. fb[3:0] / lad[3:0] fb[4] / lfr am e# lad[3:0] / fb[3:0] lframe# / fb[4] ldrq0# ldrq1# / gpio41 smbdata smbclk smbalert# / g p io 11 lan_clk lan_rxd[2:0] lan_txd[2:0] lan_rstsync lan link sata0txp, sata0txn sata0rxp, sata0rxn sata1txp, sata1txn sata1rxp, sata1rxn satarbias, satarbias# sataled# serial ata interface intel ? 82801eb ich5 / 82801er ich5r datasheet 51 signal description 2.1 hub interface to host controller 2.2 link to lan connect 2.3 eeprom interface table 3. hub interface signals name type description hi[11:0] i/o hub interface signals hi_stbf i/o hub interface strobe first: the first of two differential strobe signals used to transmit and receive data through the hub interface. hi_stbs i/o hub interface strobe second: the second of two strobe signals used to transmit and receive data through the hub interface. hircomp i/o hub interface impedance compensation: this signal is used for hub interface buffer compensation. hi_vswing i hub interface voltage swing: this is an analog input used to control the voltage swing and impedance strength of hub interface pins. the expected voltage is 800 mv. table 4. lan connect interface signals name type description lan_clk i lan i/f clock: this signal is driven by the lan connect component. the frequency range is 5 mhz to 50 mhz. lan_rxd[2:0] i received data: the platform lan connect component uses these signals to transfer data and control information to the integrated lan controller. these signals have integrated weak pull-up resistors. lan_txd[2:0] o transmit data: the integrated lan controller uses these signals to transfer data and control information to the lan connect component. lan_rstsync o lan reset/sync: the platform lan connect component?s reset and sync signals are multiplexed onto this pin. table 5. eeprom interface signals name type description ee_shclk o eeprom shift clock: this signal is the serial shift clock output to the eeprom. ee_din i eeprom data in: this signal transfers data from the eeprom to the intel ? ich5. this signal has an integrated pull-up resistor. ee_dout o eeprom data out: this signal transfers data from the ich5 to the eeprom. ee_cs o eeprom chip select: this signal is the chip select to the eeprom. 52 intel ? 82801eb ich5 / 82801er ich5r datasheet signal description 2.4 flash bios interface 2.5 pci interface table 6. flash bios interface signals name type description fb[3:0] / lad[3:0] i/o flash bios signals: these signals are multiplexed with the lpc address signals. fb4 / lframe# i/o flash bios signals: this signal is multiplexed with the lpc lframe# signal. table 7. pci interface signals (sheet 1 of 3) name type description ad[31:0] i/o pci address/data: ad[31:0] are the signals of the multiplexed address and data bus. during the first clock of a transaction, ad[31:0] contain a physical address (32 bits). during subsequent clocks, ad[31:0] contain data. the intel ? ich5 will drive all 0s on ad[31:0] during the address phase of all pci special cycles. c/be[3:0]# i/o bus command and byte enables: the command and byte enable signals are multiplexed on the same pci pins. during the address phase of a transaction, c/be[3:0]# define the bus command. during the data phase c/be[3:0]# define the byte enables. c/be[3:0]# command type 0 0 0 0 interrupt acknowledge 0 0 0 1 special cycle 0 0 1 0 i/o read 0 0 1 1 i/o write 0 1 1 0 memory read 0 1 1 1 memory write 1 0 1 0 configuration read 1 0 1 1 configuration write 1 1 0 0 memory read multiple 1 1 1 0 memory read line 1 1 1 1 memory write and invalidate all command encodings not shown are reserved. the ich5 does not decode reserved values, and therefore will not respond if a pci master generates a cycle using 1 of the reserved values. devsel# i/o device select: the ich5 asserts devsel# to claim a pci transaction. as an output, the ich5 asserts devsel# when a pci master peripheral attempts an access to an internal ich5 address or an address destined for the hub interface (main memory or agp). as an input, devsel# indicates the response to an ich5- initiated transaction on the pci bus. devsel# is tri-stated from the leading edge of pcirst#. devsel# remains tri-stated by the ich5 until driven by a target device. frame# i/o cycle frame: the current initiator drives frame# to indicate the beginning and duration of a pci transaction. while the initiator asserts frame#, data transfers continue. when the initiator negates frame#, the transaction is in the final data phase. frame# is an input to the ich5 when the ich5 is the target, and frame# is an output from the ich5 when the ich5 is the initiator. frame# remains tri- stated by the ich5 until driven by an initiator. intel ? 82801eb ich5 / 82801er ich5r datasheet 53 signal description irdy# i/o initiator ready: irdy# indicates the ich5's ability, as an initiator, to complete the current data phase of the transaction. it is used in conjunction with trdy#. a data phase is completed on any clock both irdy# and trdy# are sampled asserted. during a write, irdy# indicates the ich5 has valid data present on ad[31:0]. during a read, it indicates the ich5 is prepared to latch data. irdy# is an input to the ich5 when the ich5 is the target and an output from the ich5 when the ich5 is an initiator. irdy# remains tri-stated by the ich5 until driven by an initiator. trdy# i/o target ready: trdy# indicates the ich5's ability as a target to complete the current data phase of the transaction. trdy# is used in conjunction with irdy#. a data phase is completed when both trdy# and irdy# are sampled asserted. during a read, trdy# indicates that the ich5, as a target, has placed valid data on ad[31:0]. during a write, trdy# indicates the ich5, as a target is prepared to latch data. trdy# is an input to the ich5 when the ich5 is the initiator and an output from the ich5 when the ich5 is a target. trdy# is tri-stated from the leading edge of pcirst#. trdy# remains tri-stated by the ich5 until driven by a target. stop# i/o stop: stop# indicates that the ich5, as a target, is requesting the initiator to stop the current transaction. stop# causes the ich5, as an initiator, to stop the current transaction. stop# is an output when the ich5 is a target and an input when the ich5 is an initiator. stop# is tri-stated from the leading edge of pcirst#. stop# remains tri-stated until driven by the ich5. par i/o calculated/checked parity: par uses ?even? parity calculated on 36 bits, ad[31:0] plus c/be[3:0]#. ?even? parity means that the ich5 counts the number of 1? within the 36 bits plus par and the sum is always even. the ich5 always calculates par on 36 bits regardless of the valid byte enables. the ich5 generates par for address and data phases and only guarantees par to be valid one pci clock after the corresponding address or data phase. the ich5 drives and tri- states par identically to the ad[31:0] lines except that the ich5 delays par by exactly one pci clock. par is an output during the address phase (delayed one clock) for all ich5 initiated transactions. par is an output during the data phase (delayed one clock) when the ich5 is the initiator of a pci write transaction, and when it is the target of a read transaction. ich5 checks parity when it is the target of a pci write transaction. if a parity error is detected, the ich5 will set the appropriate internal status bits, and has the option to generate an nmi# or smi#. perr# i/o parity error : an external pci device drives perr# when it receives data that has a parity error. the ich5 drives perr# when it detects a parity error. the ich5 can either generate an nmi# or smi# upon detecting a parity error (either detected internally or reported via the perr# signal when serving as the initiator). req[0:3]# req4# / gpio40 req5# / reqb# / gpio1 i pci requests : the ich5 supports up to six masters on the pci bus. the req4# pin can instead be used as a gpi. req5# is muxed with pc/pci reqb# (must choose one or the other, but not both). if not used for pci or pc/pci, req5#/ reqb# can instead be used as gpio1. note: r eq0# is programmable to have improved arbitration latency for supporting pci-based 1394 controllers. gnt[0:3]# gnt4# / gpio48 gnt5# / gntb# / gpio17# o pci grants: the ich5 supports up to 6 masters on the pci bus. the gnt4# pin can instead be used as a gpo. gnt5# is multiplexed with pc/pci gntb# (must choose one or the other, but not both). if not needed for pci or pc/pci, gnt5# can instead be used as a gpio. pull-up resistors are not required on these signals. if pull-ups are used, they should be tied to the vcc3_3 power rail. gntb#/gnt5#/gpio17 has an internal pull-up. pciclk i pci clock: this is a 33 mhz clock. pciclk provides timing for all transactions on the pci bus. table 7. pci interface signals (sheet 2 of 3) name type description 54 intel ? 82801eb ich5 / 82801er ich5r datasheet signal description 2.6 serial ata interface pcirst# o pci reset: ich5 asserts pcirst# to reset devices that reside on the pci bus. the ich5 asserts pcirst# during power-up and when s/w initiates a hard reset sequence through the rc (cf9h) register. the ich5 drives pcirst# inactive a minimum of 1 ms after pwrok is driven active. the ich5 drives pcirst# active a minimum of 1 ms when initiated through the rc register. plock# i/o pci lock: this signal indicates an exclusive bus operation and may require multiple transactions to complete. ich5 asserts plock# when it performs non- exclusive transactions on the pci bus. plock# is ignored when pci masters are granted the bus. serr# i/od system error: serr# can be pulsed active by any pci device that detects a system error condition. upon sampling serr# active, the ich5 has the ability to generate an nmi, smi#, or interrupt. pme# i/od pci power management event: pci peripherals drive pme# to wake the system from low-power states s1?s5. pme# assertion can also be enabled to generate an sci from the s0 state. in some cases the ich5 may drive pme# active due to an internal wake event. the ich5 will not drive pme# high, but it will be pulled up to vccsus3_3 by an internal pull-up resistor. reqa# / gpio0 reqb# / req5# / gpio1 i pc/pci dma request [a:b]: this request serializes isa-like dma requests for the purpose of running isa-compatible dma cycles over the pci bus. this is used by devices such as pci based super i/o or audio codecs that need to perform legacy 8237 dma but have no isa bus. when not used for pc/pci requests, these signals can be used as general purpose inputs. reqb# can instead be used as the 6th pci bus request. gnta# / gpio16 gntb# / gnt5# / gpio17 o pc/pci dma acknowledges [a: b]: this grant serializes an isa-like dack# for the purpose of running dma/isa master cycles over the pci bus. this is used by devices such as pci based super/io or audio codecs which need to perform legacy 8237 dma but have no isa bus. when not used for pc/pci, these signals can be used as general purpose outputs. gntb# can also be used as the 6th pci bus master grant output. these signal have internal pull-up resistors. table 8. serial ata interface signals name type description sata0txp sata0txn o serial ata 0 differential transmit pair: these are outbound high-speed differential signals to port 0. sata0rxp sata0rxn i serial ata 0 differential receive pair: these are inbound high-speed differential signals from port 0. sata1txp sata1txn o serial ata 1 differential transmit pair: these are outbound high-speed differential signals to port 1. sata1rxp sata1rxn i serial ata 1 differential receive pair: these are inbound high-speed differential signals from port 1. satarbias satarbias# i serial ata resistor bias: these are analog connection points for an external resistor to ground. sataled# od sata drive activity indicator: this signal indicates sata drive activity when driven low. table 7. pci interface signals (sheet 3 of 3) name type description intel ? 82801eb ich5 / 82801er ich5r datasheet 55 signal description 2.7 ide interface table 9. ide interface signals (sheet 1 of 2) name type description pdcs1#, sdcs1# o primary and secondary ide device chip selects for 100 range: for ata command register block. this output signal is connected to the corresponding signal on the primary or secondary ide connector. pdcs3#, sdcs3# o primary and secondary ide device chip select for 300 range: for ata control register block. this output signal is connected to the corresponding signal on the primary or secondary ide connector. pda[2:0], sda[2:0] o primary and secondary ide device address: these output signals are connected to the corresponding signals on the primary or secondary ide connectors. they are used to indicate which byte in either the ata command block or control block is being addressed. pdd[15:0], sdd[15:0] i/o primary and secondary ide device data: these signals directly drive the corresponding signals on the primary or secondary ide connector. there is a weak internal pull-down resistor on pdd7 and sdd7. pddreq, sddreq i primary and secondary ide device dma request: these input signals are directly driven from the drq signals on the primary or secondary ide connector. it is asserted by the ide device to request a data transfer, and used in conjunction with the pci bus master ide function and are not associated with any at compatible dma channel. there is a weak internal pull-down resistor on these signals. pddack#, sddack# o primary and secondary ide device dma acknowledge: these signals directly drive the dak# signals on the primary and secondary ide connectors. each is asserted by the intel ? ich5 to indicate to ide dma slave devices that a given data transfer cycle (assertion of dior# or diow#) is a dma data transfer cycle. this signal is used in conjunction with the pci bus master ide function and are not associated with any at-compatible dma channel. 56 intel ? 82801eb ich5 / 82801er ich5r datasheet signal description 2.8 lpc interface pdior# / (pdwstb / prdmardy#) sdior# / (sdwstb / srdmardy#) o primary and secondary disk i/o read (pio and non-ultra dma): this is the command to the ide device that it may drive data onto the pdd or sdd lines. data is latched by the ich5 on the deassertion edge of pdior# or sdior#. the ide device is selected either by the ata register file chip selects (pdcs1# or sdcs1#, pdcs3# or sdcs3#) and the pda or sda lines, or the ide dma acknowledge (pddak# or sddak#). primary and secondary disk write strobe (ultra dma writes to disk): this is the data write strobe for writes to disk. when writing to disk, ich5 drives valid data on rising and falling edges of pdwstb or sdwstb. primary and secondary disk dma ready (ultra dma reads from disk): this is the dma ready for reads from disk. when reading from disk, ich5 deasserts prdmardy# or srdmardy# to pause burst data transfers. pdiow# / (pdstop) sdiow# / (sdstop) o primary and secondary disk i/o write (pio and non-ultra dma): this is the command to the ide device that it may latch data from the pdd or sdd lines. data is latched by the ide device on the deassertion edge of pdiow# or sdiow#. the ide device is selected either by the ata register file chip selects (pdcs1# or sdcs1#, pdcs3# or sdcs3#) and the pda or sda lines, or the ide dma acknowledge (pddak# or sddak#). primary and secondary disk stop (ultra dma): ich5 asserts this signal to terminate a burst. piordy / (pdrstb / pwdmardy#) siordy / (sdrstb / swdmardy#) i primary and secondary i/o channel ready (pio): this signal will keep the strobe active (pdior# or sdior# on reads, pdiow# or sdiow# on writes) longer than the minimum width. it adds wait-states to pio transfers. primary and secondary disk read strobe (ultra dma reads from disk): when reading from disk, ich5 latches data on rising and falling edges of this signal from the disk. primary and secondary disk dma ready (ultra dma writes to disk): when writing to disk, this is de-asserted by the disk to pause burst data transfers. table 10. lpc interface signals name type description lad[3:0] / fb[3:0] i/o lpc multiplexed command, address, data: for lad[3:0], internal pull-ups are provided. lframe# / fb4 o lpc frame: lframe# indicates the start of an lpc cycle, or an abort. ldrq0# ldrq1# / gpio41 i lpc serial dma/master request inputs: ldrq[1:0]# are used to request dma or bus master access. these signals are typically connected to external super i/o device. an internal pull-up resistor is provided on these signals. ldrq1# may optionally be used as gpi. table 9. ide interface signals (sheet 2 of 2) name type description intel ? 82801eb ich5 / 82801er ich5r datasheet 57 signal description 2.9 interrupt interface table 11. interrupt signals name type description serirq i/o serial interrupt request: this pin implements the serial interrupt protocol. pirq[d:a]# i/od pci interrupt requests: in non-apic mode the pirqx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15 as described in section 5.8.6 . each pirqx# line has a separate route control register. in apic mode, these signals are connected to the internal i/o apic in the following fashion: pirqa# is connected to irq16, pirqb# to irq17, pirqc# to irq18, and pirqd# to irq19. this frees the legacy interrupts. pirq[h:e]# / gpio[5:2] i/od pci interrupt requests: in non-apic mode the pirqx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15 as described in section 5.8.6 . each pirqx# line has a separate route control register. in apic mode, these signals are connected to the internal i/o apic in the following fashion: pirqe# is connected to irq20, pirqf# to irq21, pirqg# to irq22, and pirqh# to irq23. this frees the legacy interrupts. if not needed for interrupts, these signals can be used as gpio. irq[14:15] i interrupt request 14?15: these interrupt inputs are connected to the ide drives. irq14 is used by the drives connected to the primary controller and irq15 is used by the drives connected to the secondary controller. 58 intel ? 82801eb ich5 / 82801er ich5r datasheet signal description 2.10 usb interface table 12. usb interface signals name type description usbp0p, usbp0n, usbp1p, usbp1n i/o universal serial bus port 1:0 differential: these differential pairs are used to transmit data/address/command signals for ports 0 and 1. these ports can be routed to uhci controller #1 or the ehci controller. note: no external resistors are required on these signals. the intel ? ich5 integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no external series resistor usbp2p, usbp2n, usbp3p, usbp3n i/o universal serial bus port 3:2 differential: these differential pairs are used to transmit data/address/command signals for ports 2 and 3. these ports can be routed to uhci controller #2 or the ehci controller. note: no external resistors are required on these signals. the ich5 integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no external series resistor usbp4p, usbp4n, usbp5p, usbp5n i/o universal serial bus port 5:4 differential: these differential pairs are used to transmit data/address/command signals for ports 4 and 5. these ports can be routed to uhci controller #3 or the ehci controller. note: no external resistors are required on these signals. the ich5 integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no external series resistor usbp6p, usbp6n, usbp7p, usbp7n i/o universal serial bus port 7:6 differential: these differential pairs are used to transmit data/address/command signals for ports 6and 7. these ports can be routed to uhci controller #4 or the ehci controller. note: no external resistors are required on these signals. the ich5 integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no external series resistor oc[3:0]# oc4# / gpio9 oc5# / gpio10 oc6# / gpio14 oc7# / gpio15 i overcurrent indicators: these signals set corresponding bits in the usb controllers to indicate that an overcurrent condition has occurred. oc[7:4]# may optionally be used as gpis. usbrbias, usbrbias# o usb resistor bias: these are analog connection point for an external resistor to ground. intel ? 82801eb ich5 / 82801er ich5r datasheet 59 signal description 2.11 power management interface table 13. power management interface signals name type description thrm# i thermal alarm: this is an active low signal generated by external hardware to start the hardware clock throttling mode. can also generate an smi# or an sci. thrmtrip# i thermal trip : when low, this signal indicates that a thermal trip from the processor occurred, and the intel ? ich5 will immediately transition to a s5 state. the ich5 will not wait for the processor stop grant cycle since the processor has overheated. slp_s3# o s3 sleep control: slp_s3# is for power plane control. this signal shuts off power to all non-critical systems when in s3 (suspend to ram), s4 (suspend to disk), or s5 (soft off) states. slp_s4# o s4 sleep control : slp_s4# is for power plane control. this signal shuts power to all non-critical systems when in the s4 (suspend to disk) or s5 (soft off) state. note: this pin must be used to control the dram power in order to use the ich5?s dram power-cycling feature. refer to section 5.13.11.2 for details. slp_s5# o s5 sleep control: slp_s5# is for power plane control. this signal is used to shut power off to all non-critical systems when in the s5 (soft off) states. pwrok i power ok: when asserted, pwrok is an indication to the ich5 that core power and pciclk have been stable for at least 99 ms. pwrok can be driven asynchronously. when pwrok is negated, the ich5 asserts pcirst#. note: pwrok must deassert for a minimum of three rtc clock periods in order for the ich5 to fully reset the power and properly generate the pcirst# output pwrbtn# i power button: the power button will cause smi# or sci to indicate a system request to go to a sleep state. if the system is already in a sleep state, this signal will cause a wake event. if pwrbtn# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the s5 state. override will occur even if the system is in the s1-s4 states. this signal has an internal pull- up resistor. ri# i ring indicate: this signal is an input from the modem interface. it can be enabled as a wake event, and this is preserved across power failures. sys_reset# i system reset : this pin forces an internal reset after being debounced. the ich5 will reset immediately if the smbus is idle; otherwise, it will wait up to 25 ms 2 ms for the smbus to idle before forcing a reset on the system. rsmrst# i resume well reset: this signal is used for resetting the resume power plane logic. lan_rst# i lan reset: this signal must be asserted at least 10 ms after the resume well power (vccsus3_3) is valid. when deasserted, this signal is an indication that the resume well power is stable. sus_stat# / lpcpd# o suspend status: this signal is asserted by the ich5 to indicate that the system will be entering a low power state soon. this can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. it can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. this signal is called lpcpd# on the lpc i/f. susclk o suspend clock: this clock is an output of the rtc generator circuit to use by other chips for refresh clock. vrmpwrgd i vrm power good: this should be connected to be the processor?s vrm power good. 60 intel ? 82801eb ich5 / 82801er ich5r datasheet signal description 2.12 processor interface table 14. processor interface signals (sheet 1 of 2) name type description a20m# o mask a20: a20m# will go active based on either setting the appropriate bit in the port 92h register, or based on the a20gate input being active. speed strap: during the reset sequence, the intel ? ich5 drives a20m# high if the corresponding bit is set in the freq_strp register. cpuslp# o cpu sleep: this signal puts the processor into a state that saves substantial power compared to stop-grant state. however, during that time, no snoops occur. the ich5 can optionally assert the cpuslp# signal when going to the s1 state. ferr# i numeric coprocessor error: this signal is tied to the coprocessor error signal on the processor. ferr# is only used if the ich5 coprocessor error reporting function is enabled in the general control register (device 31:function 0, offset d0, bit 13). if ferr# is asserted, the ich5 generates an internal irq13 to its interrupt controller unit. it is also used to gate the ignne# signal to ensure that ignne# is not asserted to the processor unless ferr# is active. ferr# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. note: ferr# can be used in some states for notification by the processor of pending interrupt events. this functionality is independent of the general control register bit setting. ignne# o ignore numeric error: this signal is connected to the ignore error pin on the processor. ignne# is only used if the ich5 coprocessor error reporting function is enabled in the general control register (device 31:function 0, offset d0, bit 13). if ferr# is active, indicating a coprocessor error, a write to the coprocessor error register (f0h) causes the ignne# to be asserted. ignne# remains asserted until ferr# is negated. if ferr# is not asserted when the coprocessor error register is written, the ignne# signal is not asserted. speed strap: during the reset sequence, ich5 drives ignne# high if the corresponding bit is set in the freq_strp register. init# o initialization: init# is asserted by the ich5 for 16 pci clocks to reset the processor. ich5 can be configured to support processor bist. in that case, init# will be active when pcirst# is active. intr o cpu interrupt: intr is asserted by the ich5 to signal the processor that an interrupt request is pending and needs to be serviced. it is an asynchronous output and normally driven low. speed strap: during the reset sequence, ich5 drives intr high if the corresponding bit is set in the freq_strp register. nmi o non-maskable interrupt: nmi is used to force a non-maskable interrupt to the processor. the ich5 can generate an nmi when either serr# or iochk# is asserted. the processor detects an nmi when it detects a rising edge on nmi. nmi is reset by setting the corresponding nmi source enable/disable bit in the nmi status and control register. speed strap: during the reset sequence, ich5 drives nmi high if the corresponding bit is set in the freq_strp register. smi# o system management interrupt: smi# is an active low output synchronous to pciclk. it is asserted by the ich5 in response to one of many enabled hardware or software events. stpclk# o stop clock request: stpclk# is an active low output synchronous to pciclk. it is asserted by the ich5 in response to one of many hardware or software events. when the processor samples stpclk# asserted, it responds by stopping its internal clock. intel ? 82801eb ich5 / 82801er ich5r datasheet 61 signal description 2.13 smbus interface 2.14 system management interface rcin# i keyboard controller reset cpu: the keyboard controller can generate init# to the processor. this saves the external or gate with the ich5?s other sources of init#. when the ich5 detects the assertion of this signal, init# is generated for 16 pci clocks. note: the ich5 will ignore rcin# assertion during transitions to the s3, s4, and s5 states. a20gate i a20 gate: a20gate is from the keyboard controller. the signal acts as an alternative method to force the a20m# signal active. it saves the external or gate needed with various other pcisets. cpupwrgd / gpio49 od cpu power good: this signal should be connected to the processor?s pwrgood input. this is an open-drain output signal (external pull-up resistor required) that represents a logical and of the ich5?s pwrok and vrmpwrgd signals. this signal may optionally be configured as a gpo. table 15. sm bus interface signals name type description smbdata i/od smbus data: external pull-up is required. smbclk i/od smbus clock: external pull-up is required. smbalert# / gpio11 i smbus alert: this signal is used to wake the system or generate smi#. if not used for smbalert#, it can be used as a gpi. table 16. system management interface signals name type description intruder# i intruder detect: this signal can be set to disable system if box detected open. this signal?s status is readable, so it can be used like a gpi if the intruder detection is not needed. smlink[1:0] i/od system management link: smbus link to optional external system management asic or lan controller. external pull-ups are required. note that smlink0 corresponds to an smbus clock signal, and smlink1 corresponds to an smbus data signal. linkalert# i/od smlink alert: this signal is an output from the intel ? ich5 to either the integrated asf or an external management controller in order for the lan?s smlink slave to be serviced. table 14. processor interface signals (sheet 2 of 2) name type description 62 intel ? 82801eb ich5 / 82801er ich5r datasheet signal description 2.15 real time clock interface 2.16 other clocks 2.17 miscellaneous signals table 17. real time clock interface name type description rtcx1 special crystal input 1: this signal is connected to the 32.768 khz crystal. if no external crystal is used, then rtcx1 can be driven with the desired clock rate. rtcx2 special crystal input 2: this signal is connected to the 32.768 khz crystal. if no external crystal is used, then rtcx2 should be left floating. table 18. other clocks name type description clk14 i oscillator clock: used for 8254 timers. runs at 14.31818 mhz. this clock is permitted to stop during s3 (or lower) states. clk48 i 48 mhz clock: used to run the usb controller. runs at 48 mhz. this clock is permitted to stop during s3 (or lower) states. clk66 i 66 mhz clock: used to run the hub interface. runs at 66 mhz. this clock is permitted to stop during s3 (or lower) states. clk100p clk100n i 100 mhz differential clock: these signals are used to run the sata controller. the clock runs at 100 mhz. this clock is permitted to stop during s3 (or lower) states. table 19. miscellaneous signals name type description intvrmen i internal voltage regulator enable: this signal enables the internal 1.5 v suspend regulator. it connects to vccrtc. spkr o speaker: the spkr signal is the output of counter 2 and is internally ?anded? with port 61h bit 1 to provide speaker data enable. this signal drives an external speaker driver device, which in turn drives the system speaker. upon pcirst#, its output state is 0. note: spkr is sampled at the rising edge of pwrok as a functional strap. see section 2.21.1 for more details. there is a weak integrated pull-down resistor on spkr pin. rtcrst# i rtc reset: when asserted, this signal resets register bits in the rtc well. notes: 1. unless entering the xor chain test mode, the rtcrst# input must always be high when all other rtc power planes are on 2. in the case where the rtc battery is not functional or missing on the platform, the rtcrst# pin must rise before the rsmrst# pin. tp0 i test point 0: this signal must have an external pull-up to vccsus3_3. tp1 o test point 1: this signal is not implemented and should be routed to a test point. tp2 o test point 2: this signal is not implemented and should be routed to a test point. intel ? 82801eb ich5 / 82801er ich5r datasheet 63 signal description 2.18 ac-link note: an integrated pull-down resistor on ac_bit_clk is enabled when either: - the aclink shutoff bit in the ac?97 global control register (see section 15.2.8 ) is set to 1, or - both function 5 and function 6 of device 31 are disabled. otherwise, the integrated pull-down resistor is disabled. 2.19 general purpose i/o table 20. ac-link signals name type description ac_rst# o ac ?97 reset: master hardware reset to external codec(s). ac_sync o ac ?97 sync: 48 khz fixed rate sample sync to the codec(s). ac_bit_clk i ac ?97 bit clock: 12.288 mhz serial data clock generated by the external codec(s). this signal has an integrated pull-down resistor (see note below). ac_sdout o ac ?97 serial data out: serial tdm data output to the codec(s). note: ac_sdout is sampled at the rising edge of pwrok as a functional strap. see section 2.21.1 for more details. ac_sdin[2:0] i ac ?97 serial data in 2:0 : serial tdm data inputs from the three codecs. table 21. general purpose i/o signals (sheet 1 of 2) name type description gpio49 od fixed as output only. processor i/f power well. can instead be used as cpupwrgd. gpio48 o fixed as output only. main power well. can instead be used as gnt4#. gpio[47:42] n/a not implemented. gpio41 i fixed as input only. main power well. can be used instead as ldrq1#. gpio40 i fixed as input only. main power well. can be used instead as req4#. gpio[39:35] n/a not implemented. gpio34 i/o can be input or output. main power well. not multiplexed. gpio33 n/a not implemented. gpio32 i/o can be input or output. main power well. not multiplexed. gpio[31:29] n/a not implemented. gpio[28:27] i/o can be input or output. resume power well. not multiplexed. gpio26 i/o not implemented. gpio25 i/o can be input or output. resume power well. not multiplexed. gpio24 i/o can be input or output. resume power well. gpio23 o fixed as output only. main power well. gpio22 od fixed as output only. main power well. gpio21 o fixed as output only. main power well. 64 intel ? 82801eb ich5 / 82801er ich5r datasheet signal description note: gpio[0:7] are 5 v tolerant. gpio[8:49] not 5 v tolerant. gpio20 o fixed as output only. main power well. gpio19 o fixed as output only. main power well. gpio18 o fixed as output only. main power well. gpio[17:16] o fixed as output only. main power well. can be used instead as pc/pci gnt[a:b]#. gpio17 can also alternatively be used for pci gnt5#. integrated pull-up resistor. gpio[15:14] i fixed as input only. resume power well. can be used instead as oc[7:6]#. gpio[13:12] i fixed as input only. resume power well. not multiplexed. gpio11 i fixed as input only. resume power well. can be used instead as smbalert#. gpio[10:9] i fixed as input only. resume power well. can be used instead as oc[5:4]#. gpio8 i fixed as input only. resume power well. not multiplexed. this gpio is recommended for use as the communications streaming architecture (csa) pme# signal to provide wake-on-lan capabilities. the gpi_inv bit corresponding to gpio8 must be set in order to achieve the correct polarity in the general purpose event 0 status register. gpio7 i fixed as input only. main power well. not multiplexed. gpio6 i fixed as input only. main power well. gpio[5:2] i fixed as input only. main power well. can be used instead as pirq[e:h]#. gpio[1:0] i fixed as input only. main power well. can be used instead as pc/pci req[a:b]#. gpio1 can also alternatively be used for pci req5#. table 21. general purpose i/o signals (sheet 2 of 2) name type description intel ? 82801eb ich5 / 82801er ich5r datasheet 65 signal description 2.20 power and ground table 22. power and ground signals name description vcc3_3 3.3 v supply for core well i/o buffers (18 pins). this power may be shut off in s3, s4, s5 or g3 states. vcc1_5 1.5 v supply for core well logic and hub interface logic (25 pins). this power may be shut off in s3, s4, s5, or g3 states. v5ref reference for 5 v tolerance on core well inputs (2 pins). this power may be shut off in s3, s4, s5, or g3 states. hiref 350 mv analog input for hub interface (1 pin). this power is shut off in s3, s4, s5, and g3 states. vccsus3_3 3.3 v supply for resume well i/o buffers (10 pins). this power is not expected to be shut off unless the system is unplugged. vccsus1_5_a 1.5 v supply for resume well logic (1 pin). this power is not expected to be shut off unless ac power is not available. note: 1. this voltage plane is generated internally 2. do not connect the three sets of vccsus1_5_x signal groups on the intel ? ich5 together. each group needs to be independently connected to its corresponding decoupling capacitor for optimum noise isolation. vccsus1_5_b 1.5 v supply for resume well logic (3 pins). this power is not expected to be shut off unless ac power is not available. note: 1. this voltage plane is generated internally 2. do not connect the three sets of vccsus1_5_x signal groups on the ich5 together. each group needs to be independently connected to its corresponding decoupling capacitor for optimum noise isolation. vccsus1_5_c 1.5 v supply for resume well logic (2 pins). this power is not expected to be shut off unless ac power is not available. note: 1. this voltage plane is generated internally 2. do not connect the three sets of vccsus1_5_x signal groups on the ich5 together. each group needs to be independently connected to its corresponding decoupling capacitor for optimum noise isolation. v5ref_sus reference for 5 v tolerance on resume well inputs (1 pin). this power is not expected to be shut off unless the system is unplugged. vccrtc 3.3 v (can drop to 1.0 v min. in g3 state) supply for the rtc well (1 pin). this power is not expected to be shut off unless the rtc battery is removed or completely drained. note: implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. clearing cmos in an ich5-based platform can be done by using a jumper on rtcrst# or gpi, or using safemode strap. vccusbpll 1.5 v supply for core well logic (1 pin). this signal is used for the usb pll. this power may be shut off in s3, s4, s5, or g3 states. vccsatapll 1.5 v supply for core well logic (2 pins). this signal is used for the sata pll. this power may be shut off in s3, s4, s5, or g3 states. v_cpu_io powered by the same supply as the processor i/o voltage (3 pins). this supply is used to drive the processor interface signals listed in table 14 . vss grounds (119 pins). 66 intel ? 82801eb ich5 / 82801er ich5r datasheet signal description 2.21 pin straps 2.21.1 functional straps the following signals are used for static configuration. they are sampled at the rising edge of pwrok to select configurations, and then revert later to their normal usage. to invoke the associated mode, the signal should be driven at least four pci clocks prior to the time it is sampled. table 23. functional strap definitions signal usage when sampled comment ac_sdout safe mode rising edge of pwrok the signal has a weak internal pull-down. if the signal is sampled high, the intel ? ich5 will set the processor speed strap pins for safe mode. refer to the processor specification for speed strapping definition. the status of this strap is readable via the safe_mode bit (bit 2, d31: f0, offset d4h). gnta# top-block swap override rising edge of pwrok the signal has a weak internal pull-up. if the signal is sampled low, this indicates that the system is strapped to the ?top-block swap? mode (ich5 inverts a16 for all cycles targeting fwh bios space). the status of this strap is readable via the top_swap bit (bit 13, d31: f0, offset d4h). note that software will not be able to clear the top- swap bit until the system is rebooted without gnta# being pulled down. gnt5# / gntb / gpio17 reserved this signal has a weak internal pull-up. note: this signal should not be pulled low. tp1 reserved this signal has a weak internal pull-down. note: this signal should not be pulled high. ac_sync reserved this signal has a weak internal pull-down. linkalert# reserved this signal requires an external pullup resistor. spkr no reboot rising edge of pwrok the signal has a weak internal pull-down. if the signal is sampled high, this indicates that the system is strapped to the ?no reboot? mode (ich5 will disable the tco timer system reboot feature). the status of this strap is readable via the no_reboot bit (bit 1, d31: f0, offset d4h). intel ? 82801eb ich5 / 82801er ich5r datasheet 67 signal description 2.21.2 external rtc circuitry to reduce rtc well power consumption, the ich5 implements an internal oscillator circuit that is sensitive to step voltage changes in vccrtc. figure 2 shows a schematic diagram of the circuitry required to condition these voltages to ensure correct operation of the ich5 rtc. note: c1 and c2 depend on crystal load. 2.21.3 power sequencing requirements 2.21.3.1 v5ref / vcc3_3 sequencing requirements v5ref is the reference voltage for 5 v tolerance on inputs to the ich5. v5ref must be powered up before vcc3_3, or after vcc3_3 within 0.7 v. also, v5ref must power down after vcc3_3, or before vcc3_3 within 0.7 v. the rule must be followed in order to ensure the safety of the ich5. if the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the vcc3_3 rail. figure 3 shows a sample implementation of how to satisfy the v5ref/3.3 v sequencing rule. this rule also applies to the standby rails, but in most platforms, the vccsus3_3 rail is derived from the vccsus5 rail; therefore, the vccsus3_3 rail will always come up after the vccsus5 rail. as a result, v5ref_sus will always be powered up before vccsus3_3. in platforms that do not derive the vccsus3_3 rail from the vccsus5 rail, this rule must be comprehended in the platform design. figure 2. example external rtc circuit 32.768 khz xtal 0.1 f c2 15 pf vccrtc rtcx2 rtcx1 vbatt 1 f 1 k ? vccsus3_3 c1 15 pf + r1 10 m ? ? rtcrst# 100 k ? figure 3. example v5ref sequencing circuit vcc3_3 1 k ? 5 v supply 1 f to system 5vref to system schottky diode 68 intel ? 82801eb ich5 / 82801er ich5r datasheet signal description 2.21.3.2 3.3 v/1.5 v standby power sequencing requirements there is an integrated 1.5 v standby regulator that is used to power the resume well of the ich5. due to the use of this internal regulator, there are no power sequencing requirements for associated 3.3 v/1.5 v (standby or core) rails of the ich5. 2.21.4 test signals 2.21.4.1 test mode selection when pwrok is active (high) for at least 76 pci clocks, driving rtcrst# active (low) for a number of pci clocks (33 mhz) will activate a particular test mode a specified in table 24 . note: rtcrst# may be driven low any time after pcirst is inactive. refer to chapter 21 for a detailed description of the ich5 test modes. . table 24. test mode selection number of pci clocks rtcrst# driven low after pwrok active test mode <4 no test mode selected 4 xor chain 1 5 xor chain 2 6 xor chain 3 7 xor chain 4 8 all ?z? 9?13 reserved. do not attempt 14 long xor 15?42 reserved. do not attempt 43?51 no test mode selected 52 xor chain 6 53 xor chain 4 bandgap >53 no test mode selected intel ? 82801eb ich5 / 82801er ich5r datasheet 69 intel ? ich5 power planes and pin states intel ? ich5 power planes and pin states 3 3.1 power planes table 25. intel ? ich5 power planes plane description main i/o (3.3 v) vcc3_3: powered by the main power supply. when the system is in the s3, s4, s5, or g3 state, this plane is assumed to be shut off. main logic (1.5 v) vcc1_5: powered by the main power supply. when the system is in the s3, s4, s5, or g3 state, this plane is assumed to be shut off. resume i/o (3.3 v standby) vccsus3_3: powered by the main power supply in s0?s1 states. powered by the trickle power supply when the system is in the s3, s4, or s5 state. assumed to be shut off only when in the g3 state (system is unplugged). resume logic (1.5 v standby) vccsus1_5: powered by the main power supply in s0?s1 states. powered by the trickle power supply when the system is in the s3, s4, or s5 state. assumed to be shut off only when in the g3 state (system is unplugged). these planes are generated from the integrated vrm. processor i/f (0.8 ~ 1.75 v) v_cpu_io: powered by the main power supply via processor voltage regulator. when the system is in the s3, s4, s5, or g3 state, this plane is assumed to be shut off. rtc vccrtc: when other power is available (from the main supply), external diode coupling will provide power to reduce the drain on the rtc battery. the batter is assumed to operate from 3.3 v down to 1.0 v. 70 intel ? 82801eb ich5 / 82801er ich5r datasheet intel ? ich5 power planes and pin states 3.2 integrated pull-ups and pull-downs notes: 1. simulation data shows that these resistor values can range from 10 k ? to 40 k ? . 2. simulation data shows that these resistor values can range from 9 k ? to 50 k ? . 3. simulation data shows that these resistor values can range from 15 k ? to 35 k ?. 4. simulation data shows that these resistor values can range from 7.5 k ? to 16 k ? . 5. simulation data shows that these resistor values can range from 45 k ? to 170 k ?. 6. simulation data shows that these resistor values can range from 5.7 k ? to 28.3 k ? . 7. simulation data shows that these resistor values can range from 14.25 k ? to 24.8 k ?. 8. the pull-up or pull-down on this signal is only enabled at boot/reset for strapping function. 9. the pull-down on this signal is enabled when the aclink shutoff bit in the ac ?97 global control register is set to 1. table 26. integrated pull-up and pull-down resistors signal resistor type nominal value notes ac_bitclk pull-down 20 k ? 1, 9 ac_rst# pull-down 20 k ? 2, 9 ac_sdin[2:0] pull-down 20 k ? 2 ac_sdout pull-down 20 k ? 2, 8, 9 ac_sync pull-down 20 k ? 2, 8, 9 ee_din pull-up 20 k ? 3 ee_dout pull-up 20 k ? 3 ee_cs pull-up 20 k ? 3 gnt[b:a]# / gnt5# / gpio[17:16] pull-up 20 k ? 3, 8 lad[3:0]# / fb[3:0]# pull-up 20 k ? 3 ldrq[1:0] / gpio41 pull-up 20 k ? 3 lan_rxd[2:0] pull-up 10 k ? 4 lan_clk pull-down 100 k ? 5 pme# pull-up 20 k ? 3 pwrbtn# pull-up 20 k ? 3 pdd7 / sdd7 pull-down 11.5 k ? 6 pddreq / sddreq pull-down 11.5 k ? 6 spkr pull-down 20 k ? 2, 8 tp1 pull-down 20 k ? 2, 8 usb[7:0] [p,n] pull-down 15 k ? 7 intel ? 82801eb ich5 / 82801er ich5r datasheet 71 intel ? ich5 power planes and pin states 3.3 ide integrated series termination resistors table 27 shows the ich5 ide signals that have integrated series termination resistors. note: simulation data indicates that the integrated series termination resistors are a nominal 33 ? but can range from 21 ? to 75 ? . 3.4 output and i/o signals planes and states table 28 shows the power plane associated with the output and i/o signals, as well as the state at various times. within the table, the following terms are used: ?high-z? tri-state. ich5 not driving the signal high or low. ?high? ich5 is driving the signal to a logic 1 ?low? ich5 is driving the signal to a logic 0 ?defined? driven to a level that is defined by the function (will be high or low) ?undefined? ich5 is driving the signal, but the value is indeterminate. ?running? clock is toggling or signal is transitioning because function not stopping ?off? the power plane is off, so ich5 is not driving note that the signal levels are the same in s4 and s5. table 27. ide series termination resistors signal integrated series termination resistor value pdd[15:0], sdd[15:0], pdiow#, sdiow#, pdior#, sdior#, pdreq, sdreq, pddack#, sddack#, piordy, siordy, pda[2:0], sda[2:0], pdcs1#, sdcs1#, pdcs3#, sdcs3#, irq14, irq15 approximately 33 ? (see note) 72 intel ? 82801eb ich5 / 82801er ich5r datasheet intel ? ich5 power planes and pin states table 28. power plane and states for output and i/o signal (sheet 1 of 3) signal name power plane during pcirst# 4 / rsmrst# 5 immediately after pcirst# 4 / rsmrst# 5 s1 s3 s4/s5 pci bus ad[31:0] main i/o high-z undefined defined off off c/be[3:0]# main i/o high-z undefined defined off off devsel# main i/o high-z high-z high-z off off frame# main i/o high-z high-z high-z off off gnt[4:0]# main i/o high high high off off gnt[a:b]# main i/o high-z with internal pull- up high high off off irdy#, trdy# main i/o high-z high-z high-z off off par main i/o high-z undefined defined off off pcirst# resume i/o low high high low low perr# main i/o high-z high-z high-z off off plock# main i/o high-z high-z high-z off off stop# main i/o high-z high-z high-z off off lpc interface lad[3:0] main i/o high high high off off lframe# main i/o high high high off off lan connect and eeprom interface ee_cs resume i/o high running defined defined defined ee_dout resume i/o high high defined defined defined ee_shclk resume i/o low running defined defined defined lan_rstsync resume i/o high low defined defined defined lan_txd[2:0] resume i/o low low defined defined defined ide interface pda[2:0], sda[2:0] main i/o undefined undefined undefined off off pdcs1#, pdcs3# main i/o high high high off off pdd[15:8], sdd[15:8], pdd[6:0], sdd[6:0] main i/o high-z high-z high-z off off pdd7, sdd7 main i/o low low low off off pddack#, sddack# main i/o high high high off off pdior#, pdiow# main i/o high high high off off sdcs1#, sdcs3# main i/o high high high off off sdior#, sdiow# main i/o high high high off off intel ? 82801eb ich5 / 82801er ich5r datasheet 73 intel ? ich5 power planes and pin states sata interface sata0txp, sata0txn sata1txp, sata1txn main i/o high-z high-z defined off off satarbias main i/o high-z high-z defined defined defined sataled# main i/o low high-z defined off off interrupts pirq[a:h]# main i/o high-z high-z high-z off off serirq main i/o high-z high-z high-z off off usb interface usbp[7:0][p,n] resume i/o low low low low low usbrbias resume i/o high-z high-z defined defined defined power management slp_s3# resume i/o low high high low low slp_s4# resume i/o low high high high low slp_s5# resume i/o low high high high low sus_stat# resume i/o low high high low low susclk resume i/o running processor interface a20m# cpu i/o see note 1 high high off off cpupwrgd cpu i/o see note 3 high-z high-z off off cpuslp# cpu i/o high high defined off off ignne# cpu i/o see note 1 high high off off init# cpu i/o high high high off off intr cpu i/o see note 1 low low off off nmi cpu i/o see note 1 low low off off smi# cpu i/o high high high off off stpclk# cpu i/o high high low off off table 28. power plane and states for output and i/o signal (sheet 2 of 3) signal name power plane during pcirst# 4 / rsmrst# 5 immediately after pcirst# 4 / rsmrst# 5 s1 s3 s4/s5 74 intel ? 82801eb ich5 / 82801er ich5r datasheet intel ? ich5 power planes and pin states notes: 1. ich5 sets these signals at reset for processor frequency strap. 2. gpio18 will toggle at a frequency of approximately 1 hz when the ich5 comes out of reset 3. cpupwrgd is an open-drain output that represents a logical and of the ich5?s vrmpwrgd and pwrok signals, and thus will be driven low by ich5 when either vrmpwrgd or pwrok are inactive. during boot, or during a hard reset with power cycling, cpupwrgd will be expected to transition from low to high-z. 4. the states of main i/o signals are taken at the times during pcirst# and immediately after pcirst#. 5. the states of resume i/o signals are taken at the times during rsmrst# and immediately after rsmrst#. 6. gpio48 is an open-drain output. during boot, or during a hard reset with power cycling, gpio48 will be expected to transition from low to high-z. smbus interface smbclk, smbdata resume i/o high-z high-z defined defined defined system management interface smlink[1:0] resume i/o high-z high-z defined defined defined linkalert# resume i/o high-z high-z defined defined defined miscellaneous signals spkr main i/o low with internal pull- down low defined off off ac ?97 interface ac_rst# resume i/o low low cold reset bit (high) low low ac_sdout main i/o low running low off off ac_sync main i/o low running low off off multiplexed gpio signals gpio[17:16] main i/o high-z with internal pull- up high high off off gpio48 main i/o high high high off off gpio49 cpu i/o see note 6 high-z high-z off off unmultiplexed gpio signals gpio18 main i/o high see note 2 defined off off gpio[20:19] main i/o high high defined off off gpio21 main i/o high high defined off off gpio22 main i/o high-z high-z defined off off gpio23 main i/o low low defined off off gpio24 resume i/o high high defined defined defined gpio25 resume i/o high high defined defined defined gpio[28:27] resume i/o high high defined defined defined gpio32 main i/o high high defined off off gpio34 main i/o high high defined off off table 28. power plane and states for output and i/o signal (sheet 3 of 3) signal name power plane during pcirst# 4 / rsmrst# 5 immediately after pcirst# 4 / rsmrst# 5 s1 s3 s4/s5 intel ? 82801eb ich5 / 82801er ich5r datasheet 75 intel ? ich5 power planes and pin states 3.5 power planes for input signals table 29 shows the power plane associated with each input signal, as well as what device drives the signal at various times. valid states include: high low static: will be high or low, but will not change driven: will be high or low, and is allowed to change running: for input clocks table 29. power plane for input signals (sheet 1 of 2) signal name power well driver during reset s1 s3 s5 a20gate main i/o external microcontroller static low low ac_bit_clk main i/o ac ?97 codec low low low ac_sdin[2:0] resume i/o ac ?97 codec low low low clk14 main i/o clock generator running low low clk48 main i/o clock generator running low low clk66 main logic clock generator running low low clk100p clk100n main logic clock generator running low low ee_din resume i/o eeprom component driven driven driven ferr# cpu i/o processor static low low gpio[1:0] main i/o external circuit driven low low gpio[5:2] main i/o external circuit driven driven driven gpio[10:9] resume i/o external pull-ups driven driven driven gpio11 resume i/o external pull-up driven driven driven gpio[15:14] resume i/o external pull-ups driven driven driven gpio40 main i/o external circuit driven low low gpio41 main i/o external circuit high low low intruder# rtc external switch driven driven driven intvrmen rtc external pull-up driven driven driven irq[15:14] main i/o ide device static low low lan_clk resume i/o lan connect component driven driven driven lan_rst# resume i/o external rc circuit high high high lan_rxd[2:0] resume i/o lan connect component driven driven driven ldrq0# main i/o lpc devices high low low ldrq1# main i/o lpc devices high low low oc[7:0]# resume i/o external pull-ups driven driven driven pciclk main i/o clock generator running low low pddreq main i/o ide device static low low 76 intel ? 82801eb ich5 / 82801er ich5r datasheet intel ? ich5 power planes and pin states piordy main i/o ide device static low low pme# resume i/o internal pull-up driven driven driven pwrbtn# resume i/o internal pull-up driven driven driven pwrok rtc system power supply driven low low rcin# main i/o external microcontroller high low low req[5:0]# main i/o pci master driven low low req[b:a]# main i/o pc/pci devices driven low low ri# resume i/o serial port buffer driven driven driven rsmrst# rtc external rc circuit high high high rtcrst# rtc external rc circuit high high high sata0rxp, sata0rxn sata1rxp, sata1rxn main logic sata device driven driven driven satarbias# main logic external pull-down driven driven driven sddreq main i/o ide device static low low serr# main i/o pci bus peripherals high low low siordy main i/o ide device static low low smbalert# resume i/o external pull-up driven driven driven sys_reset# resume i/o external circuit driven driven driven thrm# main i/o thermal sensor driven low low thrmtrip# cpu i/o thermal sensor driven low low usbrbias# resume i/o external pull-down driven driven driven vrmpwrgd main i/o processor voltage regulator high low low table 29. power plane for input signals (sheet 2 of 2) signal name power well driver during reset s1 s3 s5 intel ? 82801eb ich5 / 82801er ich5r datasheet 77 intel ? ich5 and system clock domains intel ? ich5 and system clock domains 4 table 30 shows the system clock domains. figure 4 shows the assumed connection of the various system components, including the clock generator. for complete details of the system clocking solution, refer to the system?s clock generator component specification. table 30. intel ? ich5 and system clock domains clock domain frequency source usage ich5 clk100 100 mhz main clock generator differential clock pair used for sata. ich5 clk66 66 mhz main clock generator hub i/f, processor i/f. shut off during s3 or below. ich5 pciclk 33 mhz main clock generator free-running pci clock to the intel ? ich5. this clock remains on during s0 and s1 state, and is expected to be shut off during s3 or below. system pci 33 mhz main clock generator pci bus, lpc i/f. these only go to external pci and lpc devices. ich5 clk48 48 mhz main clock generator super i/o, usb controllers. expected to be shut off during s3 or below. ich5 clk14 14.31818 mhz main clock generator used for acpi timer and high-precision event timers. expected to be shut off during s3 or below. ich5 ac_bit_clk 12.288 mhz ac ?97 codec ac-link. generated by ac ?97 codec. can be shut by codec in d3. expected to be shut off during s3 or below. lan_clk 5 to 50 mhz lan connect component generated by the lan connect component. expected to be shut off during s3 or below. 78 intel ? 82801eb ich5 / 82801er ich5r datasheet intel ? ich5 and system clock domains figure 4. conceptual system clock diagram intel ? ich5 pci clocks (33 mhz) clock gen. 14.31818 mhz 48 mhz 32 khz xtal susclk# (32 khz) lan connect 50 mhz ac?97 codec(s) 12.288 mhz 66 mhz 33 mhz 14.31818 mhz 48 mhz 100 mhz diff. pair intel ? 82801eb ich5 / 82801er ich5r datasheet 79 functional description functional description 5 this chapter describes the functions and interfaces of the ich5. 5.1 hub interface to pci bridge (d30:f0) the hub interface to pci bridge resides in pci device 30, function 0 on bus #0. this portion of the ich5 implements the buffering and control logic between pci and the hub interface. the arbitration for the pci bus is handled by this pci device. the pci decoder in this device must decode the ranges for the hub interface. all register contents are lost when core well power is removed. 5.1.1 pci bus interface the ich5 pci interface provides a 33 mhz, pci local bus specification, revision 2.3 -compliant implementation. all pci signals are 5 v tolerant (except pme#). the ich5 integrates a pci arbiter that supports up to six external pci bus masters in addition to the internal ich5 requests. note that most transactions targeted to the ich5 first appear on the external pci bus before being claimed back by the ich5. the exceptions are i/o cycles involving usb, ide, sata, and ac ?97. these transactions complete over the hub interface without appearing on the external pci bus. configuration cycles targeting usb, ide, sata, or ac ?97 appear on the pci bus. if the ich5 is programmed for positive decode, the ich5 claims the cycles appearing on the external pci bus in medium decode time. if the ich5 is programmed for subtractive decode, the ich5 claims these cycles in subtractive time. if the ich5 is programmed for subtractive decode, these cycles can be claimed by another positive decode agent out on pci. this architecture enables the ability to boot off of a pci card that positively decodes the boot cycles. in order to boot off a pci card it is necessary to keep the ich5 in subtractive decode mode. when booting off a pci card, the boot_sts bit (bit 2, tco2 status register) will be set. note: the ich5?s ac ?97, ide and usb controllers cannot perform peer-to-peer traffic. note: pci bus masters should not use memory area locations as a target if that area is programmed to anything but read/write. note: pci configuration write cycles, initiated by the processor, with the following characteristics are converted to a special cycle with the shutdown message type. ? device number (ad[15:11]) = 11111 ? function number (ad[10:8]) = 111 ? register number (ad[7:2]) = 000000 ? data = 00h ? bus number matches secondary bus number 80 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description note: if the processor issues a locked cycle to a resource that is too slow (e.g., pci), the ich5 does not allow upstream requests to be performed until the cycle completes. this may be critical for isochronous buses that assume certain timing for their data flow (e.g., ac ?97 or usb). devices on these buses may suffer from underrun if the asynchronous traffic is too heavy. underrun means that the same data is sent over the bus while ich5 is not able to issue a request for the next data. snoop cycles are not permitted while the front side bus is locked. note: locked cycles are assumed to be rare. locks by pci targets are assumed to exist for a short duration (a few microseconds at most). if a system has a very large number of locked cycles and some that are very long, the system will definitely experience underruns and overruns. the units most likely to have problems are the ac ?97 controller and the usb controllers. other units could get underruns/overruns, but are much less likely. the ide controller (due to its stalling capability on the cable) should not get any underruns or overruns. 5.1.2 pci-to-pci bridge model from a software perspective, the ich5 contains a pci-to-pci bridge. this bridge connects the hub interface to the pci bus. by using the pci-to-pci bridge software model, the ich5 can have its decode ranges programmed by existing plug-and-play software such that pci ranges do not conflict with agp and graphics aperture ranges in the host controller. 5.1.3 idsel to device number mapping when addressing devices on the external pci bus (with the pci slots), the ich5 asserts one address signal as an idsel. when accessing device 0, the ich5 asserts ad16. when accessing device 1, the ich5 asserts ad17. this mapping continues all the way up to device 15 where the ich5 asserts ad31. note that the ich5?s internal functions (ac ?97, ide, usb, sata and pci bridge) are enumerated like they are on a separate pci bus (the hub interface) from the external pci bus. the integrated lan controller is device 8 on the ich5?s pci bus, and hence it uses ad24 for idsel. 5.1.4 serr# functionality there are several internal and external sources that can cause serr#. the ich5 can be programmed to cause an nmi based on detecting that an serr# condition has occurred. the nmi can also be routed to instead cause an smi#. note that the ich5 does not drive the external pci bus serr# signal active onto the pci bus. the external serr# signal is an input into the ich5 driven only by external pci devices. the conceptual logic diagrams in figure 5 and figure 6 illustrate all sources of serr#, along with their respective enable and status bits. figure 7 shows how the ich5 error reporting logic is configured for nmi# generation. intel ? 82801eb ich5 / 82801er ich5r datasheet 81 functional description figure 5. primary device status register error reporting logic figure 6. secondary status register error reporting logic an d or an d d 30:f0 b r id ge _c n t [p ari ty e rror r es pons e e nabl e] d 30:f0 b r id ge _c n t [serr# enable] pci address parity error d 30:f0 c md [s e r r _e n ] d 30:f0 p d _s ts [sse] an d an d an d or serr# pin d 30:f0 b r id ge _c n t [serr# enable] d30:f0 err_cmd [serr_rta_en] r eceived target a bort d 30:f0 c md [serr_en] d 30:f0 e r r _s ts [serr_rta] and or and and d30:f0 secsts [sse] d30:f0 bridge_cnt [serr# enable] pci delayed transaction timeout d31:f0 d31_err_cfg [serr_dtt_en] lpc device signaling an error iochk# via serirq tco1_sts [huberr_sts] d31:f0 d31_err_cfg [serr_rta_en] received target abort 82 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.1.5 parity error detection the ich5 can detect and report different parity errors in the system. the ich5 can be programmed to cause an nmi (or smi# if nmi is routed to smi#) based on detecting a parity error. the conceptual logic diagram in figure 7 details all the parity errors that the ich5 can detect, along with their respective enable bits, status bits, and the results. for hub interface-to-pci data packets, with mch?s that generate hi parity, the ich5 provides the ability to generate bad parity on all data driven by the ich5 when bad data parity was detected on hub interface. this prevents pci agents that are capable of checking parity from taking corrupted data unknowingly. this state can be entered due to either hub interface-to-pci write data or hub interface-to-pci read completion data. this mode is enabled by d30.f0.50h.bit 19 and reported in d30.f0.92h.bit 0. note: the hp_unsupported bit (d30:f0:40h bit 20) must be cleared for any of the parity checking enable bits to have any effect. note: if nmis are enabled, and parity error checking on pci is also enabled, then parity errors will cause an nmi. some operating systems will not attempt to recover from this nmi, since it considers the detection of a pci error to be a catastrophic event. figure 7. nmi# generation logic and iochk from serirq logic nmi_sc [iochk_nmi_en] and to nmi# output and gating logic or nmi_sc [iochk_nmi_sts] and nmi_sc [serr#_nmi_sts] nmi_sc [pci_serr_en] or d30:f0 secsts [sse] d30:f0 pdsts [sse] or and or tco1_sts [hubnmi_sts] tco1_cnt [nmi_now] nmi_en [nmi_en] d30:f0 pd_sts [dpd] d30:f0 secsts [dpd] pci parity error detected during ac'97, ide or usb master cycle d30:f0 bridge_cnt [parity error response enable] and d31:f0 pcista [dped] pci parity error detected during lpc or legacy dma master cycle d31:f0 pcicmd [per] and hub interface parity error detected d30:f0 cmd [parity error response] intel ? 82801eb ich5 / 82801er ich5r datasheet 83 functional description 5.1.6 standard pci bus configuration mechanism the pci bus defines a slot based ?configuration space? that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. the pci local bus specification, revision 2.3 defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the processor. configuration space is supported by a mapping mechanism implemented within the ich5. the pci local bus specification, revision 2.3 defines two mechanisms to access configuration space, mechanism 1 and mechanism 2. the ich5 only supports mechanism 1. configuration cycles for pci bus 0 devices 2 through 31, and for pci bus numbers greater than 0 are sent towards the ich5 from the host controller. the ich5 compares the non-zero bus number with the secondary bus number and subordinate bus number registers of its pci-to-pci bridge to determine if the configuration cycle is meant for primary pci or a downstream pci bus. note: configuration writes to internal devices, when the devices are disabled, are illegal and may cause undefined results. 5.1.6.1 type 0 to type 0 forwarding when a type 0 configuration cycle is received on hub interface to any function other than ehci or ac ?97, the ich5 forwards these cycles to pci and then reclaims them. the ich5 uses address bits ad[15:13] to communicate the ich5 device numbers in type 0 configuration cycles. if the type 0 cycle on hub interface specifies any device number other than 29, 30 or 31, the ich5 will not set any address bits in the range ad[31:11] during the corresponding transaction on pci. table 31 shows the device number translation. the ich5 logic generates single dword configuration read and write cycles on the pci bus. the ich5 generates a type 0 configuration cycle for configurations to the bus number matching the pci bus. type 1 configuration cycles are converted to type 0 cycles in this case. if the cycle is targeting a device behind an external bridge, the ich5 runs a type 1 cycle on the pci bus. 5.1.6.2 type 1 to type 0 conversion when the bus number for the type 1 configuration cycle matches the pci (secondary) bus number, the ich5 converts the address as follows: 1. for device numbers 0 through 15, only 1 bit of the pci address [31:16] is set. if the device number is 0, ad16 is set; if the device number is 1, ad17 is set; etc. 2. the ich5 always drives 0s on bits ad[15:11] when converting type 1 configurations cycles to type 0 configuration cycles on pci. 3. address bits [10:1] are also be passed unchanged to pci. 4. address bit 0 is changed to 0. table 31. type 0 configuration cycle device number translation device # in hub interface type 0 cycle ad[31:11] during address phase of type 0 cycle on pci 0 through 28 0000000000000000_00000b 29 0000000000000000_00100b 30 0000000000000000_01000b 31 0000000000000000_10000b 84 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.1.7 pci dual address cycle (dac) support the ich5 supports dual address cycle (dac) format on pci for cycles from pci initiators to main memory. this allows pci masters to generate an address up to 44 bits. the size of the actual supported memory space is determined by the memory controller and the processor. the dac mode is only supported for pci adapters and usb ehc, and is not supported for any of the internal pci masters (ide, lan, usb uhc, ac ?97, 8237 dma, etc.). when a pci master wants to initiate a cycle with an address above 4 g, it follows the following behavioral rules (see pci local bus specification, revision 2.3 , section 3.9 for more details): 1. on the first clock of the cycle (when frame# is first active), the peripheral uses the dac encoding on the c/be# signals. this unique encoding is: 1101. 2. also during the first clock, the peripheral drives the ad[31:0] signals with the low address. 3. on the second clock, the peripheral drives ad[31:0] with the high address. the address is right justified: a[43:32] appear on ad[12:0]. the value of ad[31:13] is expected to be 0; however, the ich5 ignores these bits. c/be# indicate the bus command type (memory read, memory write, etc.) 4. the rest of the cycle proceeds normally. 5.2 lan controller (b1:d8:f0) the ich5?s integrated lan controller includes a 32-bit pci controller that provides enhanced scatter-gather bus mastering capabilities and enables the lan controller to perform high-speed data transfers over the pci bus. its bus master capabilities enable the component to process high level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. two large transmit and receive fifos of 3 kb each help prevent data underruns and overruns while waiting for bus accesses. this enables the integrated lan controller to transmit data with minimum interframe spacing (ifs). the ich5 integrated lan controller can operate in either full-duplex or half-duplex mode. in full- duplex mode the lan controller adheres with the ieee 802.3x flow control specification . half duplex performance is enhanced by a proprietary collision reduction mechanism. the integrated lan controller also includes an interface to a serial (4-pin) eeprom. the eeprom provides power-on initialization for hardware and software configuration parameters. from a software perspective, the integrated lan controller appears to reside on the secondary side of the ich5?s virtual pci-to-pci bridge (see section 5.1.2 ). this is typically bus 1, but may be assigned a different number, depending upon system configuration. intel ? 82801eb ich5 / 82801er ich5r datasheet 85 functional description the following summarizes the ich5 lan controller features: ? compliance with advanced configuration and power interface and pci power management standards ? support for wake-up on interesting packets and link status change ? support for remote power-up using wake on lan* (wol) technology ? deep power-down mode support ? support of wired for management (wfm) revision 2.0 ? backward compatible software with 82550, 82557, 82558 and 82559 ? tcp/udp checksum off load capabilities ? support for intel?s adaptive technology 5.2.1 lan controller architectural overview figure 8 is a high-level block diagram of the ich5 integrated lan controller. it is divided into four main subsystems: a parallel subsystem, a fifo subsystem, and the carrier-sense multiple access with collision detect (csma/cd) unit. figure 8. integrated lan controller block diagram csma/cd unit data interface unit (diu) four channel addressing unit - dma pci bus interface unit (biu) pci target and eeprom interface micro- machine dual ported fifo 3 kbyte rx fifo fifo control 3 kbyte tx fifo eeprom interface pci interface lan connect interface 86 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.2.1.1 parallel subsystem overview the parallel subsystem is broken down into several functional blocks: a pci bus master interface, a micromachine processing unit and its corresponding microcode rom, and a pci target control/ eeprom/ interface. the parallel subsystem also interfaces to the fifo subsystem, passing data (such as transmit, receive, and configuration data) and command and status parameters between these two blocks. the pci bus master interface provides a complete interface to the pci bus and is compliant with the pci local bus specification, revision 2.3 . the lan controller provides 32 bits of addressing and data, as well as the complete control interface to operate on the pci bus. as a pci target, it follows the pci configuration format which allows all accesses to the lan controller to be automatically mapped into free memory and i/o space upon initialization of a pci system. for processing of transmit and receive frames, the integrated lan controller operates as a master on the pci bus, initiating zero wait-state transfers for accessing these data parameters. the lan controller control/status register block is part of the pci target element. the control/ status register block consists of the following lan controller internal control registers: system control block (scb), port, eeprom control and management data interface (mdi) control. the micromachine is an embedded processing unit contained in the lan controller that enables adaptive technology. the micromachine accesses the lan controller?s microcode rom, working its way through the opcodes (or instructions) contained in the rom to perform its functions. parameters accessed from memory, such as pointers to data buffers, are also used by the micromachine during the processing of transmit or receive frames by the lan controller. a typical micromachine function is to transfer a data buffer pointer field to the lan controller?s dma unit for direct access to the data buffer. the micromachine is divided into two units, receive unit and command unit which includes transmit functions. these two units operate independently and concurrently. control is switched between the two units according to the microcode instruction flow. the independence of the receive and command units in the micromachine allows the lan controller to execute commands and receive incoming frames simultaneously, with no real-time processor intervention. the lan controller contains an interface to an external serial eeprom. the eeprom is used to store relevant information for a lan connection such as node address, as well as board manufacturing and configuration information. both read and write accesses to the eeprom are supported by the lan controller. information on the eeprom interface is detailed in section 5.2.3 . intel ? 82801eb ich5 / 82801er ich5r datasheet 87 functional description 5.2.1.2 fifo subsystem overview the ich5 lan controller fifo subsystem consists of a 3-kb transmit fifo and 3-kb receive fifo. each fifo is unidirectional and independent of the other. the fifo subsystem serves as the interface between the lan controller parallel side and the serial csma/cd unit. it provides a temporary buffer storage area for frames as they are either being received or transmitted by the lan controller, which improves performance: ? transmit frames can be queued within the transmit fifo, allowing back-to-back transmission within the minimum interframe spacing (ifs). ? the storage area in the fifo allows the lan controller to withstand long pci bus latencies without losing incoming data or corrupting outgoing data. ? the ich5 lan controller?s transmit fifo threshold allows the transmit start threshold to be tuned to eliminate underruns while concurrent transmits are being performed. ? the fifo subsection allows extended pci zero wait-state burst accesses to or from the lan controller for both transmit and receive frames since the transfer is to the fifo storage area rather than directly to the serial link. ? transmissions resulting in errors (collision detection or data underrun) are retransmitted directly from the lan controller?s fifo, increasing performance and eliminating the need to re-access this data from the host system. ? incoming runt receive frames (in other words, frames that are less than the legal minimum frame size) can be discarded automatically by the lan controller without transferring this faulty data to the host system. 5.2.1.3 serial csma/cd unit overview the csma/cd unit of the ich5 lan controller allows it to be connected to the 82562et/em/ez/ ex 10/100 mbps ethernet lan connect components. the csma/cd unit performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc. the csma/cd unit can also be placed in a full-duplex mode that allows simultaneous transmission and reception of frames. 88 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.2.2 lan controller pci bus interface as a fast ethernet controller, the role of the ich5 integrated lan controller is to access transmitted data or deposit received data. the lan controller, as a bus master device, initiates memory cycles via the pci bus to fetch or deposit the required data. to perform these actions, the lan controller is controlled and examined by the processor via its control and status structures and registers. some of these control and status structures reside in the lan controller and some reside in system memory. for access to the lan controller?s control/ status registers (csr), the lan controller acts as a slave (in other words, a target device). the lan controller serves as a slave also while the processor accesses the eeprom. 5.2.2.1 bus slave operation the ich5 integrated lan controller serves as a target device in one of the following cases: ? processor accesses to the lan controller system control block (scb) control/status registers (csr) ? processor accesses to the eeprom through its csr ? processor accesses to the lan controller port address via the csr ? processor accesses to the mdi control register in the csr the size of the csr memory space is 4 kbyte in the memory space and 64 bytes in the i/o space. the lan controller treats accesses to these memory spaces differently. control/status register (csr) accesses the integrated lan controller supports zero wait-state single cycle memory or i/o mapped accesses to its csr space. separate bars request 4 kb of memory space and 64 bytes of i/o space to accomplish this. based on its needs, the software driver uses either memory or i/o mapping to access these registers. the lan controller provides four valid kb of csr space that include the following elements: ? system control block (scb) registers ? port register ? eeprom control register ? mdi control register ? flow control registers in the case of accessing the control/status registers, the processor is the initiator and the lan controller is the target. read accesses: the processor, as the initiator, drives address lines ad[31:0], the command and byte enable lines c/be[3:0]# and the control lines irdy# and frame#. as a slave, the lan controller controls the trdy# signal and provides valid data on each data access. the lan controller allows the processor to issue only one read cycle when it accesses the csr, generating a disconnect by asserting the stop# signal. the processor can insert wait-states by deasserting irdy# when it is not ready. intel ? 82801eb ich5 / 82801er ich5r datasheet 89 functional description write accesses: the processor, as the initiator, drives the address lines ad[31:0], the command and byte enable lines c/be[3:0]# and the control lines irdy# and frame#. it also provides the lan controller with valid data on each data access immediately after asserting irdy#. the lan controller controls the trdy# signal and asserts it from the data access. the lan controller allows the processor to issue only one i/o write cycle to the control/status registers, generating a disconnect by asserting the stop# signal. this is true for both memory mapped and i/o mapped accesses. retry premature accesses the lan controller responds with a retry to any configuration cycle accessing the lan controller before the completion of the automatic read of the eeprom. the lan controller may continue to retry any configuration accesses until the eeprom read is complete. the lan controller does not enforce the rule that the retried master must attempt to access the same address again in order to complete any delayed transaction. any master access to the lan controller after the completion of the eeprom read is honored. error handling data parity errors: the lan controller checks for data parity errors while it is the target of the transaction. if an error was detected, the lan controller always sets the detected parity error bit in the pci configuration status register, bit 15. the lan controller also asserts perr#, if the parity error response bit is set (pci configuration command register, bit 6). the lan controller does not attempt to terminate a cycle in which a parity error was detected. this gives the initiator the option of recovery. target-disconnect: the lan controller prematurely terminate a cycle in the following cases: ? after accesses to its csr ? after accesses to the configuration space system error: the lan controller reports parity error during the address phase using the serr# pin. if the serr# enable bit in the pci configuration command register or the parity error response bit are not set, the lan controller only sets the detected parity error bit (pci configuration status register, bit 15). if serr# enable and parity error response bits are both set, the lan controller sets the signaled system error bit (pci configuration status register, bit 14) as well as the detected parity error bit and asserts serr# for one clock. the lan controller, when detecting system error, claims the cycle if it was the target of the transaction and continues the transaction as if the address was correct. note: the lan controller reports a system error for any error during an address phase, whether or not it is involved in the current transaction. 90 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.2.2.2 bus master operation as a pci bus master, the ich5 integrated lan controller initiates memory cycles to fetch data for transmission or deposit received data and for accessing the memory resident control structures. the lan controller performs zero wait-state burst read and write cycles to the host main memory. for bus master cycles, the lan controller is the initiator and the host main memory (or the pci host bridge, depending on the configuration of the system) is the target. the processor provides the lan controller with action commands and pointers to the data buffers that reside in host main memory. the lan controller independently manages these structures and initiates burst memory cycles to transfer data to and from them. the lan controller uses the memory read multiple (mr multiple) command for burst accesses to data buffers and the memory read line (mr line) command for burst accesses to control structures. for all write accesses to the control structure, the lan controller uses the memory write (mw) command. for write accesses to data structure, the lan controller may use either the memory write or memory write and invalidate (mwi) commands. read accesses: the lan controller performs block transfers from host system memory in order to perform frame transmission on the serial link. in this case, the lan controller initiates zero wait-state memory read burst cycles for these accesses. the length of a burst is bounded by the system and the lan controller?s internal fifo. the length of a read burst may also be bounded by the value of the transmit dma maximum byte count in the configure command. the transmit dma maximum byte count value indicates the maximum number of transmit dma pci cycles that will be completed after an lan controller internal arbitration. the lan controller, as the initiator, drives the address lines ad[31:0], the command and byte enable lines c/be[3:0]# and the control lines irdy# and frame#. the lan controller asserts irdy# to support zero wait-state burst cycles. the target signals the lan controller that valid data is ready to be read by asserting the trdy# signal. write accesses: the lan controller performs block transfers to host system memory during frame reception. in this case, the lan controller initiates memory write burst cycles to deposit the data, usually without wait-states. the length of a burst is bounded by the system and the lan controller?s internal fifo threshold. the length of a write burst may also be bounded by the value of the receive dma maximum byte count in the configure command. the receive dma maximum byte count value indicates the maximum number of receive dma pci transfers that will be completed before the lan controller internal arbitration. the lan controller, as the initiator, drives the address lines ad[31:0], the command and byte enable lines c/be[3:0]# and the control lines irdy# and frame#. the lan controller asserts irdy# to support zero wait-state burst cycles. the lan controller also drives valid data on ad[31:0] lines during each data phase (from the first clock and on). the target controls the length and signals completion of a data phase by deassertion and assertion of trdy#. intel ? 82801eb ich5 / 82801er ich5r datasheet 91 functional description cycle completion: the lan controller completes (terminates) its initiated memory burst cycles in the following cases: ? normal completion: all transaction data has been transferred to or from the target device (for example, host main memory). ? backoff: latency timer has expired and the bus grant signal (gnt#) was removed from the lan controller by the arbiter, indicating that the lan controller has been preempted by another bus master. ? transmit or receive dma maximum byte count: the lan controller burst has reached the length specified in the transmit or receive dma maximum byte count field in the configure command block. ? target termination: the target may request to terminate the transaction with a target- disconnect, target-retry, or target-abort. in the first two cases, the lan controller initiates the cycle again. in the case of a target-abort, the lan controller sets the received target-abort bit in the pci configuration status field (pci configuration status register, bit 12) and does not re-initiate the cycle. ? master abort: the target of the transaction has not responded to the address initiated by the lan controller (in other words, devsel# has not been asserted). the lan controller simply deasserts frame# and irdy# as in the case of normal completion. ? error condition: in the event of parity or any other system error detection, the lan controller completes its current initiated transaction. any further action taken by the lan controller depends on the type of error and other conditions. memory write and invalidate the lan controller has four direct memory access (dma) channels. of these four channels, the receive dma is used to deposit the large number of data bytes received from the link into system memory. the receive dma uses both the memory write (mw) and the memory write and invalidate (mwi) commands. to use mwi, the lan controller must guarantee the following: ? minimum transfer of one cache line. ? active byte enable bits (or be[3:0]# are all low) during mwi access. ? the lan controller may cross the cache line boundary only if it intends to transfer the next cache line too. to ensure the above conditions, the lan controller may use the mwi command only under the following conditions: ? the cache line size (cls) written in the cls register during pci configuration is 8 or 16 dwords. ? the accessed address is cache line aligned. ? the lan controller has at least 8 or 16 dwords of data in its receive fifo. ? there are at least 8 or 16 dwords of data space left in the system memory buffer. ? the mwi enable bit in the pci configuration command register, bit 4, should is set to 1b. ? the mwi enable bit in the lan controller configure command should is set to 1b. 92 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description if any one of the above conditions does not hold, the lan controller uses the mw command. if a mwi cycle has started and one of the conditions is no longer valid (for example, the data space in the memory buffer is now less than cls), then the lan controller terminates the mwi cycle at the end of the cache line. the next cycle is either a mw or mwi cycle, depending on the conditions listed above. if the lan controller started a mw cycle and reached a cache line boundary, it either continues or terminates the cycle depending on the terminate write on cache line configuration bit of the lan controller configure command (byte 3, bit 3). if this bit is set, the lan controller terminates the mw cycle and attempts to start a new cycle. the new cycle is a mwi cycle if this bit is set and all of the above listed conditions are met. if the bit is not set, the lan controller continues the mw cycle across the cache line boundary if required. read align the read align feature enhances the lan controller?s performance in cache line oriented systems. in these particular systems, starting a pci transaction on a non-cache line aligned address may cause low performance. to resolve this performance anomaly, the lan controller attempts to terminate transmit dma cycles on a cache line boundary and start the next transaction on a cache line aligned address. this feature is enabled when the read align enable bit is set in the lan controller configure command (byte 3, bit 2). if this bit is set, the lan controller operates as follows: ? when the lan controller is almost out of resources on the transmit dma (that is, the transmit fifo is almost full), it attempts to terminate the read transaction on the nearest cache line boundary when possible. ? when the arbitration counter?s feature is enabled (i.e., the transmit dma maximum byte count value is set in the configure command), the lan controller switches to other pending dmas on cache line boundary only. note: 1. this feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. 2. this feature should be used only when the cls register in pci configuration space is set to 8 or 16. 3. the lan controller reads all control data structures (including receive buffer descriptors) from the first dword (even if it is not required) in order to maintain cache line alignment. error handling data parity errors: as an initiator, the lan controller checks and detects data parity errors that occur during a transaction. if the parity error response bit is set (pci configuration command register, bit 6), the lan controller also asserts perr# and sets the data parity detected bit (pci configuration status register, bit 8). in addition, if the error was detected by the lan controller during read cycles, it sets the detected parity error bit (pci configuration status register, bit 15). intel ? 82801eb ich5 / 82801er ich5r datasheet 93 functional description 5.2.2.3 pci power management enhanced support for the power management standard, pci local bus specification, revision 2.3 , is provided in the ich5 integrated lan controller. the lan controller supports a large set of wake-up packets and the capability to wake the system from a low power state on a link status change. the lan controller enables the host system to be in a sleep state and remain virtually connected to the network. after a power management event or link status change is detected, the lan controller wakes the host system. the sections below describe these events, the lan controller power states, and estimated power consumption at each power state. power states the lan controller contains power management registers for pci, and implements four power states, d0 through d3, which vary from maximum power consumption at d0 to the minimum power consumption at d3. pci transactions are only allowed in the d0 state, except for host accesses to the lan controller?s pci configuration registers. the d1 and d2 power management states enable intermediate power savings while providing the system wake-up capabilities. in the d3 cold state, the lan controller can provide wake-up capabilities. wake-up indications from the lan controller are provided by the power management event (pme#) signal. ? d0 power state the device is fully functional in the d0 power state. in this state, the lan controller receives full power and should be providing full functionality. in the lan controller the d0 state is partitioned into two substates, d0 uninitialized (d0u) and d0 active (d0a). d0u is the lan controller?s initial power state following a pci rst#. while in the d0u state, the lan controller has pci slave functionality to support its initialization by the host and supports wake on lan mode. initialization of the csr, memory, or i/o base address registers in the pci configuration space switches the lan controller from the d0u state to the d0a state. in the d0a state, the lan controller provides its full functionality and consumes its nominal power. in addition, the lan controller supports wake on link status change (see section 5.2.2.5 ). while it is active, the lan controller requires a nominal pci clock signal (in other words, a clock frequency greater than 16 mhz) for proper operation. the lan controller supports a dynamic standby mode. in this mode, the lan controller is able to save almost as much power as it does in the static power-down states. the transition to or from standby is done dynamically by the lan controller and is transparent to the software. ? d1 power state in order for a device to meet the d1 power state requirements, as specified in the advanced configuration and power interface, version 2.0b specification , it must not allow bus transmission or interrupts; however, bus reception is allowed. therefore, device context may be lost and the lan controller does not initiate any pci activity. in this state, the lan controller responds only to pci accesses to its configuration space and system wake-up events. the lan controller retains link integrity and monitors the link for any wake-up events (e.g., wake-up packets or link status change). following a wake-up event, the lan controller asserts the pme# signal. 94 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description ? d2 power state the acpi d2 power state is similar in functionality to the d1 power state. in addition to d1 functionality, the lan controller can provide a lower power mode with wake-on-link status change capability. the lan controller may enter this mode if the link is down while the lan controller is in the d2 state. in this state, the lan controller monitors the link for a transition from an invalid to a valid link. the sub-10 ma state due to an invalid link can be enabled or disabled by a configuration bit in the power management driver register (pmdr). the lan controller will consume in d2 <10 ma, regardless of the link status. it is the lan connect component that consumes much less power during link down; hence, the lan controller in this state can consume <10 ma. ? d3 power state in the d3 power state, the lan controller has the same capabilities and consumes the same amount of power as it does in the d2 state. however, it enables the pci system to be in the b3 state. if the pci system is in the b3 state (in other words, no pci power is present), the lan controller provides wake-up capabilities. if pme is disabled, the lan controller does not provide wake-up capability or maintain link integrity. in this mode the lan controller consumes its minimal power. the lan controller enables a system to be in a sub-5 watt state (low-power state) and still be virtually connected. more specifically, the lan controller supports full wake-up capabilities while it is in the d3 cold state. the lan controller is in the ich5 resume well, which enables it to provide wake-up functionality while the pci power is off. 5.2.2.4 pci reset signal the pcirst# signal may be activated in one of the following cases: ? during s3?s5 states ? due to a cf9h reset if pme is enabled (in the pci power management registers), pcirst# assertion does not affect any pme related circuits (in other words, pci power management registers and the wake-up packet would not be affected). while pcirst# is active, the lan controller ignores other pci signals. the configuration of the lan controller registers associated with acpi wake events is not affected by pcirst#. the integrated lan controller uses the pcirst# or the pwrok signal as an indication to ignore the pci interface. following the deassertion of pcirst#, the lan controller pci configuration space, mac configuration, and memory structure are initialized while preserving the pme# signal and its context. intel ? 82801eb ich5 / 82801er ich5r datasheet 95 functional description 5.2.2.5 wake-up events there are two types of wake-up events: ?interesting? packets and link status change. these two events are detailed below. note: if the wake on lan bit in the eeprom is not set, wake-up events are supported only if the pme enable bit in the power management control/status register (pmcsr) is set. however, if the wake on lan bit in the eeprom is set, and wake on magic packet* or wake on link status change are enabled, the power management enable bit is ignored with respect to these events. in the latter case, pme# would be asserted by these events. ?interesting? packet event in the power-down state, the lan controller is capable of recognizing ?interesting? packets. the lan controller supports pre-defined and programmable packets that can be defined as any of the following: ? arp packets (with multiple ip addresses) ? direct packets (with or without type qualification) ? magic packet ? neighbor discovery multicast address packet (?arp? in ipv6 environment) ? netbios over tcp/ip (nbt) query packet (under ipv4) ? internetwork package exchange* (ipx) diagnostic packet this allows the lan controller to handle various packet types. in general, the lan controller supports programmable filtering of any packet in the first 128 bytes. when the lan controller is in one of the low power states, it searches for a predefined pattern in the first 128 bytes of the incoming packets. the only exception is the magic packet, which is scanned for the entire frame. the lan controller classifies the incoming packets as one of the following categories: ? no match: the lan controller discards the packet and continues to process the incoming packets. ? tco packet: the lan controller implements perfect filtering of tco packets. after a tco packet is processed, the lan controller is ready for the next incoming packet. tco packets are treated as any other wake-up packet and may assert the pme# signal if configured to do so. ? wake-up packet: the lan controller is capable of recognizing and storing the first 128 bytes of a wake-up packet. if a wake-up packet is larger than 128 bytes, its tail is discarded by the lan controller. after the system is fully powered-up, software has the ability to determine the cause of the wake-up event via the pmdr and dump the stored data to the host memory. magic packets are an exception. the magic packets may cause a power management event and set an indication bit in the pmdr; however, it is not stored by the lan controller for use by the system when it is woken up. link status change event the lan controller link status indication circuit is capable of issuing a pme on a link status change from a valid link to an invalid link condition or vice versa. the lan controller reports a pme link status event in all power states. if the wake on lan bit in the eeprom is not set, the pme# signal is gated by the pme enable bit in the pmcsr and the csma configure command. 96 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.2.2.6 wake on lan* (preboot wake-up) the lan controller enters wake on lan mode after reset if the wake on lan bit in the eeprom is set. at this point, the lan controller is in the d0u state. when the lan controller is in wake on lan mode: ? the lan controller scans incoming packets for a magic packet and asserts the pme# signal for 52 ms when a 1 is detected in wake on lan mode. ? the activity led changes its functionality to indicates that the received frame passed individual address (ia) filtering or broadcast filtering. ? the pci configuration registers are accessible to the host. the lan controller switches from wake on lan mode to the d0a power state following a setup of the memory or i/o base address registers in the pci configuration space. 5.2.3 serial eeprom interface the serial eeprom stores configuration data for the ich5 integrated lan controller and is a serial in/serial out device. the lan controller supports a 64-register or 256-register size eeprom and automatically detects the eeprom?s size. the eeprom should operate at a frequency of at least 1 mhz. all accesses, either read or write, are preceded by a command instruction to the device. the address field is six bits for a 64-register eeprom or eight bits for a 256-register eeprom. the end of the address field is indicated by a dummy 0 bit from the eeprom, which indicates the entire address field has been transferred to the device. an eeprom read instruction waveform is shown in figure 9 . the lan controller performs an automatic read of seven words (0h, 1h, 2h, ah, bh, ch, and dh) of the eeprom after the deassertion of reset. figure 9. 64-word eeprom read instruction waveform a 1 a 0 ee_cs ee_shclkk ee_din ee_dout a 5 a 4 a 2 d 15 d 0 read op code a 3 a 1 a 0 intel ? 82801eb ich5 / 82801er ich5r datasheet 97 functional description 5.2.4 csma/cd unit the ich5 integrated lan controller csma/cd unit implements both the ieee 802.3 ethernet 10 mbps and ieee 802.3u fast ethernet 100 mbps standards. it performs all the csma/cd protocol functions (e.g., transmission, reception, collision handling, etc.). the lan controller csma/cd unit interfaces to the 82562et/em/ez/ex 10/100 mbps ethernet through the ich5?s lan connect interface signals. 5.2.4.1 full duplex when operating in full-duplex mode, the lan controller can transmit and receive frames simultaneously. transmission starts regardless of the state of the internal receive path. reception starts when the platform lan connect component detects a valid frame on its receive differential pair. the ich5 integrated lan controller also supports the ieee 802.3x flow control standard, when in full-duplex mode. the lan controller operates in either half-duplex mode or full-duplex mode. for proper operation, both the lan controller csma/cd module and the discrete platform lan connect component must be set to the same duplex mode. the csma duplex mode is set by the lan controller configure command or forced by automatically tracking the mode in the platform lan connect component. following reset, the csma defaults to automatically track the platform lan connect component duplex mode. the selection of duplex operation (full or half) and flow control is done in two levels: mac and lan connect. 5.2.4.2 flow control the lan controller supports ieee 802.3x frame-based flow control frames only in both full duplex and half duplex switched environments. the lan controller flow control feature is not intended to be used in shared media environments. flow control is optional in full-duplex mode and is selected through software configuration. there are three modes of flow control that can be selected: frame-based transmit flow control, frame- based receive flow control, and none. 5.2.4.3 address filtering modifications the lan controller can be configured to ignore 1 bit when checking for its individual address (ia) on incoming receive frames. the address bit, known as the upper/lower (u/l) bit, is the second least significant bit of the first byte of the ia. this bit may be used, in some cases, as a priority indication bit. when configured to do so, the lan controller passes any frame that matches all other 47 address bits of its ia, regardless of the u/l bit value. this configuration only affects the lan controller specific ia and not multicast, multi-ia or broadcast address filtering. the lan controller does not attribute any priority to frames with this bit set, it simply passes them to memory regardless of this bit. 98 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.2.4.4 vlan support the lan controller supports the ieee 802.1 standard vlan. all vlan flows will be implemented by software. the lan controller supports the reception of long frames, specifically frames longer than 1518 bytes, including the crc, if software sets the long receive ok bit in the configuration command. otherwise, ?long? frames are discarded. 5.2.5 media management interface the management interface allows the processor to control the platform lan connect component via a control register in the ich5 integrated lan controller. this allows the software driver to place the platform lan connect in specific modes (e.g., full duplex, loopback, power down, etc.) without the need for specific hardware pins to select the desired mode. this structure allows the lan controller to query the platform lan connect component for status of the link. this register is the mdi control register and resides at offset 10h in the lan controller csr. the mdi registers reside within the platform lan connect component, and are described in detail in the platform lan connect component?s datasheet. the processor writes commands to this register and the lan controller reads or writes the control/status parameters to the platform lan connect component through the mdi register. 5.2.6 tco functionality the ich5 integrated lan controller supports management communication to reduce total cost of ownership (tco). the smbus is used as an interface between the asf controller and the integrated tco host controller. there are two different types of tco operation that are supported (only one supported at a time), they are 1) integrated asf control or 2) external tco controller support. the smlink is a dedicated bus between the lan controller and the integrated asf controller (if enabled) or an external management controller. an eeprom of 256 words is required to support the heartbeat command. 5.2.6.1 advanced tco mode the advanced tco functionalities through the smlink are listed in table 32 . note: for a complete description on various commands, see the total cost of ownership (tco) system management bus interface application note (ap-430) . table 32. advanced tco functionality power state tco controller functionality d0 nominal transmit set receive tco packets receive tco packets read ich5 status (pm & link state) force tco mode dx (x>0) d0 functionality plus: read phy registers force tco mode dx functionality plus: config commands read/write phy registers intel ? 82801eb ich5 / 82801er ich5r datasheet 99 functional description transmit command during normal operation to serve a transmit request from the tco controller, the ich5 lan controller first completes the current transmit dma, sets the tco request bit in the pmdr register (see section 7.2 ), and then responds to the tco controller?s transmit request. following the completion of the tco transmit dma, the lan controller increments the transmit tco statistic counter (described in section 7.2.14 ). following the completion of the transmit operation, the ich5 increments the nominal transmit statistic counters, clears the tco request bit in the pmdr register, and resumes its normal transmit flow. the receive flow is not affected during this entire period of time. receive tco the ich5 lan controller supports receive flow towards the tco controller. the ich5 can transfer only tco packets, or all packets that passed mac address filtering according to its configuration and mode of operation as detailed below. while configured to transfer only tco packets, it supports ethernet type ii packets with optional vlan tagging. force tco mode: while the ich5 is in the force tco mode, it may receive packets (tco or all) directly from the tco controller. receiving tco packets and filtering level is controlled by the set receive enable command from the tco controller. following a reception of a tco packet, the ich5 increments its nominal receive statistic counters as well as the receive tco counter. dx>0 power state: while the ich5 is in a powerdown state, it may receive tco packets or all directly to the tco controller. receiving tco packets is enabled by the set receive enable command from the tco controller. although tco packet might match one of the other wake up filters, once it is transferred to the tco controller, no further matching is searched for and pme is not issued. while receive to tco is not enabled, a tco packet may cause a pme if configured to do so (setting tco to 1 in the filter type). d0 power state: at d0 power state, the ich5 may transfer tco packets to the tco controller. at this state, tco packets are posted first to the host memory, then read by the ich5, and then posted back to the tco controller. after the packet is posted to tco, the receive memory structure (that is occupied by the tco packet) is reclaimed. other than providing the necessary receive resources, there is no required device driver intervention with this process. eventually, the ich5 increments the receive tco static counter, clears the tco request bit, and resumes normal control. read ich5 status (pm and link state) the tco controller is capable of reading the ich5 power state and link status. following a status change, the ich5 asserts linkalert# and then the tco can read its new power state. set force tco mode the tco controller put the ich5 into the force tco mode. the ich5 is set back to the nominal operation following a pcirst#. following the transition from nominal mode to a tco mode, the ich5 aborts transmission and reception and loses its memory structures. the tco may configure the ich5 before it starts transmission and reception if required. note: the force tco is a destructive command. it causes the ich5 to lose its memory structures, and during the force tco mode the ich5 ignores any pci accesses. therefore, it is highly recommended to use this command by the tco controller at system emergency only. 100 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.3 alert standard format (asf) the asf controller collects information from various components in the system (including the processor, chipset, bios, and sensors on the motherboard) and sends this information via the lan controller to a remote server running a management console. the controller also accepts commands back from the management console and drives the execution of those commands on the local system. the asf controller is responsible for monitoring sensor devices and sending packets through the lan controller smbus (system management bus) interface. these asf controller alerting capabilities include system health information such as bios messages, post alerts, os failure notifications, and heartbeat signals to indicate the system is accessible to the server. also included are environmental notification (e.g., thermal, voltage and fan alerts) that send proactive warnings that something is wrong with the hardware. the packets are used as alert (s.o.s.) packets or as ?heartbeat? status packets. in addition, asset security is provided by messages (e.g., ?cover tamper? and ?cpu missing?) that notify of potential system break-ins and processor or memory theft. the asf controller is also responsible for receiving and responding to rmcp (remote management and control protocol) packets. rmcp packets are used to perform various system apm commands (e.g., reset, power-up, power-cycle, and power-down). rmcp can also be used to ping the system to ensure that it is on the network and running correctly and for capability reporting. a major advantage of asf is that it provides these services during the time that software is unable to do so (e.g., during a low-power state, during boot-up, or during an os hang) but are not precluded from running in the working state. the asf controller communicates to the system and the lan controller logic through the smbus connections. the first smbus connects to the host smbus controller (within the ich5) and any smbus platform sensors. the smbus host is accessible by the system software, including software running on the os and the bios. note that the host side bus may require isolation if there are non- auxiliary devices that can pull down the bus when un-powered. the second smbus connects to the lan controller. this second smbus is used to provide a transmit/receive network interface. the stimulus for causing the asf controller to send packets can be either internal or external to the asf controller. external stimuli are link status changes or polling data from smbus sensor devices; internal events come from, among others, a set of timers or an event caused by software. the asf controller provides three local configuration protocols via the host smbus. the first one is the smbus arp interface that is used to identify the smbus device and allow dynamic smbus address assignment. the second protocol is the asf controller command set that allows software to manage an asf controller compliant interface for retrieving info, sending alerts, and controlling timers. ich5 provides an input and an output eeprom interface. the eeprom contains the lan controller configuration and the asf controller configuration/packet information. intel ? 82801eb ich5 / 82801er ich5r datasheet 101 functional description 5.3.1 asf management solution features/capabilities ? alerting ? transmit sos packets from s0?s5 states ? system health heartbeats ? sos hardware events - system boot failure (watchdog expires on boot) - lan link loss - entity presence (on asf power-up) - smbus hung - maximum of eight legacy sensors - maximum of 128 asf sensor events ? watchdog timer for os lockup/system hang/failure to boot ? general push support for bios (post messages) ? remote control ? presence ping response ? configurable boot options ? capabilities reporting ? auto-arp support ? system remote control - power-down - power-up - power cycle - system reset ? state-based security ? conditional action on watchdog expire ? asf compliance ? compliant with the alert standard format (asf) specification, version 1.03 - pet compliant packets - rmcp - legacy sensor polling - asf sensor polling - remote control sensor support ? advanced features / miscellaneous ? smbus 2.0 compliant ? optional reset extension logic (for use with a power-on reset) 102 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.3.2 asf hardware support asf requires additional hardware to make a complete solution. note: if an asf compatible device is externally connected and properly configured, the internal ich5 asf controller will be disabled. the external asf device will have access to the smbus controller. 5.3.2.1 82562em/ex the 82562em/ex ethernet lan controller is necessary. this lan controller provides the means of transmitting and receiving data on the network, as well as adding the ethernet crc to the data from the asf. 5.3.2.2 eeprom (256x16, 1 mhz) to support the ich5 asf solution, a larger, 256x16 1 mhz, eeprom is necessary to configure defaults on reset and on hard power losses (software un-initiated). the asf controller shares this eeprom with the lan controller and provides a pass through interface to achieve this. the asf controller expects to have exclusive access to words 40h through f7h. the lan controller can use the other eeprom words. the asf controller will default to safe defaults if the eeprom is not present or not configured properly (both cause an invalid crc). 5.3.2.3 legacy sensor smbus devices the asf controller is capable of monitoring up to eight sensor devices on the main smbus. these sensors are expected to be compliant with the legacy sensor characteristics defined in the alert standard format (asf) specification, version 1.03. 5.3.2.4 remote control smbus devices the asf controller is capable of causing remote control actions to remote control devices via smbus. these remote control actions include power-up, power-down, power-cycle, and reset. the asf controller supports devices that conform to the alert standard format (asf) specification, version 1.03. , remote control devices. 5.3.2.5 asf sensor smbus devices the asf controller is capable of monitoring up to 128 asf sensor devices on the main smbus. however, asf is restricted by the number of total events which may reduce the number of smbus devices supported. the maximum number of events supported by asf is 128. the asf sensors are expected to operate as defined in the alert standard format (asf) specification, version 1.03 . 5.3.3 asf software support asf requires software support to make a complete solution. the following software is used as part of the complete solution. ? asf configuration driver / application ? network driver ? bios support for smbios, smbus arp, acpi ? sensor configuration driver / application note: contact your intel field representative for the client asf software development kit (sdk) that includes additional documentation and a copy of the client asf software drivers. intel also provides an asf console sdk to add asf support to a management console. intel ? 82801eb ich5 / 82801er ich5r datasheet 103 functional description 5.4 lpc bridge (w/ system and management functions) (d31:f0) the lpc bridge function of the ich5 resides in pci device 31:function 0. in addition to the lpc bridge function, d31:f0 contains other functional units including dma, interrupt controllers, timers, power management, system management, gpio, and rtc. in this chapter, registers and functions associated with other functional units (power management, gpio, usb, ide, etc.) are described in their respective sections. 5.4.1 lpc interface the ich5 implements an lpc interface as described in the low pin count interface specification, revision 1.1 . the lpc interface to the ich5 is shown in figure 10 . note that the ich5 implements all of the signals that are shown as optional, but peripherals are not required to do so. figure 10. lpc interface diagram ich super i/o pci bus pci clk pci rst# lad[3:0] pci serirq lpcpd# (optional) pci pme# lsmi# (optional) lframe# ldrq# (optional) gpi sus_stat# 104 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.4.1.1 lpc cycle types the ich5 implements all of the cycle types described in the low pin count interface specification, revision 1.0 . table 33 shows the cycle types supported by the ich5. notes: 1. for memory cycles below 16 mb that do not target enabled flash bios ranges, the ich5performs standard lpc memory cycles. it only attempts 8-bit transfers. if the cycle appears on pci as a 16-bit transfer, it appears as two consecutive 8-bit transfers on lpc. likewise, if the cycle appears as a 32-bit transfer on pci, it appears as four consecutive 8-bit transfers on lpc. if the cycle is not claimed by any peripheral, it is subsequently aborted, and the ich5 returns a value of all 1s to the processor. this is done to maintain compatibility with isa memory cycles where pull-up resistors would keep the bus high if no device responds. 2. bus master read or write cycles must be naturally aligned. for example, a 1-byte transfer can be to any address. however, the 2-byte transfer must be word aligned (i.e., with an address where a0=0). a dword transfer must be dword aligned (i.e., with an address where a1and a0 are both 0). 5.4.1.2 start field definition note: all other encodings are reserved. table 33. lpc cycle types supported cycle type comment memory read single: 1 byte only memory write single: 1 byte only i/o read 1 byte only. intel ? ich5 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. see note 1 below. i/o write 1 byte only. ich5 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. see note 1 below. dma read can be 1, or 2 bytes dma write can be 1, or 2 bytes bus master read can be 1, 2, or 4 bytes. (see note 2 below) bus master write can be 1, 2, or 4 bytes. (see note 2 below) table 34. start field bit definitions bits[3:0] encoding definition 0000 start of cycle for a generic target 0010 grant for bus master 0 0011 grant for bus master 1 1111 stop/abort: end of a cycle for a target. intel ? 82801eb ich5 / 82801er ich5r datasheet 105 functional description 5.4.1.3 cycle type / direction (cyctype + dir) the ich5 always drives bit 0 of this field to 0. peripherals running bus master cycles must also drive bit 0 to 0. table 35 shows the valid bit encodings. 5.4.1.4 size bits[3:2] are reserved. the ich5 always drives them to 00. peripherals running bus master cycles are also supposed to drive 00 for bits 3:2; however, the ich5 ignores those bits. bits[1:0] are encoded as listed in table 36 . table 35. cycle type bit definitions bits[3:2] bit1 definition 00 0 i/o read 00 1 i/o write 01 0 memory read 01 1 memory write 10 0 dma read 10 1 dma write 11 x reserved. if a peripheral performing a bus master cycle generates this value, the intel ? ich5 aborts the cycle. table 36. transfer size bit definition bits[1:0] size 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) 10 reserved. the intel ? ich5 never drives this combination. if a peripheral running a bus master cycle drives this combination, the ich5 may abort the transfer. 11 32-bit transfer (4 bytes) 106 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.4.1.5 sync valid values for the sync field are shown in table 37 . note: all other combinations are reserved. 5.4.1.6 sync time-out there are several error cases that can occur on the lpc interface. table 38 indicates the failing case and the ich5 response. there may be other peripheral failure conditions; however, these are not handled by the ich5. 5.4.1.7 sync error indication the sync protocol allows the peripheral to report an error via the lad[3:0] = 1010b encoding. the intent of this encoding is to give peripherals a method of communicating errors to aid higher layers with more robust error recovery. if the ich5 was reading data from a peripheral, data will still be transferred in the next two nibbles. this data may be invalid, but it must be transferred by the peripheral. if the ich5 was writing data to the peripheral, the data had already been transferred. table 37. sync bit definition bits[3:0] indication 0000 ready: sync achieved with no error. for dma transfers, this also indicates dma request deassertion and no more transfers desired for that channel. 0101 short wait: part indicating wait-states. for bus master cycles, the intel ? ich5 does not use this encoding. instead, the ich5 uses the long wait encoding (see next encoding below). 0110 long wait: part indicating wait-states, and many wait-states will be added. this encoding driven by the ich5 for bus master cycles, rather than the short wait (0101). 1001 ready more (used only by peripheral for dma cycle): sync achieved with no error and more dma transfers desired to continue after this transfer. this value is valid only on dma transfers and is not allowed for any other type of cycle. 1010 error: sync achieved with error. this is generally used to replace the serr# or iochk# signal on the pci/isa bus. it indicates that the data is to be transferred, but there is a serious error in this transfer. for dma transfers, this not only indicates an error, but also indicates dma request deassertion and no more transfers desired for that channel. table 38. intel ? ich5 response to sync failures possible sync failure intel ? ich5 response intel ? ich5 starts a memory, i/o, or dma cycle, but no device drives a valid sync after 4 consecutive clocks. this could occur if the processor tries to access an i/o location to which no device is mapped. ich5 aborts the cycle after the fourth clock. ich5 drives a memory, i/o, or dma cycle, and a peripheral drives more than 8 consecutive valid sync to insert wait-states using the short (0101b) encoding for sync. this could occur if the peripheral is not operating properly. continues waiting ich5 starts a memory, i/o, or dma cycle, and a peripheral drives an invalid sync pattern. this could occur if the peripheral is not operating properly or if there is excessive noise on the lpc i/f. ich5 aborts the cycle when the invalid sync is recognized. intel ? 82801eb ich5 / 82801er ich5r datasheet 107 functional description in the case of multiple byte cycles (e.g., for memory and dma cycles) an error sync terminates the cycle. therefore, if the ich5 is transferring 4 bytes from a device, if the device returns the error sync in the first byte, the other three bytes will not be transferred. upon recognizing the sync field indicating an error, the ich5 treats this the same as iochk# going active on the isa bus. 5.4.1.8 lframe# usage start of cycle for memory, i/o, and dma cycles, the ich5 asserts lframe# for one clock at the beginning of the cycle ( figure 11 ). during that clock, the ich5 drives lad[3:0] with the proper start field. abort mechanism when performing an abort, the ich5 drives lframe# active for four, consecutive clocks. on the fourth clock, it drives lad[3:0] to 1111b. the ich5 performs an abort for the following cases (possible failure cases): ? ich5 starts a memory, i/o, or dma cycle, but no device drives a valid sync after four consecutive clocks. ? ich5 starts a memory, i/o, or dma cycle, and the peripheral drives an invalid sync pattern. ? a peripheral drives an illegal address when performing bus master cycles. ? a peripheral drives an invalid value. figure 11. typical timing for lframe# lframe# start lclk lad[3:0] cyctype addr start dir & size tar sync data tar 1 - 8 clocks 2 clocks 1 - n clocks 2 clocks 2 clocks 1 clock 1 clock figure 12. abort mechanism lframe# start lclk lad[3:0] cyctype addr dir & size tar sync peripheral must stop driving too many syncs causes timeout chipset will drive high 108 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.4.1.9 i/o cycles for i/o cycles targeting registers specified in the ich5?s decode ranges, the ich5 performs i/o cycles as defined in the low pin count interface specification, revision 1.1 . these are 8-bit transfers. if the processor attempts a 16-bit or 32-bit transfer, the ich5 breaks the cycle up into multiple 8-bit transfers to consecutive i/o addresses. note: if the cycle is not claimed by any peripheral (and subsequently aborted), the ich5 returns a value of all 1s (ffh) to the processor. this is to maintain compatibility with isa i/o cycles where pull-up resistors would keep the bus high if no device responds. 5.4.1.10 bus master cycles the ich5 supports bus master cycles and requests (using ldrq#) as defined in the low pin count interface specification, revision 1.1 . the ich5 has two ldrq# inputs, and thus supports two separate bus master devices. it uses the associated start fields for bus master 0 (0010b) or bus master 1 (0011b). note: the ich5 does not support lpc bus masters performing i/o cycles. lpc bus masters should only perform memory read or memory write cycles. 5.4.1.11 lpc power management lpcpd# protocol same timings as for sus_stat#. upon driving sus_stat# low, lpc peripherals drive ldrq# low or tri-state it. ich5 shuts off the ldrq# input buffers. after driving sus_stat# active, the ich5 drives lframe# low, and tri-states (or drive low) lad[3:0]. note: the low pin count interface specification, revision 1.1 defines the lpcpd# protocol where there is at least 30 s from lpcpd# assertion to lrst# assertion. this specification explicitly states that this protocol only applies to entry/exit of low power states which does not include asynchronous reset events. the ich5 asserts both sus_stat# (connects to lpcpd#) and pcirst# (connects to lrst#) at the same time when the core logic is reset (via cf9h, pwrok, or sys_reset#, etc.). this is not inconsistent with the lpc lpcpd# protocol. 5.4.1.12 configuration and intel ? ich5 implications lpc i/f decoders to allow the i/o cycles and memory mapped cycles to go to the lpc interface, the ich5 includes several decoders. during configuration, the ich5 must be programmed with the same decode ranges as the peripheral. the decoders are programmed via the device 31:function 0 configuration space. note: the ich5 cannot accept pci write cycles from pci-to-pci bridges or devices with similar characteristics (specifically those with a ?retry read? feature which is enabled) to an lpc device if there is an outstanding lpc read cycle towards the same pci device or bridge. these cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures. bus master device mapping and start fields bus masters must have a unique start field. in the case of the ich5 that supports 2 lpc bus masters, it drives 0010 for the start field for grants to bus master #0 (requested via ldrq0#) and 0011 for grants to bus master #1 (requested via ldrq1#.). thus, no registers are needed to configure the start fields for a particular bus master. intel ? 82801eb ich5 / 82801er ich5r datasheet 109 functional description 5.5 dma operation (d31:f0) the ich5 supports two types of dma: lpc, and pc/pci. dma via lpc is similar to isa dma. lpc dma and pc/pci dma use the ich5?s dma controller. the dma controller has registers that are fixed in the lower 64 kb of i/o space. the dma controller is configured using registers in the pci configuration space. these registers allow configuration of individual channels for use by lpc or pc/pci dma. the dma circuitry incorporates the functionality of two 82c37 dma controllers with seven independently programmable channels ( figure 13 ). dma controller 1 (dma-1) corresponds to dma channels 0?3 and dma controller 2 (dma-2) corresponds to channels 5?7. dma channel 4 is used to cascade the two controllers and defaults to cascade mode in the dma channel mode (dcm) register. channel 4 is not available for any other purpose. in addition to accepting requests from dma slaves, the dma controller also responds to requests that software initiates. software may initiate a dma service request by setting any bit in the dma channel request register to a 1. each dma channel is hardwired to the compatible settings for dma device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. ich5 provides 24-bit addressing in compliance with the isa-compatible specification. each channel includes a 16-bit isa-compatible current register which holds the 16 least-significant bits of the 24-bit address, an isa-compatible page register which contains the eight next most significant bits of address. the dma controller also features refresh address generation, and autoinitialization following a dma termination. figure 13. intel ? ich5 dma controller channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 dma-1 dma-2 110 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.5.1 channel priority for priority resolution, the dma consists of two logical channel groups: channels 0?3 and channels 4?7. each group may be in either fixed or rotate mode, as determined by the dma command register. dma i/o slaves normally assert their dreq line to arbitrate for dma service. however, a software request for dma service can be presented through each channel's dma request register. a software request is subject to the same prioritization as any hardware request. see the detailed register description for request register programming information in the section 9.2 . 5.5.1.1 fixed priority the initial fixed priority structure is as follows: the fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. in this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. channels [3:0] of dma-1 assume the priority position of channel 4 in dma-2, thus taking priority over channels 5, 6, and 7. 5.5.1.2 rotating priority rotation allows for "fairness" in priority resolution. the priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0?3, 5?7). channels 0?3 rotate as a group of 4. they are always placed between channel 5 and channel 7 in the priority list. channel 5?7 rotate as part of a group of 4. that is, channels (5?7) form the first three positions in the rotation, while channel group (0?3) comprises the fourth position in the arbitration. 5.5.2 address compatibility mode when the dma is operating, the addresses do not increment or decrement through the high and low page registers. therefore, if a 24-bit address is 01ffffh and increments, the next address is 010000h, not 020000h. similarly, if a 24-bit address is 020000h and decrements, the next address is 02ffffh, not 01ffffh. however, when the dma is operating in 16-bit mode, the addresses still do not increment or decrement through the high and low page registers but the page boundary is now 128 k. therefore, if a 24-bit address is 01fffeh and increments, the next address is 000000h, not 0100000h. similarly, if a 24-bit address is 020000h and decrements, the next address is 03fffeh, not 02fffeh. this is compatible with the 82c37 and page register implementation used in the pc-at. this mode is set after cpurst is valid. high priority low priority 0, 1, 2, 3 5, 6, 7 intel ? 82801eb ich5 / 82801er ich5r datasheet 111 functional description 5.5.3 summary of dma transfer sizes table 39 lists each of the dma device transfer sizes. the column labeled ?current byte/word count register? indicates that the register contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. the column labeled ?current address increment/ decrement? indicates the number added to or taken from the current address register after each dma transfer cycle. the dma channel mode register determines if the current address register will be incremented or decremented. 5.5.3.1 address shifting when programmed for 16-bit i/o count by words the ich5 maintains compatibility with the implementation of the dma in the pc at that used the 82c37. the dma shifts the addresses for transfers to/from a 16-bit device count-by-words. note that the least significant bit of the low page register is dropped in 16-bit shifted mode. when programming the current address register (when the dma channel is in this mode), the current address must be programmed to an even address with the address value shifted right by one bit. the address shifting is shown in table 40 . note: the least significant bit of the page register is dropped in 16-bit shifted mode. 5.5.4 autoinitialize by programming a bit in the dma channel mode register, a channel may be set up as an autoinitialize channel. when a channel undergoes autoinitialization, the original values of the current page, current address and current byte/word count registers are automatically restored from the base page, address, and byte/word count registers of that channel following tc. the base registers are loaded simultaneously with the current registers by the microprocessor when the dma channel is programmed and remain unchanged throughout the dma service. the mask bit is not set when the channel is in autoinitialize. following autoinitialize, the channel is ready to perform another dma service, without processor intervention, as soon as a valid dreq is detected. table 39. dma transfer size dma device date size and word count current byte/word count register current address increment/decrement 8-bit i/o, count by bytes bytes 1 16-bit i/o, count by words (address shifted) words 1 table 40. address shifting in 16-bit i/o dma transfers output address 8-bit i/o programmed address (ch 0?3) 16-bit i/o programmed address (ch 5?7) (shifted) a0 a[16:1] a[23:17] a0 a[16:1] a[23:17] 0 a[15:0] a[23:17] 112 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.5.5 software commands there are three additional special software commands that the dma controller can execute. the three software commands are: ? clear byte pointer flip-flop ? master clear ? clear mask register they do not depend on any specific bit pattern on the data bus. 5.5.5.1 clear byte pointer flip-flop this command is executed prior to writing or reading new address or word count information to/ from the dma controller. this initializes the flip-flop to a known state so that subsequent accesses to register contents by the microprocessor will address upper and lower bytes in the correct sequence. when the host processor is reading or writing dma registers, two byte pointer flip-flops are used; one for channels 0?3 and one for channels 4?7. both of these act independently. there are separate software commands for clearing each of them (0ch for channels 0?3, 0d8h for channels 4?7). 5.5.5.2 dma master clear this software instruction has the same effect as the hardware reset. the command, status, request, and internal first/last flip-flop registers are cleared and the mask register is set. the dma controller enters the idle cycle. there are two independent master clear commands; 0dh that acts on channels 0?3, and 0dah that acts on channels 4?7. 5.5.5.3 clear mask register this command clears the mask bits of all four channels, enabling them to accept dma requests. i/o port 00eh is used for channels 0?3 and i/o port 0dch is used for channels 4?7. intel ? 82801eb ich5 / 82801er ich5r datasheet 113 functional description 5.6 pci dma ich5 provides support for the pc/pci dma protocol. pc/pci dma uses dedicated request and grant signals to permit pci devices to request transfers associated with specific dma channels. upon receiving a request and getting control of the pci bus, ich5 performs a two-cycle transfer. for example, if data is to be moved from the peripheral to main memory, ich5 first reads data from the peripheral and then writes it to main memory. the location in main memory is the current address registers in the 8237. ich5 supports up to two pc/pci req/gnt pairs, req[a:b]# and gnt[a:b]#. a 16-bit register is included in the ich5 function 0 configuration space at offset 90h. it is divided into seven 2-bit fields that are used to configure the seven dma channels. each dma channel can be configured to one of two options: ? lpc dma ? pc/pci style dma using the req/gnt signals it is not possible for a particular dma channel to be configured for more than one style of dma; however, the seven channels can be programmed independently. for example, channel 3 could be set up for pc/pci and channel 5 set up for lpc dma. the ich5 req[a:b]# and gnt[a:b]# can be configured for support of a pc/pci dma expansion agent. the pci dma expansion agent can then provide dma service or isa bus master service using the ich5 dma controller. the req#/gnt# pair must follow the pc/pci serial protocol described below. 5.6.1 pci dma expansion protocol the pci expansion agent must support the pci expansion channel passing protocol defined in figure 14 for both the req# and gnt# pins. the requesting device must encode the channel request information as shown above, where ch0?ch7 are one clock active high states representing dma channel requests 0?7. ich5 encodes the granted channel on the gnt# line as shown above, where the bits have the same meaning as shown in figure 14 . for example, the sequence [start, bit 0, bit 1, bit 2=0,1,0,0] grants dma channel 1 to the requesting device, and the sequence [start, bit 0, bit 1, bit 2=0,0,1,1] grants dma channel 6 to the requesting device. figure 14. dma serial channel passing protocol pciclk start ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 bit0 bit1 bit2 start req# gnt# 114 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description all pci dma expansion agents must use the channel passing protocol described above. they must also work as follows: ? if a pci dma expansion agent has more than one request active, it must resend the request serial protocol after one of the requests has been granted the bus and it has completed its transfer. the expansion device should drive its req# inactive for two clocks and then transmit the serial channel passing protocol again, even if there are no new requests from the pci expansion agent to ich5. for example: if a pci expansion agent had active requests for dma channel 1 and channel 5, it would pass this information to ich5 through the expansion channel passing protocol. if after receiving gnt# (assume for ch5) and having the device finish its transfer (device stops driving request to pci expansion agent) it would then need to re-transmit the expansion channel passing protocol to inform ich5 that dma channel 1 was still requesting the bus, even if that was the only request the expansion device had pending. ? if a pci dma expansion agent has a request go inactive before ich5 asserts gnt#, it must resend the expansion channel passing protocol to update ich5 with this new request information. for example: if a pci expansion agent has dma channel 1 and 2 requests pending it sends them serially to ich5 using the expansion channel passing protocol. if, however, dma channel 1 goes inactive into the expansion agent before the expansion agent receives a gnt# from ich5, the expansion agent must pull its req# line high for one clock and resend the expansion channel passing information with only dma channel 2 active. note that ich5 does not do anything special to catch this case because a dreq going inactive before a dack# is received is not allowed in the isa dma protocol and, therefore, does not need to work properly in this protocol either. this requirement is needed to be able to support plug-n-play isa devices that toggle dreq# lines to determine if those lines are free in the system. ? if a pci expansion agent has sent its serial request information and receives a new dma request before receiving gnt# the agent must resend the serial request with the new request active. for example: if a pci expansion agent has already passed requests for dma channel 1 and 2 and sees dreq 3 active before a gnt is received, the device must pull its req# line high for one clock and resend the expansion channel passing information with all three channels active. the three cases above require the following functionality in the pci dma expansion device: ? drive req# inactive for one clock to signal new request information. ? drive req# inactive for two clocks to signal that a request that had been granted the bus has gone inactive. ? the req# and gnt# state machines must run independently and concurrently (i.e., a gnt# could be received while in the middle of sending a serial req# or a gnt# could be active while req# is inactive). 5.6.2 pci dma expansion cycles ich5?s support of the pc/pci dma protocol currently consists of four types of cycles: memory- to-i/o, i/o-to-memory, verify, and isa master cycles. isa masters are supported through the use of a dma channel that has been programmed for cascade mode. the dma controller does a two cycle transfer (a load followed by a store) as opposed to the isa "fly-by" cycle for pc/pci dma agents. the memory portion of the cycle generates a pci memory read or memory write bus cycle, its address representing the selected memory. intel ? 82801eb ich5 / 82801er ich5r datasheet 115 functional description the i/o portion of the dma cycle generates a pci i/o cycle to one of four i/o addresses ( table 41 ). note that these cycles must be qualified by an active gnt# signal to the requesting device. 5.6.3 dma addresses the memory portion of the cycle generates a pci memory read or memory write bus cycle, its address representing the selected memory. the i/o portion of the dma cycle generates a pci i/o cycle to one of the four i/o addresses listed in table 41 . 5.6.4 dma data generation the data generated by pc/pci devices on i/o reads when they have an active gnt# is on the lower two bytes of the pci ad bus. table 42 lists the pci pins that the data appears on for 8- and 16-bit channels. each i/o read results in one memory write, and each memory read results in one i/o write. if the i/o device is 8 bit, the ich5 performs an 8-bit memory write. the ich5 does not assemble the i/o read into a dword for writing to memory. similarly, the ich5 does not disassemble a dword read from memory to the i/o device. 5.6.5 dma byte enable generation the byte enables generated by the ich5 on i/o reads and writes must correspond to the size of the i/o device. table 43 defines the byte enables asserted for 8- and 16-bit dma cycles. note: for verify cycles the value of the byte enables (bes) is a ?don?t care.? table 41. dma cycle vs. i/o address dma cycle type dma i/o address pci cycle type normal 00h i/o read/write normal tc 04h i/o read/write verify 0c0h i/o read verify tc 0c4h i/o read table 42. pci data bus vs. dma i/o port size pci dma i/o port size pci data bus connection byte ad[7:0] word ad[15:0] table 43. dma i/o cycle width vs. be[3:0]# be[3:0]# description 1110b 8-bit dma i/o cycle: channels 0?3 1100b 16-bit dma i/o cycle: channels 5?7 116 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.6.6 dma cycle termination dma cycles are terminated when a terminal count is reached in the dma controller and the channel is not in autoinitialize mode, or when the pc/pci device deasserts its request. the pc/pci device must follow explicit rules when deasserting its request, or the ich5 may not see it in time and run an extra i/o and memory cycle. the pc/pci device must deassert its request 7 pciclks before it generates trdy# on the i/o read or write cycle, or the ich5 is allowed to generate another dma cycle. for transfers to memory, this means that the memory portion of the cycle will be run without an asserted pc/pci req#. 5.6.7 lpc dma dma on lpc is handled through the use of the ldrq# lines from peripherals and special encodings on lad[3:0] from the host. single, demand, verify, and increment modes are supported on the lpc interface. channels 0?3 are 8 bit channels. channels 5?7 are 16-bit channels. channel 4 is reserved as a generic bus master request. 5.6.8 asserting dma requests peripherals that need dma service encode their requested channel number on the ldrq# signal. to simplify the protocol, each peripheral on the lpc i/f has its own dedicated ldrq# signal (they may not be shared between two separate peripherals). the ich5 has two ldrq# inputs, allowing at least two devices to support dma or bus mastering. ldrq# is synchronous with lclk (pci clock). as shown in figure 15 , the peripheral uses the following serial encoding sequence: ? peripheral starts the sequence by asserting ldrq# low (start bit). ldrq# is high during idle conditions. ? the next three bits contain the encoded dma channel number (msb first). ? the next bit (act) indicates whether the request for the indicated dma channel is active or inactive. the act bit is 1 (high) to indicate if it is active and 0 (low) if it is inactive. the case where act is low is rare, and is only used to indicate that a previous request for that channel is being abandoned. ? after the active/inactive indication, the ldrq# signal must go high for at least 1 clock. after that one clock, ldrq# signal can be brought low to the next encoding sequence. if another dma channel also needs to request a transfer, another sequence can be sent on ldrq#. for example, if an encoded request is sent for channel 2, and then channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral can send the encoded request for channel 3. this allows multiple dma agents behind an i/o device to request use of the lpc interface, and the i/o device does not need to self-arbitrate before sending the message. figure 15. dma request assertion through ldrq# start msb lsb act start lclk ldrq# intel ? 82801eb ich5 / 82801er ich5r datasheet 117 functional description 5.6.9 abandoning dma requests dma requests can be deasserted in two fashions: on error conditions by sending an ldrq# message with the ?act? bit set to 0, or normally through a sync field during the dma transfer. this section describes boundary conditions where the dma request needs to be removed prior to a data transfer. there may be some special cases where the peripheral desires to abandon a dma transfer. the most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its fifo, or software stopping a device prematurely. in these cases, the peripheral wishes to stop further dma activity. it may do so by sending an ldrq# message with the act bit as 0. however, since the dma request was seen by the ich5, there is no guarantee that the cycle has not been granted and will shortly run on lpc. therefore, peripherals must take into account that a dma cycle may still occur. the peripheral can choose not to respond to this cycle, in which case the host will abort it, or it can choose to complete the cycle normally with any random data. this method of dma deassertion should be prevented whenever possible, to limit boundary conditions both on the ich5 and the peripheral. 5.6.10 general flow of dma transfers arbitration for dma channels is performed through the 8237 within the host. once the host has won arbitration on behalf of a dma channel assigned to lpc, it asserts lframe# on the lpc i/f and begins the dma transfer. the general flow for a basic dma transfer is as follows: 1. ich5 starts transfer by asserting 0000b on lad[3:0] with lframe# asserted. 2. ich5 asserts ?cycle type? of dma, direction based on dma transfer direction. 3. ich5 asserts channel number and, if applicable, terminal count. 4. ich5 indicates the size of the transfer: 8 or 16 bits. 5. if a dma read? ? the ich5 drives the first 8 bits of data and turns the bus around. ? the peripheral acknowledges the data with a valid sync. ? if a 16-bit transfer, the process is repeated for the next 8 bits. 6. if a dma write? ? the ich5 turns the bus around and waits for data. ? the peripheral indicates data ready through sync and transfers the first byte. ? if a 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. the peripheral turns around the bus. 118 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.6.11 terminal count terminal count is communicated through lad3 on the same clock that dma channel is communicated on lad[2:0]. this field is the channel field. terminal count indicates the last byte of transfer, based upon the size of the transfer. for example, on an 8-bit transfer size (size field is 00b), if the tc bit is set, then this is the last byte. on a 16-bit transfer (size field is 01b), if the tc bit is set, then the second byte is the last byte. the peripheral, therefore, must internalize the tc bit when the channel field is communicated, and only signal tc when the last byte of that transfer size has been transferred. 5.6.12 verify mode verify mode is supported on the lpc interface. a verify transfer to the peripheral is similar to a dma write, where the peripheral is transferring data to main memory. the indication from the host is the same as a dma write, so the peripheral will be driving data onto the lpc interface. however, the host will not transfer this data into main memory. 5.6.13 dma request deassertion an end of transfer is communicated to the ich5 through a special sync field transmitted by the peripheral. an lpc device must not attempt to signal the end of a transfer by deasserting ldreq#. if a dma transfer is several bytes (e.g., a transfer from a demand mode device) the ich5 needs to know when to deassert the dma request based on the data currently being transferred. the dma agent uses a sync encoding on each byte of data being transferred, which indicates to the ich5 whether this is the last byte of transfer or if more bytes are requested. to indicate the last byte of transfer, the peripheral uses a sync value of 0000b (ready with no error), or 1010b (ready with error). these encodings tell the ich5 that this is the last piece of data transferred on a dma read (ich5 to peripheral), or the byte that follows is the last piece of data transferred on a dma write (peripheral to ich5). when the ich5 sees one of these two encodings, it ends the dma transfer after this byte and deasserts the dma request to the 8237. therefore, if the ich5 indicated a 16 bit transfer, the peripheral can end the transfer after one byte by indicating a sync value of 0000b or 1010b. the ich5 does not attempt to transfer the second byte, and deasserts the dma request internally. if the peripheral indicates a 0000b or 1010b sync pattern on the last byte of the indicated size, then the ich5 only deasserts the dma request to the 8237 since it does not need to end the transfer. if the peripheral wishes to keep the dma request active, then it uses a sync value of 1001b (ready plus more data). this tells the 8237 that more data bytes are requested after the current byte has been transferred, so the ich5 keeps the dma request active to the 8237. therefore, on an 8 bit transfer size, if the peripheral indicates a sync value of 1001b to the ich5, the data will be transferred and the dma request will remain active to the 8237. at a later time, the ich5 will then come back with another start ? cyctype ? channel ? size etc. combination to initiate another transfer to the peripheral. intel ? 82801eb ich5 / 82801er ich5r datasheet 119 functional description the peripheral must not assume that the next start indication from the ich5 is another grant to the peripheral if it had indicated a sync value of 1001b. on a single mode dma device, the 8237 will re-arbitrate after every transfer. only demand mode dma devices can be guaranteed that they will receive the next start indication from the ich5. note: indicating a 0000b or 1010b encoding on the sync field of an odd byte of a 16-bit channel (first byte of a 16 bit transfer) is an error condition. note: the host stops the transfer on the lpc bus as indicated, fills the upper byte with random data on dma writes (peripheral to memory), and indicates to the 8237 that the dma transfer occurred, incrementing the 8237?s address and decrementing its byte count. 5.6.14 sync field / ldrq# rules since dma transfers on lpc are requested through an ldrq# assertion message, and are ended through a sync field during the dma transfer, the peripheral must obey the following rule when initiating back-to-back transfers from a dma channel. the peripheral must not assert another message for eight lclks after a deassertion is indicated through the sync field. this is needed to allow the 8237, that typically runs off a much slower internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next agent. under default operation, the host only performs 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. the method by which this communication between host and peripheral through system bios is performed is beyond the scope of this specification. since the lpc host and lpc peripheral are motherboard devices, no ?plug-n-play? registry is required. the peripheral must not assume that the host is able to perform transfer sizes that are larger than the size allowed for the dma channel, and be willing to accept a size field that is smaller than what it may currently have buffered. to that end, it is recommended that future devices that may appear on the lpc bus, that require higher bandwidth than 8-bit or 16-bit dma allow, do so with a bus mastering interface and not rely on the 8237. 120 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.7 8254 timers (d31:f0) the ich5 contains three counters that have fixed uses. all registers and functions associated with the 8254 timers are in the core well. the 8254 unit is clocked by a 14.31818 mhz clock. counter 0, system timer this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value 1 counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by two each counter period. the counter then asserts irq0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating irq0. counter 1, refresh request signal this counter provides the refresh request signal and is typically programmed for mode 2 operation. the counter negates refresh request for 1 counter period (838 ns) during each count cycle. the initial count value is loaded 1 counter period after being written to the counter i/o address. the counter initially asserts refresh request, and negates it for 1 counter period when the count value reaches 1. the counter then asserts refresh request and continues counting from the initial count value. counter 2, speaker tone this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initial count value. the speaker must be enabled by a write to port 061h (see nmi status and control ports). 5.7.1 timer programming the counter/timers are programmed in the following fashion: 1. write a control word to select a counter. 2. write an initial count for that counter. 3. load the least and/or most significant bytes (as required by control word bits 5, 4) of the 16-bit counter. 4. repeat with other counters. only two conventions need to be observed when programming the counters. first, for each counter, the control word must be written before the initial count is written. second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). a new initial count may be written to a counter at any time without affecting the counter's programmed mode. counting is affected as described in the mode definitions. the new count must follow the programmed count format. intel ? 82801eb ich5 / 82801er ich5r datasheet 121 functional description if a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. the control word register at port 43h controls the operation of all three counters. several commands are available: ? control word command. specifies which counter to read or write, the operating mode, and the count format (binary or bcd). ? counter latch command. latches the current count so that it can be read by the system. the countdown process continues. ? read back command. reads the count value, programmed mode, the current state of the out pins, and the state of the null count flag of the selected counter. table 44 lists the six operating modes for the interval counters. 5.7.2 reading from the interval timer it is often desirable to read the value of a counter without disturbing the count in progress. there are three methods for reading the counters: a simple read operation, counter latch command, and the read-back command. each is explained below. with the simple read and counter latch command methods, the count must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other. read, write, or programming operations for other counters may be inserted between them. table 44. counter operating modes mode function description 0 out signal on end of count (=0) output is 0. when count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. 1 hardware retriggerable one-shot output is 0. when count goes to 0, output goes to 1 for one clock time. 2 rate generator (divide by n counter) output is 1. output goes to 0 for one clock time, then back to 1 and counter is reloaded. 3 square wave output output is 1. output goes to 0 when counter rolls over, and counter is reloaded. output goes to 1 when counter rolls over, and counter is reloaded, etc. 4 software triggered strobe output is 1. output goes to 0 when count expires for one clock time. 5 hardware triggered strobe output is 1. output goes to 0 when count expires for one clock time. 122 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.7.2.1 simple read the first method is to perform a simple read operation. the counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). note: performing a direct read from the counter does not return a determinate value, because the counting process is asynchronous to read operations. however, in the case of counter 2, the count can be stopped by writing to the gate bit in port 61h. 5.7.2.2 counter latch command the counter latch command, written to port 43h, latches the count of a specific counter at the time the command is received. this command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. the count value is then read from each counter?s count register as was programmed by the control register. the count is held in the latch until it is read or the counter is reprogrammed. the count is then unlatched. this allows reading the contents of the counters on the fly without affecting counting in progress. multiple counter latch commands may be used to latch more than one counter. counter latch commands do not affect the programmed mode of the counter in any way. if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read is the count at the time the first counter latch command was issued. 5.7.2.3 read back command the read back command, written to port 43h, latches the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the value of the counter and its status may then be read by i/o access to the counter address. the read back command may be used to latch multiple counter outputs at one time. this single command is functionally equivalent to several counter latch commands, one for each counter latched. each counter's latched count is held until it is read or reprogrammed. once read, a counter is unlatched. the other counters remain latched until they are read. if multiple count read back commands are issued to the same counter without reading the count, all but the first are ignored. the read back command may additionally be used to latch status information of selected counters. the status of a counter is accessed by a read from that counter's i/o port address. if multiple counter status latch operations are performed without reading the status, all but the first are ignored. both count and status of the selected counters may be latched simultaneously. this is functionally the same as issuing two consecutive, separate read back commands. if multiple count and/or status read back commands are issued to the same counters without any intervening reads, all but the first are ignored. if both count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latched first. the next one or two reads, depending on whether the counter is programmed for one or two type counts, returns the latched count. subsequent reads return unlatched count. intel ? 82801eb ich5 / 82801er ich5r datasheet 123 functional description 5.8 8259 interrupt controllers (pic) (d31:f0) the ich5 incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the isa compatible interrupts. these interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, ide, mouse, and dma channels. in addition, this interrupt controller can support the pci based interrupts, by mapping the pci interrupt onto the compatible isa interrupt line. each 8259 core supports eight interrupts, numbered 0 ? 7. table 45 shows how the cores are connected. . the ich5 cascades the slave controller onto the master controller through master controller interrupt input 2. this means there are only 15 possible interrupts for the ich5 pic. interrupts can individually be programmed to be edge or level, except for irq0, irq2, irq8#, and irq13. note that previous piixn devices internally latched irq12 and irq1 and required a port 60h read to clear the latch. the ich5 can be programmed to latch irq12 or irq1 (see bit 11 and bit 12 in general control register, d31:f0, offset d0h). note: active-low interrupt sources (e.g., the pirq#s) are inverted inside the ich5. in the following descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface of the 8259s, after the required inversions have occurred. therefore, the term ?high? indicates ?active,? which means ?low? on an originating pirq#. table 45. interrupt controller core connections 8259 8259 input typical interrupt source connected pin / function master 0 internal internal timer / counter 0 output / hpet#0 1 keyboard irq1 via serirq 2 internal slave controller intr output 3 serial port a irq3 via serirq 4 serial port b irq4 via serirq 5 parallel port / generic irq5 via serirq 6 floppy disk irq6 via serirq 7 parallel port / generic irq7 via serirq slave 0 internal real time clock internal rtc / hpet #1 1 generic irq9 via serirq 2 generic irq10 via serirq 3 generic irq11 via serirq 4 ps/2 mouse irq12 via serirq 5 internal state machine output based on processor ferr# assertion. 6 primary ide cable irq14 from input signal (primary ide in legacy mode only) or via serirq 7 secondary ide cable irq15 from input signal (secondary ide in legacy mode only) or via serirq 124 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.8.1 interrupt handling 5.8.1.1 generating interrupts the pic interrupt sequence involves three bits, from the irr, isr, and imr, for each interrupt level. these bits are used to determine the interrupt vector returned, and status of any other pending interrupts. table 46 defines the irr, isr, and imr. 5.8.1.2 acknowledging interrupts the processor generates an interrupt acknowledge cycle that is translated by the host bridge into a pci interrupt acknowledge cycle to the ich5. the pic translates this command into two internal inta# pulses expected by the 8259 cores. the pic uses the first internal inta# pulse to freeze the state of the interrupts for priority resolution. on the second inta# pulse, the master or slave sends the interrupt vector to the processor with the acknowledged interrupt code. this code is based upon bits [7:3] of the corresponding icw2 register, combined with three bits representing the interrupt within that controller. table 46. interrupt status registers bit description irr interrupt request register. this bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. this bit is set whether or not the interrupt is masked. however, a masked interrupt will not generate intr. isr interrupt service register. this bit is set, and the corresponding irr bit cleared, when an interrupt acknowledge cycle is seen, and the vector returned is for that interrupt. imr interrupt mask register. this bit determines whether an interrupt is masked. masked interrupts will not generate intr. table 47. content of interrupt vector byte master, slave interrupt bits [7:3] bits [2:0] irq7,15 icw2[7:3] 111 irq6,14 110 irq5,13 101 irq4,12 100 irq3,11 011 irq2,10 010 irq1,9 001 irq0,8 000 intel ? 82801eb ich5 / 82801er ich5r datasheet 125 functional description 5.8.1.3 hardware/software interrupt sequence 1. one or more of the interrupt request lines (irq) are raised high in edge mode, or seen high in level mode, setting the corresponding irr bit. 2. the pic sends intr active to the processor if an asserted interrupt is not masked. 3. the processor acknowledges the intr and responds with an interrupt acknowledge cycle. the cycle is translated into a pci interrupt acknowledge cycle by the host bridge. this command is broadcast over pci by the ich5. 4. upon observing its own interrupt acknowledge cycle on pci, the ich5 converts it into the two cycles that the internal 8259 pair can respond to. each cycle appears as an interrupt acknowledge pulse on the internal inta# pin of the cascaded interrupt controllers. 5. upon receiving the first internally generated inta# pulse, the highest priority isr bit is set and the corresponding irr bit is reset. on the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. the slave controller uses these bits to determine if it must respond with an interrupt vector during the second inta# pulse. 6. upon receiving the second internally generated inta# pulse, the pic returns the interrupt vector. if no interrupt request is present because the request was too short in duration, the pic returns vector 7 from the master controller. 7. this completes the interrupt cycle. in aeoi mode the isr bit is reset at the end of the second inta# pulse. otherwise, the isr bit remains set until an appropriate eoi command is issued at the end of the interrupt subroutine. 5.8.2 initialization command words (icwx) before operation can begin, each 8259 must be initialized. in the ich5, this is a four byte sequence. the four initialization command words are referred to by their acronyms: icw1, icw2, icw3, and icw4. the base address for each 8259 initialization command word is a fixed location in the i/o memory space: 20h for the master controller, and a0h for the slave controller. 5.8.2.1 icw1 an i/o write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to icw1. upon sensing this write, the ich5 pic expects three more byte writes to 21h for the master controller, or a1h for the slave controller, to complete the icw sequence. a write to icw1 starts the initialization sequence during which the following automatically occur: 1. following initialization, an interrupt request (irq) input must make a low-to-high transition to generate an interrupt. 2. the interrupt mask register is cleared. 3. irq7 input is assigned priority 7. 4. the slave mode address is set to 7. 5. special mask mode is cleared and status read is set to irr. 126 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.8.2.2 icw2 the second write in the sequence (icw2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. a different base is selected for each interrupt controller. 5.8.2.3 icw3 the third write in the sequence (icw3) has a different meaning for each controller. ? for the master controller, icw3 is used to indicate which irq input line is used to cascade the slave controller. within the ich5, irq2 is used. therefore, bit 2 of icw3 on the master controller is set to a 1, and the other bits are set to 0s. ? for the slave controller, icw3 is the slave identification code used during an interrupt acknowledge cycle. on interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. the slave controller compares this identification code to the value stored in its icw3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 5.8.2.4 icw4 the final write in the sequence (icw4) must be programmed for both controllers. at the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an intel architecture-based system. 5.8.3 operation command words (ocw) these command words reprogram the interrupt controller to operate in various interrupt modes. ? ocw1 masks and unmasks interrupt lines. ? ocw2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the eoi function. ? ocw3 is sets up isr/irr reads, enables/disables the special mask mode (smm), and enables/ disables polled interrupt mode. 5.8.4 modes of operation 5.8.4.1 fully nested mode in this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest. when an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. additionally, the isr for the interrupt is set. this isr bit remains set until: the processor issues an eoi command immediately before returning from the service routine; or if in aeoi mode, on the trailing edge of the second inta#. while the isr bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels generate another interrupt. interrupt priorities can be changed in the rotating priority mode. intel ? 82801eb ich5 / 82801er ich5r datasheet 127 functional description 5.8.4.2 special fully-nested mode this mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. in this case, the special fully-nested mode is programmed to the master controller. this mode is similar to the fully-nested mode with the following exceptions: ? when an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave are recognized by the master and initiate interrupts to the processor. in the normal- nested mode, a slave is masked out when its request is in service. ? when exiting the interrupt service routine, software has to check whether the interrupt serviced was the only one from that slave. this is done by sending a non-specific eoi command to the slave and then reading its isr. if it is 0, a non-specific eoi can also be sent to the master. 5.8.4.3 automatic rotation mode (equal priority devices) in some applications, there are a number of interrupting devices of equal priority. automatic rotation mode provides for a sequential 8-way rotation. in this mode, a device receives the lowest priority after being serviced. in the worst case, a device requesting an interrupt has to wait until each of seven other devices are serviced at most once. there are two ways to accomplish automatic rotation using ocw2; the rotation on non-specific eoi command (r=1, sl=0, eoi=1) and the rotate in automatic eoi mode which is set by (r=1, sl=0, eoi=0). 5.8.4.4 specific rotation mode (specific priority) software can change interrupt priorities by programming the bottom priority. for example, if irq5 is programmed as the bottom priority device, then irq6 is the highest priority device. the set priority command is issued in ocw2 to accomplish this, where: r=1, sl=1, and lo?l2 is the binary priority level code of the bottom priority device. in this mode, internal status is updated by software control during ocw2. however, it is independent of the eoi command. priority changes can be executed during an eoi command by using the rotate on specific eoi command in ocw2 (r=1, sl=1, eoi=1 and lo?l2=irq level to receive bottom priority. 5.8.4.5 poll mode poll mode can be used to conserve space in the interrupt vector table. multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command. poll mode can also be used to expand the number of interrupts. the polling interrupt service routine can call the appropriate service routine, instead of providing the interrupt vectors in the vector table. in this mode, the intr output is not used and the microprocessor internal interrupt enable flip-flop is reset, disabling its interrupt input. service to devices is achieved by software using a poll command. the poll command is issued by setting p=1 in ocw3. the pic treats its next i/o read as an interrupt acknowledge, sets the appropriate isr bit if there is a request, and reads the priority level. interrupts are frozen from the ocw3 write to the i/o read. the byte returned during the i/o read contains a 1 in bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. 128 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.8.4.6 cascade mode the pic in the ich5 has one master 8259 and one slave 8259 cascaded onto the master through irq2. this configuration can handle up to 15 separate priority levels. the master controls the slaves through a three bit internal bus. in the ich5, when the master drives 010b on this bus, the slave controller takes responsibility for returning the interrupt vector. an eoi command must be issued twice: once for the master and once for the slave. 5.8.4.7 edge and level triggered mode in isa systems this mode is programmed using bit 3 in icw1, which sets level or edge for the entire controller. in the ich5, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. this is the edge/level control registers elcr1 and elcr2. if an elcr bit is 0, an interrupt request will be recognized by a low-to-high transition on the corresponding irq input. the irq input can remain high without generating another interrupt. if an elcr bit is 1, an interrupt request will be recognized by a high level on the corresponding irq input and there is no need for an edge detection. the interrupt request must be removed before the eoi command is issued to prevent a second interrupt from occurring. in both the edge and level triggered modes, the irq inputs must remain active until after the falling edge of the first internal inta#. if the irq input goes inactive before this time, a default irq7 vector is returned. 5.8.4.8 end of interrupt operations an eoi can occur in one of two fashions: by a command word write issued to the pic before returning from a service routine, the eoi command; or automatically when aeoi bit in icw4 is set to 1. 5.8.4.9 normal end of interrupt in normal eoi, software writes an eoi command before leaving the interrupt service routine to mark the interrupt as completed. there are two forms of eoi commands: specific and non-specific. when a non-specific eoi command is issued, the pic clears the highest isr bit of those that are set to 1. non-specific eoi is the normal mode of operation of the pic within the ich5, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. when the pic is operated in modes that preserve the fully nested structure, software can determine which isr bit to clear by issuing a specific eoi. an isr bit that is masked is not cleared by a non-specific eoi if the pic is in the special mask mode. an eoi command must be issued for both the master and slave controller. 5.8.4.10 automatic end of interrupt mode in this mode, the pic automatically performs a non-specific eoi operation at the trailing edge of the last interrupt acknowledge pulse. from a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single pic. the aeoi mode can only be used in the master controller and not the slave controller. intel ? 82801eb ich5 / 82801er ich5r datasheet 129 functional description 5.8.5 masking interrupts 5.8.5.1 masking on an individual interrupt request each interrupt request can be masked individually by the interrupt mask register (imr). this register is programmed through ocw1. each bit in the imr masks one interrupt channel. masking irq2 on the master controller masks all requests for service from the slave controller. 5.8.5.2 special mask mode some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. for example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. the special mask mode enables all interrupts not masked by a bit set in the mask register. normally, when an interrupt service routine acknowledges an interrupt without issuing an eoi to clear the isr bit, the interrupt controller inhibits all lower priority requests. in the special mask mode, any interrupts may be selectively enabled by loading the mask register with the appropriate pattern. the special mask mode is set by ocw3 where: ssmm=1, smm=1, and cleared where ssmm=1, smm=0. 5.8.6 steering pci interrupts the ich5 can be programmed to allow pirqa#-pirqh# to be internally routed to interrupts 3?7, 9?12, 14 or 15. the assignment is programmable through the pirqx route control registers, located at 60?63h and 68?6bh in function 0. one or more pirqx# lines can be routed to the same irqx input. if interrupt steering is not required, the route registers can be programmed to disable steering. the pirqx# lines are defined as active low, level sensitive to allow multiple interrupts on a pci board to share a single line across the connector. when a pirqx# is routed to specified irq line, software must change the irq's corresponding elcr bit to level sensitive mode. the ich5 internally inverts the pirqx# line to send an active high level to the pic. when a pci interrupt is routed onto the pic, the selected irq can no longer be used by an isa device (through serirq). however, active low non-isa interrupts can share their interrupt with pci interrupts. internal sources of the pirqs, including sci and tco interrupts, cause the external pirq to be asserted. the ich5 receives the pirq input, like all of the other external sources, and routes it accordingly. 130 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.9 advanced interrupt controller (apic) (d31:f0) in addition to the standard isa-compatible pic described in the previous chapter, the ich5 incorporates the apic. while the standard interrupt controller is intended for use in a uni-processor system, apic can be used in either a uni-processor or multi-processor system. 5.9.1 interrupt handling the i/o apic handles interrupts very differently than the 8259. briefly, these differences are: ? method of interrupt transmission. the i/o apic transmits interrupts through memory writes on the normal datapath to the processor, and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. ? interrupt priority. the priority of interrupts in the i/o apic is independent of the interrupt number. for example, interrupt 10 can be given a higher priority than interrupt 3. ? more interrupts. the i/o apic in the ich5 supports a total of 24 interrupts. ? multiple interrupt controllers. the i/o apic architecture allows for multiple i/o apic devices in the system with their own interrupt vectors. 5.9.2 interrupt mapping the i/o apic within the ich5 supports 24 apic interrupts. each interrupt has its own unique vector assigned by software. the interrupt vectors are mapped as follows, and match ?config 6? of the multi-processor specification. table 48. apic interrupt mapping (sheet 1 of 2) irq # via serirq direct from pin via pci message internal modules 0 no no no cascade from 8259 #1 1yes no yes 2 no no no 8254 counter 0, hpet #0 (legacy mode) 3yes no yes 4yes no yes 5yes no yes 6yes no yes 7yes no yes 8 no no no rtc, hpet #1 (legacy mode) 9 yes no yes option for sci, tco 10 yes no yes option for sci, tco 11 yes no yes hpet #2, option for sci, tco 12 yes no yes 13 no no no ferr# logic 14 yes yes 1 yes storage (ide/sata) primary (legacy mode) 15 yes yes 1 yes storage (ide/sata) secondary (legacy mode) intel ? 82801eb ich5 / 82801er ich5r datasheet 131 functional description notes: 1. irq 14 and 15 can only be driven directly from the pins when in legacy ide mode. 2. when programming the polarity of internal interrupt sources on the apic, interrupts 0 through 15 receive active-high internal interrupt sources, while interrupts 16 through 23 receive active-low internal interrupt sources. 3. if irq 11 is used for hpet #2, software should ensure irq 11 is not shared with any other devices to guarantee the proper operation of hpet #2. ich5 hardware does not prevent sharing of irq 11. 4. pci message interrupts are not prevented by hardware in these cases. however, the system must not program these interrupts as edge-triggered (as required for pci message interrupts) because the internal and external pirqs on these inputs must be programmed in level-triggered modes. 5.9.3 pci message-based interrupts the following scheme is only supported when the internal i/o(x) apic is used (rather than just the 8259). the ich5 supports the new method for pci devices to deliver interrupts as write cycles, rather than using the traditional pirq[a:d] signals. essentially, the pci devices are given a write path directly to a register that will cause the desired interrupt. this mode is only supported when the ich5?s internal i/o apic is enabled. the interrupts associated with the pci message-based interrupt method must be set up for edge triggered mode, rather than level triggered, since the peripheral only does the write to indicate the edge. 16 pirqa# pirqa# no 4 usb uhci controller #1, usb uhci controller #4 17 pirqb# pirqb# no 4 ac ?97 audio, modem, option for smbus 18 pirqc# pirqc# no 4 usb uhci controller #3, storage (ide/sata) native mode 19 pirqd# pirqd# no 4 usb uhci controller #2 20 n/a pirqe# no 4 lan, option for sci, tco, hpet #0,1,2 21 n/a pirqf# yes option for sci, tco, hpet #0,1,2 22 n/a pirqg# yes option for sci, tco, hpet #0,1,2 23 n/a pirqh# no 4 usb ehci controller, option for sci, tco, hpet #0,1,2 table 48. apic interrupt mapping (sheet 2 of 2) irq # via serirq direct from pin via pci message internal modules 132 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description the following sequence is used: 1. during pci pnp, the pci peripheral is first programmed with an address (message_address) and data value (message_data) that will be used for the interrupt message delivery. for the ich5, the message_address is the irq pin assertion register, which is mapped to memory location: fec0_0020h. 2. to cause the interrupt, the pci peripheral requests the pci bus and when granted, writes the message_data value to the location indicated by the message_address. the message_data value indicates which interrupt occurred. this message_data value is a binary encoded. for example, to indicate that interrupt 7 should go active, the peripheral will write a binary value of 0000111. the message_data is a 32-bit value, although only the lower 5 bits are used. 3. if the prq bit in the apic version register is set, the ich5 positively decodes the cycles (as a slave) in medium time. 4. the ich5 decodes the binary value written to message_address and sets the appropriate irr bit in the internal i/o apic. the corresponding interrupt must be set up for edge-triggered interrupts. the ich5 supports interrupts 00h through 23h. binary values outside this range do not cause any action. 5. after sending the interrupt message to the processor, the ich5 automatically clears the interrupt. because they are edge triggered, the interrupts that are allocated to the pci bus for this scheme may not be shared with any other interrupt (such as the standard pci pirq[a:d], those received via serirq#, or the internal level-triggered interrupts such as sci or tco). the ich5 ignores interrupt messages sent by pci masters that attempt to use irq0, 2, 8, or 13. 5.9.3.1 registers and bits associated with pci interrupt delivery capabilities indication the capability to support pci interrupt delivery are indicated via acpi configuration techniques. this involves the bios creating a data structure that gets reported to the acpi configuration software. the os reads the prq bit in the apic version register to see if the ich5 is capable of support pci-based interrupt messages. as a precaution, the prq bit is not set if the xapic_en bit is not set. interrupt message register the pci devices all write their message into the irq pin assertion register, which is a memory- mapped register located at the apic base memory location + 20h. intel ? 82801eb ich5 / 82801er ich5r datasheet 133 functional description 5.9.4 front side bus interrupt delivery for processors that support front side bus (fsb) interrupt delivery, the ich5 requires that the i/o apic deliver interrupt messages to the processor in a parallel manner, rather than using the i/o apic serial scheme. this is done by the ich5 writing (via the hub interface) to a memory location that is snooped by the processor(s). the processor(s) snoop the cycle to know which interrupt goes active. the following sequence is used: 1. when the ich5 detects an interrupt event (active edge for edge-triggered mode or a change for level-triggered mode), it sets or resets the internal irr bit associated with that interrupt. 2. internally, the ich5 requests to use the bus in a way that automatically flushes upstream buffers. this can be internally implemented similar to a dma device request. 3. the ich5 then delivers the message by performing a write cycle to the appropriate address with the appropriate data. the address and data formats are described below in section 5.9.4.4 . note: fsb interrupt delivery compatibility with processor clock control depends on the processor, not the ich5. 5.9.4.1 edge-triggered operation in this case, the ?assert message? is sent when there is an inactive-to-active edge on the interrupt. 5.9.4.2 level-triggered operation in this case, the ?assert message? is sent when there is an inactive-to-active edge on the interrupt. if after the eoi the interrupt is still active, then another ?assert message? is sent to indicate that the interrupt is still active. 5.9.4.3 registers associated with front side bus interrupt delivery capabilities indication: the capability to support front side bus interrupt delivery is indicated via acpi configuration techniques. this involves the bios creating a data structure that gets reported to the acpi configuration software. 5.9.4.4 interrupt message format the ich5 writes the message to pci (and to the host controller) as a 32-bit memory write cycle. it uses the formats shown in table 49 and table 50 for the address and data. the local apic (in the processor) has a delivery mode option to interpret front side bus messages as a smi in which case the processor treats the incoming interrupt as a smi instead of as an interrupt. this does not mean that the ich5 has any way to have a smi source from ich5 power management logic cause the i/o apic to send an smi message (there is no way to do this). the ich5?s i/o apic can only send interrupts due to interrupts which do not include smi, nmi or init. this means that in ia32/ia64 based platforms, front side bus interrupt message format delivery modes 010 (smi/pmi), 100 (nmi), and 101 (init) as indicated in this section, must not be used and is not supported. only the hardware pin connection is supported by ich5. 134 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description : table 49. interrupt message address format bit description 31:20 will always be feeh 19:12 destination id: this is the same as bits 63:56 of the i/o redirection table entry for the interrupt associated with this message. 11:4 extended destination id : this is the same as bits 55:48 of the i/o redirection table entry for the interrupt associated with this message. 3 redirection hint: this bit is used by the processor host bridge to allow the interrupt message to be redirected. 0 = the message will be delivered to the agent (processor) listed in bits 19:12. 1 = the message will be delivered to an agent with a lower interrupt priority this can be derived from bits 10:8 in the data field (see below). the redirection hint bit will be a 1 if bits 10:8 in the delivery mode field associated with corresponding interrupt are encoded as 001 (lowest priority). otherwise, the redirection hint bit will be 0 2 destination mode: this bit is used only the redirection hint bit is set to 1. if the redirection hint bit and the destination mode bit are both set to 1, then the logical destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical id. 1:0 will always be 00. table 50. interrupt message data format bit description 31:16 will always be 0000h. 15 trigger mode: 1 = level, 0 = edge. same as the corresponding bit in the i/o redirection table for that interrupt. 14 delivery status: 1 = assert, 0 = deassert. if using edge-triggered interrupts, then bit is always 1, since only the assertion is sent. if using level-triggered interrupts, then this bit indicates the state of the interrupt input. 13:12 will always be 00 11 destination mode: 1 = logical. 0 = physical. same as the corresponding bit in the i/o redirection table for that interrupt. 10:8 delivery mode: this is the same as the corresponding bits in the i/o redirection table for that interrupt. 000 = fixed 100 = nmi 001 = lowest priority 101 = init 010 = smi/pmi 110 = reserved 011 = reserved 111 = extint 7:0 vector: this is the same as the corresponding bits in the i/o redirection table for that interrupt. intel ? 82801eb ich5 / 82801er ich5r datasheet 135 functional description 5.10 serial interrupt (d31:f0) the ich5 supports a serial irq scheme. this allows a single signal to be used to report interrupt requests. the signal used to transmit this information is shared between the host, the ich5, and all peripherals that support serial interrupts. the signal line, serirq, is synchronous to pci clock, and follows the sustained tri-state protocol that is used by all pci signals. this means that if a device has driven serirq low, it will first drive it high synchronous to pci clock and release it the following pci clock. the serial irq protocol defines this sustained tri-state signaling in the following fashion: ? s ? sample phase. signal driven low ? r ? recovery phase. signal driven high ? t ? turn-around phase. signal released the ich5 supports a message for 21 serial interrupts. these represent the 15 isa interrupts (irq0?1, 2?15), the four pci interrupts, and the control signals smi# and iochk#. the serial irq protocol does not support the additional apic interrupts (20?23). note: when the ide primary and secondary controllers are configured for native ide mode, the only way to use the internal irq14 and irq15 connections to the interrupt controllers is through the serial interrupt pin. 5.10.1 start frame the serial irq protocol has two modes of operation which affect the start frame. these two modes are: continuous, where the ich5 is solely responsible for generating the start frame; and quiet, where a serial irq peripheral is responsible for beginning the start frame. the mode that must first be entered when enabling the serial irq protocol is continuous mode. in this mode, the ich5 asserts the start frame. this start frame is 4, 6, or 8 pci clocks wide based upon the serial irq control register, bits 1:0 at 64h in device 31:function 0 configuration space. this is a polling mode. when the serial irq stream enters quiet mode (signaled in the stop frame), the serirq line remains inactive and pulled up between the stop and start frame until a peripheral drives the serirq signal low. the ich5 senses the line low and continues to drive it low for the remainder of the start frame. since the first pci clock of the start frame was driven by the peripheral in this mode, the ich5 drives the serirq line low for 1 pci clock less than in continuous mode. this mode of operation allows for a quiet, and therefore lower power, operation. 136 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.10.2 data frames once the start frame has been initiated, all of the serirq peripherals must start counting frames based on the rising edge of serirq. each of the irq/data frames has exactly 3 phases of 1 clock each: ? sample phase. during this phase, the serirq device drives serirq low if the corresponding interrupt signal is low. if the corresponding interrupt is high, then the serirq devices tri-state the serirq signal. the serirq line remains high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). a low level during the irq0 ? 1 and irq2 ? 15 frames indicates that an active-high isa interrupt is not being requested, but a low level during the pci int[a:d], smi#, and iochk# frame indicates that an active-low interrupt is being requested. ? recovery phase. during this phase, the device drives the serirq line high if in the sample phase it was driven low. if it was not driven in the sample phase, it is tri-stated in this phase. ? turn-around phase. the device tri-states the serirq line 5.10.3 stop frame after all data frames, a stop frame is driven by the ich5. the serirq signal is driven low by the ich5 for 2 or 3 pci clocks. the number of clocks is determined by the serirq configuration register. the number of clocks determines the next mode: 5.10.4 specific interrupts not supported via serirq there are three interrupts seen through the serial stream that are not supported by the ich5. these interrupts are generated internally, and are not sharable with other devices within the system. these interrupts are: ? irq0. heartbeat interrupt generated off of the internal 8254 counter 0. ? irq8#. rtc interrupt can only be generated internally. ? irq13. floating point error interrupt generated off of the processor assertion of ferr#. the ich5 ignores the state of these interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream. in addition, the interrupts irq14 and irq15 from the serial stream are treated differently than their isa counterparts. these two frames are not passed to the bus master ide logic. the bus master ide logic expects ide to be behind the ich5. table 51. stop frame explanation stop frame width next mode 2 pci clocks quiet mode. any serirq device may initiate a start frame 3 pci clocks continuous mode. only the host (intel ? ich5) may initiate a start frame intel ? 82801eb ich5 / 82801er ich5r datasheet 137 functional description 5.10.5 data frame format table 52 shows the format of the data frames. for the pci interrupts (a ? d), the output from the ich5 is anded with the pci input signal. this way, the interrupt can be signaled via both the pci interrupt input signal and via the serirq signal (they are shared). 5.11 real time clock (d31:f0) the real time clock (rtc) module provides a battery backed-up date and time keeping device with two banks of static ram with 128 bytes each, although the first bank has 114 bytes for general purpose usage. three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 s to 500 ms, and end of update cycle notification. seconds, minutes, hours, days, day of week, month, and year are counted. daylight savings compensation is optional. the hour is represented in twelve or twenty-four hour format, and data can be represented in bcd or binary format. the design is meant to be functionally compatible with the motorola ms146818b. the time keeping comes from a 32.768 khz oscillating source, which is divided to achieve an update every second. the lower 14 bytes on the lower ram block has very specific functions. the first ten are for time and date information. the next four (0ah to 0dh) are registers, which configure and report rtc functions. table 52. data frame format data frame # interrupt clocks past start frame comment 1 irq0 2 ignored. irq0 can only be generated via the internal 8524 2irq1 5 3 smi# 8 causes smi# if low. will set the serirq_smi_sts bit. 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23 9 irq8 26 ignored. irq8# can only be generated internally or on isa. 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 ignored. irq13 can only be generated from ferr# 15 irq14 44 do not include in bm ide interrupt logic 16 irq15 47 do not include in bm ide interrupt logic 17 iochck# 50 same as isa iochck# going active. 18 pci inta# 53 drive pirqa# 19 pci intb# 56 drive pirqb# 20 pci intc# 59 drive pirqc# 21 pci intd# 62 drive pirqd# 138 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description the time and calendar data should match the data mode (bcd or binary) and hour mode (12 or 24 hour) as selected in register b. it is up to the programmer to make sure that data stored in these locations is within the reasonable values ranges and represents a possible date and time. the exception to these ranges is to store a value of c0?ff in the alarm bytes to indicate a don?t care situation. all alarm conditions must match to trigger an alarm flag, which could trigger an alarm interrupt if enabled. the set bit must be 1 while programming these locations to avoid clashes with an update cycle. access to time and date information is done through the ram locations. if a ram read from the ten time and date bytes is attempted during an update cycle, the value read do not necessarily represent the true contents of those locations. any ram writes under the same conditions are ignored. note: the leap year determination for adding a 29th day to february does not take into account the end-of-the-century exceptions. the logic simply assumes that all years divisible by 4 are leap years. according to the royal observatory greenwich, years that are divisible by 100 are typically not leap years. in every fourth century (years divisible by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. note that the year 2100 will be the first time in which the current rtc implementation would incorrectly calculate the leap-year. the ich5 does not implement month/year alarms. 5.11.1 update cycles an update cycle occurs once a second, if the set bit of register b is not asserted and the divide chain is properly configured. during this procedure, the stored time and date are incremented, overflow is checked, a matching alarm condition is checked, and the time and date are rewritten to the ram locations. the update cycle will start at least 488 s after the uip bit of register a is asserted, and the entire cycle does not take more than 1984 s to complete. the time and date ram locations (0 ? 9) are disconnected from the external bus during this time. to avoid update and data corruption conditions, external ram access to these locations can safely occur at two times. when a updated-ended interrupt is detected, almost 999 ms is available to read and write the valid time and date data. if the uip bit of register a is detected to be low, there is at least 488 s before the update cycle begins. warning: the overflow conditions for leap years and daylight savings adjustments are based on more than one date or time item. to ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs. 5.11.2 interrupts the real-time clock interrupt is internally routed within the ich5 both to the i/o apic and the 8259. it is mapped to interrupt vector 8. this interrupt does not leave the ich5, nor is it shared with any other interrupt. irq8# from the serirq stream is ignored. intel ? 82801eb ich5 / 82801er ich5r datasheet 139 functional description 5.11.3 lockable ram ranges the rtc?s battery-backed ram supports two 8-byte ranges that can be locked via the configuration space. if the locking bits are set, the corresponding range in the ram will not be readable or writable. a write cycle to those locations will have no effect. a read cycle to those locations will not return the location?s actual value (may be all 0s or all 1s). once a range is locked, the range can be unlocked only by a hard reset, which will invoke the bios and allow it to relock the ram range. 5.11.4 century rollover the ich5 detects a rollover when the year byte (rtc i/o space, index offset 09h) transitions form 99 to 00. upon detecting the rollover, the ich5 sets the newcentury_sts bit (tcobase + 04h, bit 7). if the system is in an s0 state, this causes an smi#. the smi# handler can update registers in the rtc ram that are associated with century value. if the system is in a sleep state (s1 ? s5) when the century rollover occurs, the ich5 also sets the newcentury_sts bit, but no smi# is generated. when the system resumes from the sleep state, bios should check the newcentury_sts bit and update the century value in the rtc ram. 5.11.5 clearing battery-backed rtc ram clearing cmos ram in an ich5-based platform can be done by using a jumper on rtcrst# or gpi, or using safemode strap. implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. using rtcrst# to clear cmos a jumper on rtcrst# can be used to clear cmos values, as well as reset to default, the state of those configuration bits that reside in the rtc power well. when the rtcrst# is strapped to ground, the rtc_pwr_sts bit (d31:f0:a4h bit 2) will be set and those configuration bits in the rtc power well will be set to their default state. bios can monitor the state of this bit, and manually clear the rtc cmos array once the system is booted. the normal position would cause rtcrst# to be pulled up through a weak pull-up resistor. table 53 shows which bits are set to their default state when rtcrst# is asserted. 140 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description using a gpi to clear cmos a jumper on a gpi can also be used to clear cmos values. bios would detect the setting of this gpi on system boot-up, and manually clear the cmos array. using the safemode strap to clear cmos a jumper on ac_sdout (safemode strap) can also be used to clear cmos values. bios would detect the setting of the safe_mode status bit (d31:f0: offset d4h bit 2) on system boot-up, and manually clear the cmos array. note: both the gpi and safemode strap techniques to clear cmos require multiple steps to implement. the system is booted with the jumper in new position, then powered back down. the jumper is replaced back to the normal position, then the system is rebooted again. the rtcrst# jumper technique allows the jumper to be moved and then replaced, all while the system is powered off. then, once booted, the rtc_pwr_sts can be detected in the set state. note: clearing cmos, using a jumper on vccrtc, must not be implemented. table 53. configuration bits reset by rtcrst# assertion bit name default state register location bit(s) freq_strap[3:0] gen_sts d31:f0:d4h 11:8 1111b aie rtc reg b i/o space 5 0 af rtc reg c i/o space 5 0 pwr_flr gen_pmcon_3 d31:f0:a4h 1 0 afterg3_en gen_pmcon_3 d31:f0:a4h 0 0 rtc_pwr_sts gen_pmcon_3 d31:f0:a4h 2 1 prbtnor_sts pm1_sts pmbase + 00h 11 0 pme_en gpe0_en pmbase + 2ah 11 0 ri_en gpe0_en pmbase + 2ah 8 0 new_century_sts tco1_sts tcobase + 04h 7 0 intrd_det tco2_sts tcobase + 06h 0 0 top_swap gen_sts d31:f0:d4h 13 0 rtc_en pm1_en pmbase + 02h 10 0 batlow_en gpe0_en pmbase + 2ah 10 0 intel ? 82801eb ich5 / 82801er ich5r datasheet 141 functional description 5.12 processor interface (d31:f0) the ich5 interfaces to the processor with a variety of signals ? standard outputs to processor: a20m#, smi#, nmi, init#, intr, stpclk#, ignne#, cpuslp#, cpupwrgd ? standard input from processor: ferr# most ich5 outputs to the processor use standard buffers. the ich5 has separate v_cpu_io signals that are pulled up at the system level to the processor voltage, and thus determines v oh for the outputs to the processor. note that this is different than previous generations of chips, that have used open-drain outputs. this new method saves up to 12 external pull-up resistors. the ich5 also handles the speed setting for the processor by holding specific signals at certain states just prior to cpurst going inactive. this avoids the glue often required with other chipsets. the ich5 does not support the processor?s frc mode. 5.12.1 processor interface signals this section describes each of the signals that interface between the ich5 and the processor(s). note that the behavior of some signals may vary during processor reset, as the signals are used for frequency strapping. 5.12.1.1 a20m# (mask a20) the a20m# signal is active (low) when both of the following conditions are true: ? the alt_a20_gate bit (bit 1 of port92 register) is a 0 ? the a20gate input signal is a 0 the a20gate input signal is expected to be generated by the external microcontroller (kbc). 5.12.1.2 init# (initialization) the init# signal is active (driven low) based on any one of several events described in table 54 . when any of these events occur, init# is driven low for 16 pci clocks, then driven high. note: the 16-clock counter for init# assertion halts while stpclk# is active. therefore, if init# is supposed to go active while stpclk# is asserted, it actually goes active after stpclk# goes inactive. 142 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.12.1.3 ferr#/ignne# (numeric coprocessor error / ignore numeric error) the ich5 supports the coprocessor error function with the ferr#/ignne# pins. the function is enabled via the coproc_err_en bit (device 31:function 0, offset d0, bit 13). ferr# is tied directly to the coprocessor error signal of the processor. if ferr# is driven active by the processor, irq13 goes active (internally). when it detects a write to the coproc_err register, the ich5 negates the internal irq13 and drives ignne# active. ignne# remains active until ferr# is driven inactive. ignne# is never driven active unless ferr# is active. if coproc_err_en is not set, the assertion of ferr# will have not generate an internal irq13, nor will the write to f0h generate ignne#. table 54. init# going active cause of init# going active comment shutdown special cycle from processor. port92 write, where init_now (bit 0) transitions from a 0 to a 1. portcf9 write, where sys_rst (bit 1) was a 0 and rst_cpu (bit 2) transitions from 0 to 1. rcin# input signal goes low. rcin# is expected to be driven by the external microcontroller (kbc). 0 to 1 transition on rcin# must occur before the intel ? ich5 will arm init# to be generated again. note: rcin# signal is expected to be low during s3, s4, and s5 states. transition on the rcin# signal in those states (or the transition to those states) may not necessarily cause the init# signal to be generated to the processor. cpu bist to enter bist, software sets cpu_bist_en bit and then does a full processor reset using the cf9 register. figure 16. coprocessor error timing diagram ferr# internal irq13 i/o write to f0h ignne# intel ? 82801eb ich5 / 82801er ich5r datasheet 143 functional description 5.12.1.4 nmi (non-maskable interrupt) non-maskable interrupts (nmis) can be generated by several sources, as described in table 55 . 5.12.1.5 stop clock request and cpu sleep (stpclk# and cpuslp#) the ich5 power management logic controls these active-low signals. refer to section 5.13 for more information on the functionality of these signals. 5.12.1.6 cpu power good (cpupwrgood) this signal is connected to the processor?s pwrgood input. this is an open-drain output signal (external pull-up resistor required) that represents a logical and of the ich5?s pwrok and vrmpwrgd signals. 5.12.2 dual-processor issues 5.12.2.1 signal differences in dual-processor designs, some of the processor signals are unused or used differently than for uniprocessor designs. table 55. nmi sources cause of nmi comment serr# goes active (either internally, externally via serr# signal, or via message from mch) can instead be routed to generate an sci, through the nmi2sci_en bit (device 31:function 0, offset 4e, bit 11). iochk# goes active via serirq# stream (isa system error) can instead be routed to generate an sci, through the nmi2sci_en bit (device 31:function 0, offset 4e, bit 11). table 56. dp signal differences signal difference a20m# / a20gate generally not used, but still supported by intel ? ich5. stpclk# used for s1 state as well as preparation for entry to s3?s5 also allows for therm# based throttling (not via acpi control methods). should be connected to both processors. ferr# / ignne# generally not used, but still supported by ich5. 144 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.12.2.2 power management attempting clock control with more than one processor is not feasible, because the host controller does not provide any indication as to which processor is executing a particular stop-grant cycle. without this information, there is no way for the ich5 to know when it is safe to deassert stpclk#. because the s1 state will have the stpclk# signal active, the stpclk# signal can be connected to both processors. the bios must indicate that the ich5 only supports the c1 state for dual- processor designs. however, the thrm# signal can be used for overheat conditions to activate thermal throttling. when entering s1, the ich5 asserts stpclk# to both processors. to meet the processor specifications, the cpuslp# signal will have to be delayed until the second stop-grant cycle occurs. to ensure this, the ich5 waits a minimum or 60 pci clocks after receipt of the first stop- grant cycle before asserting cpuslp# (if the slp_en bit is set to 1). both processors must immediately respond to the stpclk# assertion with stop grant acknowledge cycles before the ich5 asserts cpuslp# in order to meet the processor setup time for cpuslp#. meeting the processor setup time for cpuslp# is not an issue if both processors are idle when the system is entering s1. if you cannot guarantee that both processors will be idle, do not enable the slp_en bit. note that setting slp_en to 1 is not required to support s1 in a dual- processor configuration. in going to the s3, s4, or s5 states, the system will appear to pass through the s1 state; thus, stpclk# and slp# are also used. during the s3, s4, and s5 states, both processors will lose power. upon exit from those states, the processors will have their power restored. 5.12.3 speed strapping for processor the ich5 directly sets the speed straps for the processor, saving the external logic that has been needed with prior pcisets. refer to processor specification for speed strapping definition. the ich5 performs the following to set the speed straps for the processor: 1. while pcirst# is active, the ich5 drives a20m#, ignne#, nmi, and intr high. 2. as soon as pwrok goes active, the ich5 reads the freq_strap field contents. 3. the next step depends on the power state being exited as described in table 57 . table 57. frequency strap behavior based on exit state state exiting intel ? ich5 s1 there is no processor reset, so no frequency strap logic is used. s3, s4, s5, or g3 based on pwrok going active, the intel ? ich5 deasserts pcirst#, and based on the value of the freq_strap field (d31:f0,offset d4), the ich5 drives the intended core frequency values on a20m#, ignne#, nmi, and intr. intel ? 82801eb ich5 / 82801er ich5r datasheet 145 functional description note: the freq_strap register is in the rtc well. the value in the register can be forced to 1111h via a pinstrap (ac_sdout signal), or the ich5 can automatically force the speed strapping to 1111h if the processor fails to boot. table 58. frequency strap bit mapping freq_strap bits [3:0] sets high/low level for the corresponding signal 3nmi 2intr 1 ignne# 0 a20m# figure 17. signal strapping processor si s intel ? ich5 a20m#, ignne#, intr, nmi host controller 4x 2 to 1 mux frequency strap register pcirst# pwrok init# cpurst# 146 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.13 power management (d31:f0) 5.13.1 features ? acpi power and thermal management support ? acpi 24-bit timer ? software initiated throttling of processor performance for thermal and power reduction ? hardware override to throttle processor performance if system too hot ? sci and smi# generation ? pci pme# signal for wake up from low-power states ? system sleeping state control ? acpi s1 state: stop grant or quickstart state (using stpclk# signal) halts processor?s instruction stream (only stpclk# active, and slp# optional) ?acpi s3 state ? suspend to ram (str) ? acpi s4 state ? suspend-to-disk (std) ? acpi g2/s5 state ? soft off (soff) ? power failure detection and recovery ? streamlined legacy power management support for apm-based systems 5.13.2 intel ? ich5 and system power states table 59 shows the power states defined for ich5-based platforms. the state names generally match the corresponding acpi states. table 59. general power states for systems using intel ? ich5 state/ substates legacy name / description g0/s0/c0 full on: processor operating. individual devices may be shut down to save power. the different processor operating levels are defined by cx states, as shown in table 60 . within the c0 state, the intel ? ich5 can throttle the stpclk# signal to reduce power consumption. the throttling can be initiated by software or by the thrm# input signal. g0/s0/c1 auto-halt: processor has executed a autohalt instruction and is not executing code. the processor snoops the bus and maintains cache coherency. g1/s1 stop-grant: ich5 also has the option to assert the cpuslp# signal to further reduce processor power consumption. note: the behavior for this state is slightly different when supporting ia64 processors. g1/s3 suspend-to-ram (str): the system context is maintained in system dram, but power is shut off to non-critical circuits. memory is retained, and refreshes continue. all clocks stop except rtc clock. g1/s4 suspend-to-disk (std): the context of the system is maintained on the disk. all power is then shut off to the system except for the logic required to resume. g2/s5 soft off (soff): system context is not maintained. all power is shut off except for the logic required to restart. a full boot is required when waking. g3 mechanical off (moff): system context not maintained. all power is shut off except for the rtc. no ?wake? events are possible, because the system does not have any power. this state occurs if the user removes the batteries, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the ?waking? logic. when system power returns, transition will depends on the state just prior to the entry to g3 and the afterg3 bit in the gen_pmcon3 register (d31:f0, offset a4). refer to table 66 for more details. intel ? 82801eb ich5 / 82801er ich5r datasheet 147 functional description table 60 shows the transitions rules among the various states. note that transitions among the various states may appear to temporarily transition through intermediate states. for example, in going from s0 to s1, it may appear to pass through the g0/s0 states. these intermediate transitions and states are not listed in the table. notes: 1. some wake events can be preserved through power failure. table 60. state transition rules for intel ? ich5 present state transition trigger next state g0/s0/c0 ? processor halt instruction ? slp_en bit set ? power button override ? mechanical off/power failure ?g0/s0/c1 ?g0/s0 ?g0/s0 ? g1/sx or g2/s5 state ?g2/s5 ?g3 g0/s0/c1 ? any enabled break event ? stpclk# goes active ? power button override ? power failure ?g0/s0/c0 ?g0/s0 ?g2/s5 ?g3 g1/s1, g1/s3, or g1/s4 ? any enabled wake event ? power button override ? power failure ?g0/s0/c0 ?g2/s5 ?g3 g2/s5 ? any enabled wake event ? power failure ? g0/s0/c0 ?g3 g3 ? power returns ? optional to go to s0/c0 (reboot) or g2/s5 (stay off until power button pressed or other wake event). (see note 1) 148 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.13.3 system power planes the system has several independent power planes, as described in table 61 . note that when a particular power plane is shut off, it should go to a 0 v level. s 5.13.4 intel ? ich5 power planes the ich5 power planes are previously defined in section 3.1 . although not specific power planes within the ich5, there are many interface signals that go to devices that may be powered down. these include: ? ide: ich5 can tri-state or drive low all ide output signals and shut off input buffers. ? usb: ich5 can tri-state usb output signals and shut off input buffers if usb wakeup is not desired ? ac ?97: ich5 can drive low the outputs and shut off inputs 5.13.5 smi#/sci generation on any smi# event taking place, ich5 asserts smi# to the processor, which causes it to enter smm space. smi# remains active until the eos bit is set. when the eos bit is set, smi# goes inactive for a minimum of 4 pciclk. if another smi event occurs, smi# is driven active again. the sci is a level-mode interrupt that is typically handled by an acpi-aware operating system. in non-apic systems (which is the default), the sci irq is routed to one of the 8259 interrupts (irq 9, 10, or 11). the 8259 interrupt controller must be programmed to level mode for that interrupt. in systems using the apic, the sci can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. the interrupt polarity changes depending on whether it is on an interrupt shareable with a pirq or not; ( see section 9.1.11 acpi control register for details. ) the interrupt remains asserted until all sci sources are removed. table 61. system power plane plane controlled by description cpu slp_s3# signal the slp_s3# signal can be used to cut the power to the processor completely. main slp_s3# signal when slp_s3# goes active, power can be shut off to any circuit not required to wake the system from the s3 state. since the s3 state requires that the memory context be preserved, power must be retained to the main memory. the processor, devices on the pci bus, lpc i/f downstream hub interface and agp will typically be shut off when the main power plane is shut, although there may be small subsections powered. memory slp_s4# signal when the slp_s4# goes active, power can be shut off to any circuit not required to wake the system from the s4. since the memory context does not need to be preserved in the s4 state, the power to the memory can also be shut down. device[n] gpio individual subsystems may have their own power plane. for example, gpio signals may be used to control the power to disk drives, audio amplifiers, or the display screen. intel ? 82801eb ich5 / 82801er ich5r datasheet 149 functional description table 62 shows which events can cause an smi# and sci. note that some events can be programmed to cause either an smi# or sci. the usage of the event for sci (instead of smi#) is typically associated with an acpi-based system. each smi# or sci source has a corresponding enable and status bit. table 62. causes of smi# and sci (sheet 1 of 2) cause sci smi additional enables where reported pme# yes yes pme_en=1 pme_sts pme_b0 (internal ehci controller) yes yes pme_b0_en=1 pme_b0_sts power button press yes yes pwrbtn_en=1 pwrbtn_sts rtc alarm yes yes rtc_en=1 rtc_sts ring indicate yes yes ri_en=1 ri_sts ac ?97 wakes yes yes ac97_en=1 ac97_sts usb#1 wakes yes yes usb1_en=1 usb1_sts usb#2 wakes yes yes usb2_en=1 usb2_sts usb#3 wakes yes yes usb3_en=1 usb3_sts usb#4 wakes yes yes usb4_en=1 usb4_sts thrm# pin active yes yes thrm_en=1 thrm_sts acpi timer overflow (2.34 sec.) yes yes tmrof_en=1 tmrof_sts any gpi yes yes gpi[x]_route=10 (sci) gpi[x]_route=01 (smi) gpe0[x]_en=1 gpi[x]_sts gpe0_sts tco sci logic yes no tcosci_en=1 tcosci_sts tco sci message from mch yes no none mchsci_sts tco smi logic no yes tco_en=1 tco_sts tco smi ? year 2000 rollover no yes none newcentury_sts tco smi ? tco timerout no yes none timeout tco smi ? os writes to tco_dat_in register no yes none os_tco_smi tco smi ? message from mch no yes none mchsmi_sts tco smi ? nmi occurred (and nmis mapped to smi) no yes nmi2smi_en=1 nmi2smi_sts tco smi ? intruder# signal goes active no yes intrd_sel=10 intrd_det tco smi ? change of the bioswp bit from 0 to 1 no yes bld=1 bioswr_sts tco smi ? write attempted to bios no yes bioswp=1 bioswr_sts bios_rls written to yes no gbl_en=1 gbl_sts gbl_rls written to no yes bios_en=1 bios_sts write to b2h register no yes none apm_sts periodic timer expires no yes periodic_en=1 periodic_sts 64 ms timer expires no yes swsmi_tmr_en=1 swsmi_tmr_sts 150 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description notes: 1. sci_en must be 1 to enable sci. sci_en must be 0 to enable smi. 2. sci can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in apic mode). 3. gbl_smi_en must be 1 to enable smi. 4. eos must be written to 1 to re-enable smi for the next 1. 5.13.6 dynamic processor clock control the ich5 has extensive control for dynamically starting and stopping system clocks. the clock control is used for transitions among the various s0/cx states, and processor throttling. each dynamic clock control method is described in this section. the various sleep states may also perform types of non-dynamic clock control. the ich5 supports the acpi c0 and c1 states. the dynamic processor clock control is handled using the following signals: ? stpclk#: used to halt processor instruction stream. the c1 state is entered based on the processor performing an auto halt instruction. a c1 state ends due to a break event. based on the break event, the ich5 returns the system to c0 state. enhanced usb legacy support event no yes legacy_usb2_en = 1 legacy_usb2_sts enhanced usb intel specific event no yes intel_usb2_en = 1 intel_usb2_sts uhci usb legacy logic no yes legacy_usb_en=1 legacy_usb_sts serial irq smi reported no yes none serirq_smi_sts device monitors match address in its range no yes dev[n]_trap_en=1 devmon_sts, dev[n]_trap_sts smbus host controller no yes smb_smi_en host controller enabled smbus host status reg. smbus slave smi message no yes none smbus_smi_sts smbus smbalert# signal active no yes none smbus_smi_sts smbus host notify message received no yes host_notify_intren smbus_smi_sts host_notify_sts access microcontroller 62h/66h no yes mcsmi_en mcsmi_sts slp_en bit written to 1 no yes smi_on_slp_en=1 smi_on_slp_en_sts table 62. causes of smi# and sci (sheet 2 of 2) cause sci smi additional enables where reported intel ? 82801eb ich5 / 82801er ich5r datasheet 151 functional description 5.13.6.1 throttling using stpclk# throttling is used to lower power consumption or reduce heat. the ich5 asserts stpclk# to throttle the processor clock. after a programmable time, the ich5 deasserts stpclk# and the processor appears to return to the c0 state. this allows the processor to operate at reduced average power, with a corresponding decrease in performance. two methods are included to start throttling: 1. software enables a timer with a programmable duty cycle. the duty cycle is set by the thtl_dty field and the throttling is enabled using the thtl_en field. this is known as manual throttling. the period is fixed to be in the non-audible range, due to the nature of switching power supplies. 2. a thermal override condition (thrm# signal active for >2 seconds) occurs that unconditionally forces throttling, independent of the thtl_en bit. the throttling due to thermal override has a separate duty cycle (thrm_dty) which may vary by field and system. the thermal override condition will end when thrm# goes inactive. throttling due to the thrm# signal has higher priority than the software initiated throttling. 5.13.6.2 transition rules among s0/cx and throttling states the following priority rules and assumptions apply among the various s0/cx and throttling states: ? entry to any s0/cx state is mutually exclusive with entry to any s1?s5 state. this is because the processor can only perform one register access at a time and sleep states have higher priority than thermal throttling. ? when the slp_en bit is set (system going to a sleep state (s1?s5), the thtl_en bit can be internally treated as being disabled (no throttling while going to sleep state). note that thermal throttling (based on thrm# signal) cannot be disabled in an s0 state. however, once the slp_en bit is set, the thermal throttling is shut off (since stpclk# will be active in s1?s5 states). ? level 2 c2 level 2 level 2 c2 level 2 c2 the host controller must post stop-grant cycles in such a way that the processor gets an indication of the end of the special cycle prior to the ich5 observing the stop-grant cycle. this ensures that the stpclk# signals stays active for a sufficient period after the processor observes the response phase. 5.13.7 sleep states 5.13.7.1 sleep state overview the ich5 directly supports different sleep states (s1?s5), which are entered by setting the slp_en bit, or due to a power button press. the entry to the sleep states are based on several assumptions: ? entry to a cx state is mutually exclusive with entry to a sleep state. this is because the processor can only perform one register access at a time. a request to sleep always has higher priority than throttling. ? prior to setting the slp_en bit, the software turns off processor-controlled throttling. note that thermal throttling cannot be disabled, but setting the slp_en bit disables thermal throttling (since s1?s5 sleep state has higher priority). ? the g3 state cannot be entered via any software mechanism. the g3 state indicates a complete loss of power. 152 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.13.7.2 initiating sleep state sleep states (s1?s5) are initiated by: ? masking interrupts, turning off all bus master enable bits, setting the desired type in the slp_typ field, and then setting the slp_en bit. the hardware then attempts to gracefully put the system into the corresponding sleep state. ? pressing the pwrbtn# signal for more than 4 seconds to cause a power button override event. in this case the transition to the s5 state is less graceful, since there are no dependencies on observing stop-grant cycles from the processor or on clocks other than the rtc clock. 5.13.7.3 exiting sleep states sleep states (s1?s5) are exited based on wake events. the wake events forces the system to a full on state (s0), although some non-critical subsystems might still be shut off and have to be brought back manually. for example, the hard disk may be shut off during a sleep state, and have to be enabled via a gpio pin before it can be used. upon exit from the ich5-controlled sleep states, the wak_sts bit is set. the possible causes of wake events (and their restrictions) are shown in table 64 . table 63. sleep types sleep type comment s1 intel ? ich5 asserts the stpclk# signal. it also has the option to assert cpuslp# signal. this lowers the processor?s power consumption. no snooping is possible in this state. s3 ich5 asserts slp_s3#. the slp_s3# signal controls the power to non-critical circuits. power is only retained to devices needed to wake from this sleeping state, as well as to the memory. s4 ich5 asserts slp_s3# and slp_s4#. the slp_s4# signal shuts off the power to the memory subsystem. only devices needed to wake from this state should be powered. s5 same power state as s4. ich5 asserts slp_s3#, slp_s4# and slp_s5#. intel ? 82801eb ich5 / 82801er ich5r datasheet 153 functional description notes: 1. this is a wake event from s5 only if the sleep state was entered by setting the slp_en and slp_typ bits via software. 2. if in the s5 state due to a powerbutton override, the possible wake events are due to power button, hard reset without cycling (see command type 3 in table 121 ), and hard reset system (see command type 4 in table 121 ). it is important to understand that the various gpis have different levels of functionality when used as wake events. the gpis that reside in the core power well can only generate wake events from an s1 state. also, only certain gpis are ?acpi compliant,? meaning that their status and enable bits reside in acpi i/o space. table 65 summarizes the use of gpis as wake events. the latency to exit the various sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the ich5 are insignificant. table 64. causes of wake events cause states can wake from how enabled rtc alarm s1 ? s5 (note 1) set rtc_en bit in pm1_en register power button s1 ? s5 always enabled as wake event gpi[0:n] s1 ? s5 (note 1) gpe0_en register usb s1 ? s5 set usb1_en, usb 2_en, usb3_en, and usb4_en bits in gpe0_en register lan s1 ? s5 will use pme#. wake enable set with lan logic. ri# s1 ? s5 (note 1) set ri_en bit in gpe0_en register ac97 s1 ? s5 set ac97_en bit in gpe0_en register primary pme# s1 ? s5 pme_b0_en bit in gpe0_en register secondary pme# s1 ? s5 (note 1) set pme_en bit in gpe0_en register. gst timeout s1m setting the gst timeout range to a value other than 00h. smbalert# s1 ? s5 always enabled as wake event smbus slave message s1 ? s5 wake/smi# command always enabled as a wake event. note: smbus slave message can wake the system from s1?s5, as well as from s5 due to power button override. smbus host notify message received s1 ? s5 host_notify_wken bit smbus slave command register. reported in the smb_wak_sts bit in the gpeo_sts register. pme_b0 (internal usb2.0 ehci controller) s1 ? s5 (note 1) set pme_b0_en bit in gpe0_en register. table 65. gpi wake events gpi power well wake from notes gpi[7:0] core s1 gpi[13:11], gpi8 resume s1?s5 acpi compliant 154 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.13.7.4 sx-g3-sx, handling power failures power failures can occur if the ac power is cut (a real power failure) or if the system is unplugged. in either case, pwrok and rsmrst# are assumed to go low. depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure. the after_g3 bit provides the ability to program whether or not the system should boot once power returns after a power loss event. if the policy is to not boot, the system remains in an s5 state (unless previously in s4). there are only three possible events that will wake the system after a power failure. 1. pwrbtn#: pwrbtn# is always enabled as a wake event. when rsmrst# is low (g3 state), the pwrbtn_sts bit is reset. when the ich5 exits g3 after power returns (rsmrst# goes high), the pwrbtn# signal is already high (because v cc -standby goes high before rsmrst# goes high) and the pwrbtn_sts bit is 0. 2. ri#: ri# does not have an internal pull-up. therefore, if this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. if this signal goes low (active), when power returns the ri_sts bit is set and the system interprets that as a wake event. 3. rtc alarm: the rtc_en bit is in the rtc well and is preserved after a power loss. like pwrbtn_sts the rtc_sts bit is cleared when rsmrst# goes low. the ich5 monitors both pwrok and rsmrst# to detect for power failures. if pwrok goes low, the pwrok_flr bit is set. if rsmrst# goes low, pwr_flr is set. note: although pme_en is in the rtc well, this signal cannot wake the system after a power loss. pme_en is cleared by rtcrst#, and pme_sts is cleared by rsmrst#. table 66. transitions due to power failure state at power failure afterg3_en bit transition when power returns s0, s1, s3 1 0 s5 s0 s4 1 0 s4 s0 s5 1 0 s5 s0 intel ? 82801eb ich5 / 82801er ich5r datasheet 155 functional description 5.13.8 thermal management the ich5 has mechanisms to assist with managing thermal problems in the system. 5.13.8.1 thrm# signal the thrm# signal is used as a status input for a thermal sensor. based on the thrm# signal going active, the ich5 generates an smi# or sci (depending on sci_en). if the thrm_pol bit is set low, when the thrm# signal goes low, the thrm_sts bit will be set. this is an indicator that the thermal threshold has been exceeded. if the thrm_en bit is set, then when thrm_sts goes active, either an smi# or sci will be generated (depending on the sci_en bit being set). the power management software (bios or acpi) can then take measures to start reducing the temperature. examples include shutting off unwanted subsystems, or halting the processor. by setting the thrm_pol bit to high, another smi# or sci can optionally be generated when the thrm# signal goes back high. this allows the software (bios or acpi) to turn off the cooling methods. note: thrm# assertion does not cause a tco event message in s3 or s4. the level of the signal is not reported in the heartbeat message. 5.13.8.2 thrm# initiated passive cooling if the thrm# signal remains active for some time greater than 2 seconds and the ich5 is in the s0/g0/c0 state, then the ich5 enters an auto-throttling mode, in which it provides a duty cycle on the stpclk# signal. this reduces the overall power consumption by the system, and should cool the system. the intended result of the cooling is that the thrm# signal should go back inactive. for all programmed values (001?111), thrm# going active results in stpclk# active for a minimum time of 12.5% and a maximum of 87.5%. the period is 1024 pci clocks. thus, the stpclk# signal can be active for as little as 128 pci clocks or as much as 896 pci clocks. the actual slowdown (and cooling) of the processor depends on the instruction stream, because the processor is allowed to finish the current instruction. furthermore, the ich5 waits for the stop-grant cycle before starting the count of the time the stpclk# signal is active. when thrm# goes inactive, the throttling stops. in case that the ich5 is already attempting throttling because the thtl_en bit is set, the duty cycle associated with the thrm# signal has higher priority. if the ich5 is in the s1?s5 states, then no throttling will be caused by the thrm# signal being active. 5.13.8.3 thrm# override software bit the force_thtl bit allows the bios to force passive cooling, just as if the thrm# signal had been active for 2 seconds. if this bit is set, the ich5 starts throttling using the ratio in the thrm_dty field. when this bit is cleared the ich5 stops throttling, unless the thrm# signal has been active for 2 seconds or if the thtl_en bit is set (indicating that acpi software is attempting throttling). 156 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.13.8.4 processor initiated passive cooling (via programmed duty cycle on stpclk#) using the thtl_en and thtl_dty bits, the ich5 can force a programmed duty cycle on the stpclk# signal. this reduces the effective instruction rate of the processor and cuts its power consumption and heat generation. 5.13.8.5 active cooling active cooling involves fans. the gpio signals from the ich5 can be used to turn on/off a fan. 5.13.9 event input signals and their usage the ich5 has various input signals that trigger specific events. this section describes those signals and how they should be used. 5.13.9.1 pwrbtn# (power button) the ich5 pwrbtn# signal operates as a ?fixed power button? as described in the advanced configuration and power interface, version 2.0b. pwrbtn# signal has a 16 ms de-bounce on the input. the state transition descriptions are included in table 67 . note that the transitions start as soon as the pwrbtn# is pressed (but after the debounce logic), and does not depend on when the power button is released. note: during the time that the slp_s4# signal is stretched for the minimum assertion width (if enabled), the power button is not a wake event. refer to power button override function section below for further detail. table 67. transitions due to power button present state event transition/action comment s0/cx pwrbtn# goes low smi# or sci generated (depending on sci_en) software typically initiates a sleep state. s1?s5 pwrbtn# goes low wake event. transitions to s0 state. standard wakeup g3 pwrbtn# pressed none no effect since no power. not latched nor detected. s0?s4 pwrbtn# held low for at least 4 consecutive seconds unconditional transition to s5 state. no dependence on processor (e.g., stop-grant cycles) or any other subsystem. intel ? 82801eb ich5 / 82801er ich5r datasheet 157 functional description power button override function if pwrbtn# is observed active for at least four consecutive seconds, the state machine should unconditionally transition to the g2/s5 state, regardless of present state (s0?s4). in this case, the transition to the g2/s5 state should not depend on any particular response from the processor (e.g., a stop-grant cycle), nor any similar dependency from any other subsystem. new: a power button override forces a transition to s5, even if pwrok is not active . the pwrbtn# status is readable to check if the button is currently being pressed or has been released. the status is taken after the de-bounce, and is readable via the pwrbtn_lvl bit. note: the 4-second pwrbtn# assertion should only be used if a system lock-up has occurred. the 4-second timer starts counting when the ich5 is in a s0 state. if the pwrbtn# signal is asserted and held active when the system is in a suspend state (s1?s5), the assertion causes a wake event. once the system has resumed to the s0 state, the 4-second timer starts. note: during the time that the slp_s4# signal is stretched for the minimum assertion width (if enabled by d31:f0:a4h bit 3), the power button is not a wake event. as a result, it is conceivable that the user will press and continue to hold the power button waiting for the system to awake. since a 4-second press of the power button is already defined as an unconditional power down, the power button timer will be forced to inactive while the power-cycle timer is in progress. once the power-cycle timer has expired, the power button awakes the system. once the minimum slp_s4# power cycle expires, the power button must be pressed for another 4 to 5 seconds to create the override condition to s5. sleep button the advanced configuration and power interface, version 2.0b defines an optional sleep button. it differs from the power button in that it only is a request to go from s0 to s1?s4 (not s5). also, in an s5 state, the power button can wake the system, but the sleep button cannot. although the ich5 does not include a specific signal designated as a sleep button, one of the gpio signals can be used to create a ?control method? sleep button. see the advanced configuration and power interface, version 2.0b for implementation details. 5.13.9.2 ri# (ring indicator) the ring indicator can cause a wake event (if enabled) from the s1?s5 states. table 68 shows when the wake event is generated or ignored in different states. if in the g0/s0/cx states, the ich5 generates an interrupt based on ri# active, and the interrupt will be set up as a break event. note: filtering/debounce on ri# will not be done in ich5. can be in modem or external. table 68. transitions due to ri# signal present state event ri_en event s0 ri# active x ignored s1?s5 ri# active 0 1 ignored wake event 158 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.13.9.3 pme# (pci power management event) the pme# signal comes from a pci device to request that the system be restarted. the pme# signal can generate an smi#, sci, or optionally a wake event. the event occurs when the pme# signal goes from high to low. no event is caused when it goes from low to high. in the ehci controller, there is an internal pme_b0 bit. this is separate from the external pme# signal and can cause the same effect. 5.13.9.4 sys_reset# signal sys_reset# on the ich5 is used to eliminate extra glue logic on the board. before the addition of this pin, a system reset was activated by external glue forcing the pwrok signal low after the reset button was pressed. this pin eliminates the need for that glue. when the sys_reset# pin is detected as active after the 16 ms debounce logic, the ich5 attempts to perform a ?graceful? reset, by waiting up to 25 ms for the smbus to go idle. if the smbus is idle when the pin is detected active, the reset occurs immediately; otherwise, the counter starts. if at any point during the count the smbus goes idle the reset occurs. if, however, the counter expires and the smbus is still active, a reset is forced upon the system even though activity is still occurring. once the reset is asserted, it remains asserted for approximately 1 ms regardless of whether the sysreset# input remains asserted or not. it cannot occur again until sys_reset# has been detected inactive after the debounce logic, and the system is back to a full s0 state with pcirst# inactive. 5.13.9.5 thrmtrip# signal if thrmtrip# goes active, the processor is indicating an overheat condition, and the ich5 immediately transitions to an s5 state. however, since the processor has overheated, it does not respond to the ich5?s stpclk# pin with a stop grant special cycle. therefore, the ich5 does not wait for one. immediately upon seeing thrmtrip# low, the ich5 initiates a transition to the s5 state, drive slp_s3#, slp_s4#, slp_s5# low, and set the cts bit. the transition looks like a power button override. it is extremely important that when a thrmtrip# event occurs, the ich5 power down immediately without following the normal s0 -> s5 path. this path may be taken in parallel, but ich5 must immediately enter a power down state. it does this by driving slp_s3#, slp_s4#, and slp_s5# immediately after sampling thrmtrip# active. if the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the ich5, are no longer executing cycles properly. therefore, if thrmtrip# fires, and the ich5 is relying on state machine logic to perform the power down, the state machine may not be working, and the system will not power down. the ich5 follows this flow for thrmtrip#. 1. at boot (pcirst# low), thrmtrip# ignored. 2. after power-up (pcirst# high), if thrmtrip# sampled active, slp_s3#, slp_s4#, and slp_s5# fire, and normal sequence of sleep machine starts. 3. until sleep machine enters the s5 state, slp_s3#, slp_s4#, and slp_s5# stay active, even if thrmtrip# is now inactive. this is the equivalent of ?latching? the thermal trip event. 4. if s5 state reached, go to step #1, otherwise stay here. if the ich5 never reaches s5, the ich5 does not reboot until power is cycled. intel ? 82801eb ich5 / 82801er ich5r datasheet 159 functional description 5.13.10 alt access mode before entering a low power state, several registers from powered down parts may need to be saved. in the majority of cases, this is not an issue, as registers have read and write paths. however, several of the isa compatible registers are either read only or write only. to get data out of write-only registers, and to restore data into read-only registers, the ich5 implements an alt access mode. if the alt access mode is entered and exited after reading the registers of the ich5 timer (8254), the timer starts counting faster (13.5 ms). the following steps listed below can cause problems: 1. bios enters alt access mode for reading the ich5 timer related registers. 2. bios exits alt access mode. 3. bios continues through the execution of other needed steps and passes control to the os. after getting control in step #3, if the os does not reprogram the system timer again, the timer ticks may be happening faster than expected. for example dos and its associated software assume that the system timer is running at 54.6 ms and as a result the time-outs in the software may be happening faster than expected. operating systems (e.g., microsoft windows* 98, windows* 2000, and windows nt*) reprogram the system timer and therefore do not encounter this problem. for some other loss (e.g., microsoft ms-dos*) the bios should restore the timer back to 54.6 ms before passing control to the os. if the bios is entering alt access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from alt access mode. 5.13.10.1 write only registers with read paths in alt access mode the registers described in table 69 have read paths in alt access mode. the access number field in the table indicates which register will be returned per access to that port. table 69. write only registers with read paths in alt access mode (sheet 1 of 2) restore data restore data i/o addr # of rds access data i/o addr # of rds access data 00h 2 1 dma chan 0 base address low byte 40h 7 1 timer counter 0 status, bits [5:0] 2 dma chan 0 base address high byte 2 timer counter 0 base count low byte 01h 2 1 dma chan 0 base count low byte 3 timer counter 0 base count high byte 2 dma chan 0 base count high byte 4 timer counter 1 base count low byte 02h 2 1 dma chan 1 base address low byte 5 timer counter 1 base count high byte 2 dma chan 1 base address high byte 6 timer counter 2 base count low byte 03h 2 1 dma chan 1 base count low byte 7 timer counter 2 base count high byte 2 dma chan 1 base count high byte 41h 1 timer counter 1 status, bits [5:0] 160 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description notes: 1. the ocw1 register must be read before entering alt access mode. 2. bits 5, 3, 1, and 0 return 0. 04h 2 1 dma chan 2 base address low byte 42h 1 timer counter 2 status, bits [5:0] 2 dma chan 2 base address high byte 70h 1 bit 7 = nmi enable, bits [6:0] = rtc address 05h 2 1 dma chan 2 base count low byte c4h 2 1 dma chan 5 base address low byte 2 dma chan 2 base count high byte 2 dma chan 5 base address high byte 06h 2 1 dma chan 3 base address low byte c6h 2 1 dma chan 5 base count low byte 2 dma chan 3 base address high byte 2 dma chan 5 base count high byte 07h 2 1 dma chan 3 base count low byte c8h 2 1 dma chan 6 base address low byte 2 dma chan 3 base count high byte 2 dma chan 6 base address high byte 08h 6 1 dma chan 0?3 command 2 cah 2 1 dma chan 6 base count low byte 2 dma chan 0?3 request 2 dma chan 6 base count high byte 3 dma chan 0 mode: bits(1:0) = 00 cch 2 1 dma chan 7 base address low byte 4 dma chan 1 mode: bits(1:0) = 01 2 dma chan 7 base address high byte 5 dma chan 2 mode: bits(1:0) = 10 ceh 2 1 dma chan 7 base count low byte 6 dma chan 3 mode: bits(1:0) = 11. 2 dma chan 7 base count high byte 20h 12 1 pic icw2 of master controller d0h 6 1 dma chan 4?7 command 2 2 pic icw3 of master controller 2 dma chan 4?7 request 3 pic icw4 of master controller 3 dma chan 4 mode: bits(1:0) = 00 4 pic ocw1 of master controller 1 4 dma chan 5 mode: bits(1:0) = 01 5 pic ocw2 of master controller 5 dma chan 6 mode: bits(1:0) = 10 6 pic ocw3 of master controller 6 dma chan 7 mode: bits(1:0) = 11. 7 pic icw2 of slave controller 8 pic icw3 of slave controller 9 pic icw4 of slave controller 10 pic ocw1 of slave controller 1 11 pic ocw2 of slave controller 12 pic ocw3 of slave controller table 69. write only registers with read paths in alt access mode (sheet 2 of 2) restore data restore data i/o addr # of rds access data i/o addr # of rds access data intel ? 82801eb ich5 / 82801er ich5r datasheet 161 functional description 5.13.10.2 pic reserved bits many bits within the pic are reserved, and must have certain values written in order for the pic to operate properly. therefore, there is no need to return these values in alt access mode. when reading pic registers from 20h and a0h, the reserved bits shall return the values listed in table 70 . 5.13.10.3 read only registers with write paths in alt access mode the registers described in table 71 have write paths to them in alt access mode. software restores these values after returning from a powered down state. these registers must be handled special by software. when in normal mode, writing to the base address/count register also writes to the current address/count register. therefore, the base address/count must be written first, then the part is put into alt access mode and the current address/count register is written. 5.13.11 system power supplies, planes, and signals 5.13.11.1 power plane control with slp_s3#, slp_s4# and slp_s5# the slp_s3# output signal can be used to cut power to the system core supply, since it only goes active for the str state (typically mapped to acpi s3). power must be maintained to the ich5 resume well, and to any other circuits that need to generate wake signals from the str state. cutting power to the core may be done via the power supply, or by external fets to the motherboard. the slp_s4# or slp_s5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. cutting power to the memory may be done via the power supply, or by external fets to the motherboard. table 70. pic reserved bits return values pic reserved bits value returned icw2(2:0) 000 icw4(7:5) 000 icw4(3:2) 00 icw4(0) 0 ocw2(4:3) 00 ocw3(7) 0 ocw3(5) reflects bit 6 ocw3(4:3) 01 table 71. register write accesses in alt access mode i/o address register write value 08h dma status register for channels 0?3. d0h dma status register for channels 4?7. 162 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.13.11.2 slp_s4# and suspend-to-ram sequencing the system memory suspend voltage regulator is controlled by the glue logic ?latched_backfeed_cut? signal. this signal should be generated using the slp_s4# signal rather than the slp_s5# signal, even if the platform does not support s4 sleep state. the slp_s4# logic in the ich5 provides a mechanism to fully cycle the power to the dram and/or detect if the power is not cycled for a minimum time. note: to utilize the minimum dram power-down feature that is enabled by the slp_s4# assertion stretch enable bit (d31:f0:a4h bit 3), the dram power must be controlled by the slp_s4# signal. 5.13.11.3 pwrok signal the pwrok input should go active based on the core supply voltages becoming valid. pwrok should go active no sooner than 100 ms after vcc3_3 and vcc1_5 have reached their nominal values. note: 1. sysreset# is recommended for implementing the system reset button. this saves external logic that is needed if the pwrok input is used. additionally, it allows for better handling of the smbus and processor resets, and avoids improperly reporting power failures. 2. if the pwrok input is used to implement the system reset button, the ich5 does not provide any mechanism to limit the amount of time that the processor is held in reset. the platform must externally guarantee that maximum reset assertion specs are met. 3. if a design has an active-low reset button electrically and?d with the pwrok signal from the power supply and the processor?s voltage regulator module the ich5 pwrok_flr bit will be set. the ich5 treats this internally as if the rsmrst# signal had gone active. however, it is not treated as a full power failure. if pwrok goes inactive and then active (but rsmrst# stays high), then the ich5 reboots (regardless of the state of the afterg3 bit). if the rsmrst# signal also goes low before pwrok goes high, then this is a full power failure, and the reboot policy is controlled by the afterg3 bit. 4. pwrok and rsmrst# are sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by the ich5. 5. in the case of true pwrok failure, pwrok goes low first before the vrmpwrgd. 5.13.11.4 vrmpwrgd signal this signal is connected to the processor?s vrm and is internally and?d with the pwrok signal that comes from the system power supply. this saves the external and gate found in desktop systems. intel ? 82801eb ich5 / 82801er ich5r datasheet 163 functional description 5.13.11.5 controlling leakage and power consumption during low-power states to control leakage in the system, various signals tri-state or go low during some low-power states. general principles: ? all signals going to powered down planes (either internally or externally) must be either tri-stated or driven low. ? signals with pull-up resistors should not be low during low-power states. this is to avoid the power consumed in the pull-up resistor. ? buses should be halted (and held) in a known state to avoid a floating input (perhaps to some other device). floating inputs can cause extra power consumption. based on the above principles, the following measures are taken: ? during s3 (str), all signals attached to powered down planes are tri-stated or driven low. 5.13.12 clock generators the clock generator is expected to provide the frequencies shown in table 72 . table 72. intel ? ich5 clock inputs clock domain frequency source usage clk100 100 mhz differential main clock generator used by sata controller. stopped in s3 ~ s5 based on slp_s3# assertion. clk66 66 mhz main clock generator should be running in all cx states. stopped in s3 ~ s5 based on slp_s3# assertion. pciclk 33 mhz main clock generator free-running pci clock to ich5. stopped in s3 ~ s5 based on slp_s3# assertion. clk48 48 mhz main clock generator used by usb controllers. stopped in s3 ~ s5 based on slp_s3# assertion. clk14 14.318 mhz main clock generator used by acpi timers. stopped in s3 ~ s5 based on slp_s3# assertion. ac_bit_clk 12.288 mhz ac ?97 codec ac-link. control policy is determined by the clock source. lan_clk 0.8 to 50 mhz lan connect lan connect link. control policy is determined by the clock source. 164 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.13.13 legacy power management theory of operation instead of relying on acpi software, legacy power management uses bios and various hardware mechanisms. the scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. however, the os is assumed to be at least apm enabled. without apm calls, there is no quick way to know when the system is idle between keystrokes. the ich5 does not support burst modes. 5.13.13.1 apm power management the ich5 has a timer that, when enabled by the 1min_en bit in the smi control and enable register, generates an smi# once per minute. the smi handler can check for system activity by reading the devact_sts register. if none of the system bits are set, the smi handler can increment a software counter. when the counter reaches a sufficient number of consecutive minutes with no activity, the smi handler can then put the system into a lower power state. if there is activity, various bits in the devact_sts register will be set. software clears the bits by writing a 1 to the bit position. the devact_sts register allows for monitoring various internal devices, or super i/o devices (sp, pp, fdc) on lpc or pci, keyboard controller accesses, or audio functions on lpc or pci. other pci activity can be monitored by checking the pci interrupts. 5.14 system management (d31:f0) the ich5 provides various functions to make a system easier to manage and to lower the total cost of ownership (tco) of the system. in addition, ich5 provides integrated asf management support. features and functions can be augmented via external a/d converters and gpio, as well as an external microcontroller. the following features and functions are supported by the ich5: ? processor present detection ? detects if processor fails to fetch the first instruction after reset ? various error detection (such as ecc errors) indicated by host controller ? can generate smi#, sci, serr, nmi, or tco interrupt ? intruder detect input ? can generate tco interrupt or smi# when the system cover is removed ? intruder# allowed to go active in any power state, including g3 ? detection of bad flash bios programming ? detects if data on first read is ffh (indicates unprogrammed flash bios) ? ability to hide a pci device ? allows software to hide a pci device in terms of configuration space through the use of a device hide register (see section 8.1.26 ) ? integrated asf management support note: voltage id from the processor can be read via gpi signals. intel ? 82801eb ich5 / 82801er ich5r datasheet 165 functional description 5.14.1 theory of operation the system management functions are designed to allow the system to diagnose failing subsystems. the intent of this logic is that some of the system management functionality be provided without the aid of an external microcontroller. 5.14.1.1 detecting a system lockup when the processor is reset, it is expected to fetch its first instruction. if the processor fails to fetch the first instruction after reset, the tco timer times out twice and the ich5 asserts pcirst#. 5.14.1.2 handling an intruder the ich5 has an input signal, intruder#, that can be attached to a switch that is activated by the system?s case being open. this input has a two rtc clock debounce. if intruder# goes active (after the debouncer), this will set the intrd_det bit in the tco_sts register. the intrd_sel bits in the tco_cnt register can enable the ich5 to cause an smi# or interrupt. the bios or interrupt handler can then cause a transition to the s5 state by writing to the slp_en bit. the software can also directly read the status of the intruder# signal (high or low) by clearing and then reading the intrd_det bit. this allows the signal to be used as a gpi if the intruder function is not required. if the intruder# signal goes inactive some point after the intrd_det bit is written as a 1, then the intrd_det signal will go to a 0 when intruder# input signal goes inactive. note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. note: the intrd_det bit resides in the ich5?s rtc well, and is set and cleared synchronously with the rtc clock. thus, when software attempts to clear intrd_det (by writing a 1 to the bit location) there may be as much as two rtc clocks (about 65 s) delay before the bit is actually cleared. also, the intruder# signal should be asserted for a minimum of 1 ms to guarantee that the intrd_det bit will be set. note: if the intruder# signal is still active when software attempts to clear the intrd_det bit, the bit remains set and the smi is generated again immediately. the smi handler can clear the intrd_sel bits to avoid further smis. however, if the intruder# signal goes inactive and then active again, there will not be further smis, since the intrd_sel bits would select that no smi# be generated. 5.14.1.3 detecting improper flash bios programming the ich5 can detect the case where the flash bios is not programmed. this results in the first instruction fetched to have a value of ffh. if this occurs, the ich5 sets the bad_bios bit, which can then be reported via the heartbeat and event reporting using an external, alert on lan enabled lan controller (see section 5.14.2 ). 166 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.14.1.4 handling an ecc error or other memory error the host controller provides a message to indicate that it would like to cause an smi#, sci, serr#, or nmi. the software must check the host controller as to the exact cause of the error. 5.14.2 heartbeat and event reporting via smbus the ich5 integrated lan controller supports asf heartbeat and event reporting functionality when used with the 82562em or 82562ez platform lan connect component. this allows the integrated lan controller to report messages to a network management console without the aid of the system processor. this is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state. all heartbeat and event messages are sent on the smbus interface. this allows an external lan controller to act upon these messages if the internal lan controller is not used. the basic scheme is for the ich5 integrated lan controller to send a prepared ethernet message to a network management console. the prepared message is stored in the non-volatile eeprom that is connected to the ich5. messages are sent by the lan controller either because a specific event has occurred, or they are sent periodically (also known as a heartbeat). the event and heartbeat messages have the exact same format. the event messages are sent based on events occurring. the heartbeat messages are sent every 30 to 32 seconds. when an event occurs, the ich5 sends a new message and increments the seq[3:0] field. for heartbeat messages, the sequence number does not increment. the following rules/steps apply if the system is in a g0 state and the policy is for the ich5 to reboot the system after a hardware lockup: 1. on detecting the lockup, the second_to_sts bit is set. the ich5 may send up to 1 event message to the lan controller. the ich5 then attempts to reboot the processor. 2. if the reboot at step 1 is successful then the bios should clear the second_to_sts bit. this prevents any further heartbeats from being sent. the bios may then perform addition recovery/boot steps. (see note 2, below.) 3. if the reboot attempt in step 1 is not successful, the timer will timeout a third time. at this point the system has locked up and was unsuccessful in rebooting. the ich5 does not attempt to automatically reboot again. the ich5 starts sending a message every heartbeat period (30?32 seconds). the heartbeats continue until some external intervention occurs (reset, power failure, etc.). 4. after step 3 (unsuccessful reboot after third timeout), if the user does a power button override, the system goes to an s5 state. the ich5 continues sending the messages every heartbeat period. 5. after step 4 (power button override after unsuccessful reboot) if the user presses the power button again, the system should wake to an s0 state and the processor should start executing the bios. 6. if step 5 (power button press) is successful in waking the system, the ich5 continues sending messages every heartbeat period until the bios clears the second_to_sts bit. (see note 2) intel ? 82801eb ich5 / 82801er ich5r datasheet 167 functional description 7. if step 5 (power button press) is unsuccessful in waking the system, the ich5 continues sending a message every heartbeat period. the ich5 does not attempt to automatically reboot again. the ich5 starts sending a message every heartbeat period (30?32 seconds). the heartbeats continue until some external intervention occurs (reset, power failure, etc.). (see note 3) 8. after step 3 (unsuccessful reboot after third timeout), if a reset is attempted (using a button that pulses pwrok low or via the message on the smbus slave i/f), the ich5 attempts to reset the system. 9. after step 8 (reset attempt) if the reset is successful, the bios is run. the ich5 continues sending a message every heartbeat period until the bios clears the second_to_sts bit. (see note 2) 10. after step 8 (reset attempt), if the reset is unsuccessful, the ich5 continues sending a message every heartbeat period. the ich5 does not attempt to reboot the system again without external intervention. (see note 3) the following rules/steps apply if the system is in a g0 state and the policy is for the ich5 to not reboot the system after a hardware lockup. 1. on detecting the lockup the second_to_sts bit is set. the ich5 sends a message with the watchdog (wd) event status bit set (and any other bits that must also be set). this message is sent as soon as the lockup is detected, and is sent with the next (incremented) sequence number. 2. after step 1, the ich5 sends a message every heartbeat period until some external intervention occurs. 3. rules/steps 4?10 apply if no user intervention (resets, power button presses, smbus reset messages) occur after a third timeout of the watchdog timer. if the intervention occurs before the third timeout, then jump to rule/step11. 4. after step 3 (third timeout), if the user does a power button override, the system goes to an s5 state. the ich5 continues sending heartbeats at this point. 5. after step 4 (power button override), if the user presses the power button again, the system should wake to an s0 state and the processor should start executing the bios. 6. if step 5 (power button press) is successful in waking the system, the ich5 continues sending heartbeats until the bios clears the second_to_sts bit. (see note 2) 7. if step 5 (power button press) is unsuccessful in waking the system, the ich5 continues sending heartbeats. the ich5 does not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). (see note 3) 8. after step 3 (3 rd timeout), if a reset is attempted (using a button that pulses pwrok low or via the message on the smbus slave i/f), the ich5 attempts to reset the system. 9. if step 8 (reset attempt) is successful, the bios is run. the ich5 continues sending heartbeats until the bios clears the second_to_sts bit. (see note 2) 10. if step 8 (reset attempt), is unsuccessful, the ich5 continues sending heartbeats. the ich5 does not attempt to reboot the system again without external intervention. note: a system that has locked up and can not be restarted with power button press is probably broken (bad power supply, short circuit on some bus, etc.) 11. this and the following rules/steps apply if the user intervention (power button press, reset, smbus message, etc.) occur prior to the third timeout of the watchdog timer. 168 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 12. after step 1 (second timeout), if the user does a power button override, the system goes to an s5 state. the ich5 continues sending heartbeats at this point. 13. after step 12 (power button override), if the user presses the power button again, the system should wake to an s0 state and the processor should start executing the bios. 14. if step 13 (power button press) is successful in waking the system, the ich5 continues sending heartbeats until the bios clears the second_to_sts bit. (see note 2) 15. if step 13 (power button press) is unsuccessful in waking the system, the ich5 continues sending heartbeats. the ich5 does not attempt to reboot the system again until some external intervention occurs (reset, power failure, etc.). (see note 3) 16. after step 1 (second timeout), if a reset is attempted (using a button that pulses pwrok low or via the message on the smbus slave i/f), the ich5 attempts to reset the system. 17. if step 16 (reset attempt) is successful, the bios is run. the ich5 continues sending heartbeats until the bios clears the second_to_sts bit. (see note 2) 18. if step 16 (reset attempt), is unsuccessful, the ich5 continues sending heartbeats. the ich5 does not attempt to reboot the system again without external intervention. (see note 3) if the system is in a g1 (s1?s4) state, the ich5 sends a heartbeat message every 30?32 seconds. if an event occurs prior to the system being shutdown, the ich5 immediately sends an event message with the next incremented sequence number. after the event message, the ich5 resumes sending heartbeat messages. note: notes for previous two numbered lists. 1. normally, the ich5 does not send heartbeat messages while in the g0 state (except in the case of a lockup). however, if a hardware event (or heartbeat) occurs just as the system is transitioning into a g0 state, the hardware continues to send the message even though the system is in a g0 state (and the status bits may indicate this). these messages are sent via the smbus. the ich5 abides by the smbus rules associated with collision detection. it delays starting a message until the bus is idle, and detects collisions. if a collision is detected the ich5 waits until the bus is idle, and tries again. 2. warning: it is important the bios clears the second_to_sts bit, as the alerts interfere with the lan device driver from working properly. the alerts reset part of the lan controller and would prevent an os?s device driver from sending or receiving some messages. 3. a system that has locked up and can not be restarted with power button press is assumed to have broken hardware (bad power supply, short circuit on some bus, etc.), and is beyond ich5?s recovery mechanisms. 4. a spurious alert could occur in the following sequence: ? the processor has initiated an alert using the send_now bit ? during the alert, the thrm#, intruder# or gpi11 changes state ? the system then goes to a non-s0 state. intel ? 82801eb ich5 / 82801er ich5r datasheet 169 functional description once the system transitions to the non-s0 state, it may send a single alert with an incremental sequence number. 5. an inaccurate alert message can be generated in the following scenario ? the system successfully boots after a second watchdog timeout occurs. ? pwrok goes low (typically due to a reset button press) or a power button override occurs (before the second_to_sts bit is cleared). ? an alert message indicating that the processor is missing or locked up is generated with a new sequence number. table 73 shows the data included in the alert on lan messages. table 73. heartbeat message data field comment cover tamper status 1 = this bit is set if the intruder detect bit is set (intrd_det). temp event status 1 = this bit is set if the intel ? ich5 therm# input signal is asserted. processor missing event status 1 = this bit is set if the processor failed to fetch its first instruction. tco timer event status 1 = this bit is set when the tco timer expires. software event status 1 = this bit is set when software writes a 1 to the send_now bit. unprogrammed flash bios event status 1 = first bios fetch returned a value of ffh, indicating that the flash bios has not yet been programmed (still erased). gpio status 1 = this bit is set when gpio11 signal is high. 0 = this bit is cleared when gpio11 signal is low. an event message is triggered on an transition of gpio11. seq[3:0] this is a sequence number. it initially is 0, and increments each time the ich5 sends a new message. upon reaching 1111, the seq uence number rolls over to 0000. msb (seq3) sent first. system power state 00 = g0, 01 = g1, 10 = g2, 11 = pre-boot. msb sent first message1 will be the same as the message1 register. msb sent first. message2 will be the same as the message2 register. msb sent first. wdstatus will be the same as the wdstatus register. msb sent first. 170 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.15 general purpose i/o 5.15.1 gpio mapping table 74. gpio implementation (sheet 1 of 4) gpio type alternate function (note 1) power well tolerant notes gpi0 input only reqa# core 5.0 v ? gpio_use_sel bit 0 enables req/ gnta# pair. ? input active status read from gpe0_sts register bit 0. ? input active high/low set through gpi_inv register bit 0. gpi1 input only reqb# or req5# core 5.0 v ? gpio_use_sel bit 1 enables req/ gntb# pair (see note 4). ? input active status read from gpe0_sts register bit 1. ? input active high/low set through gpi_inv register bit 1. gpi[5:2] input only pirq[e:h]# core 5.0 v ? gpio_use_sel bits [2:5] enable pirq[e:h]#. ? input active status read from gpe0_sts reg. bits [2:5]. ? input active high/low set through gpi_inv reg. bit [2:5]. gpi6 input only n/a core 5.0 v ? input active status read from gpe0_sts register bit 6. ? input active high/low set through gpi_inv register bit 6. gpi7 input only unmuxed core 5.0 v ? input active status read from gpe0_sts register bit 7. ? input active high/low set through gpi_inv register bit 7 gpi8 input only unmuxed resume 3.3 v ? input active status read from gpe0_sts register bit 8. ? input active high/low set through gpi_inv register bit 8. gpio[10:9] input only oc[4:5]# resume 3.3 v ? gpio_use_sel bits [9:10] enable oc[4:5]#. ? input active status read from gpe0_sts register bits [9:10]. ? input active high/low set through gpi_inv register bits [9:10]. gpi11 input only smbalert# resume 3.3 v ? gpio_use_sel bit 11 enables smbalert# ? input active status read from gpe0_sts register bit 11. ? input active high/low set through gpi_inv register bit 11. intel ? 82801eb ich5 / 82801er ich5r datasheet 171 functional description gpi12 input only unmuxed resume 3.3 v ? input active status read from gpe0_sts register bit 12. ? input active high/low set through gpi_inv register bit 12. gpi13 input only unmuxed resume 3.3 v ? input active status read from gpe0_sts register bit 13. ? input active high/low set through gpi_inv register bit 13. gpio[15:14] input only oc[6:7]# resume 3.3 v ? gpio_use_sel bits [14:15] enable oc[6:7]#. ? input active status read from gpe0_sts register bits [14:15]. ? input active high/low set through gpi_inv register bits[14:15]. gpo16 output only gnta# core 3.3 v ? output controlled via gp_lvl register bit 16. ttl driver output gpo17 output only gntb# or gnt5# core 3.3 v ? output controlled via gp_lvl register bit 17. ? ttl driver output gpo18 output only n/a core 3.3 v ? blink enabled via gpo_blink register (d31:f0: offset gpiobase+18h) bits [19:18] ? gpo18 will blink by default immediately after reset. ? output controlled via gp_lvl register (d31:f0: offset gpiobase+0ch) bits [18:19]. ? ttl driver output gpo19 output only n/a core 3.3 v ? blink enabled via gpo_blink register (d31:f0: offset gpiobase+18h) bits [19:18] ? output controlled via gp_lvl register (d31:f0: offset gpiobase+0ch) bits [18:19]. ? ttl driver output gpo20 output only n/a core 3.3 v ? output controlled via gp_lvl register bit 20. ? ttl driver output gpio21 output only n/a core 3.3 v ? output controlled via gp_lvl register bit 21. ? ttl driver output gpio22 output only n/a core 3.3 v ? output controlled via gp_lvl register bit 22. ? open-drain output gpio23 output only n/a core 3.3 v ? output controlled via gp_lvl register bit 23. ? ttl driver output table 74. gpio implementation (sheet 2 of 4) gpio type alternate function (note 1) power well tolerant notes 172 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description gpio24 i/o n/a resume 3.3 v ? input active status read from gp_lvl register bit 24. ? output controlled via gp_lvl register bit 24. ? ttl driver output gpio25 i/o unmuxed resume 3.3 v ? blink enabled via gpo_blink register (d31:f0: offset gpiobase+18h) bit 25 ? input active status read from gp_lvl register bit 25 ? output controlled via gp_lvl register bit 25. ? ttl driver output gpio26 n/a n/a n/a ? not implemented gpio[28:27] i/o unmuxed resume 3.3 v ? blink enabled via gpo_blink register (d31:f0: offset gpiobase+18h) bits [28:27] ? input active status read from gp_lvl register bits [27:28] ? output controlled via gp_lvl register bits [27:28] ? ttl driver output gpio[31:29] n/a n/a n/a ? not implemented gpio32 i/o unmuxed core 3.3 v ? input active status read from gp_lvl register bit 32 ? output controlled via gp_lvl2 register bit 32 ? ttl driver output gpio33 n/a n/a n/a ? not implemented gpio34 i/o unmuxed core 3.3 v ? input active status read from gp_lvl register bit 34 ? output controlled via gp_lvl2 register bit 34 ? ttl driver output gpio[39:35] n/a n/a n/a ? not implemented gpio40 input only req4# core 3.3 v ? gpio_use_sel bit 40 enables req/ gnt4# pair. ? input active status read from gp_lvl2 register bit 40 ? ttl driver output gpio41 input only ldrq1# core 3.3 v ? gpio_use_sel bit 41 enables ldrq1#. input active status read from gp_lvl2 register bit 41 ? ttl driver output table 74. gpio implementation (sheet 3 of 4) gpio type alternate function (note 1) power well tolerant notes intel ? 82801eb ich5 / 82801er ich5r datasheet 173 functional description notes: 1. all gpios default to their alternate function. 2. all inputs are sticky. the status bit remains set as long as the input was asserted for two clocks. gpis are sampled on pci clocks in s0/s1. gpis are sampled on rtc clocks in s3/s4/s5. 3. gpio[0:7] are 5 v tolerant, and all gpis can be routed to cause an sci or smi#. 4. if gpio_use_sel bit 1 is set to 1 and gen_cnt bit 25 is also set to 1 then req/gnt5# is enabled. see section 9.1.22 . 5.15.2 power wells some gpios exist in the resume power plane. care must be taken to make sure gpio signals are not driven high into powered-down planes. some ich5 gpios may be connected to pins on devices that exist in the core well. if these gpios are outputs, there is a danger that a loss of core power (pwrok low) or a power button override event results in the ich5 driving a pin to a logic 1 to another device that is powered down. gpio[1:15] have ?sticky? bits on the input. refer to the gpe0_sts register. as long as the signal goes active for at least 2 clocks, the ich5 keeps the sticky status bit active. the active level can be selected in the gp_lvl register. if the system is in an s0 or an s1 state, the gpi inputs are sampled at 33 mhz, so the signal only needs to be active for about 60 ns to be latched. in the s3?s5 states, the gpi inputs are sampled at 32.768 khz, and thus must be active for at least 61 microseconds to be latched. if the input signal is still active when the latch is cleared, it will again be set. another edge trigger is not required. this makes these signals ?level? triggered inputs. 5.15.3 smi# and sci routing the routing bits for gpio[0:15] allow an input to be routed to smi# or sci, or neither. note that a bit can be routed to either an smi# or an sci, but not both. gpio[47:42] n/a n/a n/a ? not implemented gpio48 output only gnt4# core 3.3 v ? output controlled via gp_lvl2 register bit 48 ? ttl driver output gpio49 output only cpupwrgd cpu i/f 3.3 v ? gpio_use_sel bit 49 enables cpupwrgd. ? output controlled via gp_lvl2 register bit 49 ? ttl driver output table 74. gpio implementation (sheet 4 of 4) gpio type alternate function (note 1) power well tolerant notes 174 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.16 ide controller (d31:f1) the ich5 ide controller features two sets of interface signals (primary and secondary) that can be independently enabled, tri-stated or driven low. in addition, the ich5 ide controller supports both legacy mode and native mode ide interface. in native mode, the ide controller is a fully pci compliant software interface and does not use any legacy i/o or interrupt resources. the ide interfaces of the ich5 can support several types of data transfers: ? programmed i/o (pio): processor is in control of the data transfer. ? 8237 style dma: dma protocol that resembles the dma on the isa bus, although it does not use the 8237 in the ich5. this protocol off loads the processor from moving data. this allows higher transfer rate of up to 16 mb/s. ? ultra ata/33: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 33 mb/s. ? ultra ata/66: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 66 mb/s. ? ultra ata/100: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 100 mb/s. 5.16.1 pio transfers the ich5 ide controller includes both compatible and fast timing modes. the fast timing modes can be enabled only for the ide data ports. all other transactions to the ide registers are run in single transaction mode with compatible timings. up to two ide devices may be attached per ide connector (drive 0 and drive 1). the idetim and sidetim registers permit different timing modes to be programmed for drive 0 and drive 1 of the same connector. the ultra ata/33/66/100 synchronous dma timing modes can also be applied to each drive by programming the ide i/o configuration register and the synchronous dma control and timing registers. when a drive is enabled for synchronous dma mode operation, the dma transfers are executed with the synchronous dma timings. the pio transfers are executed using compatible timings or fast timings if also enabled. 5.16.1.1 ide port decode the command and control block registers are accessed differently depending on the decode mode, which is selected by the programming interface configuration register (offset 09h). note: the primary and secondary channels are controlled by separate bits, allowing one to be in native mode and the other in legacy mode simultaneously. intel ? 82801eb ich5 / 82801er ich5r datasheet 175 functional description 5.16.1.2 ide legacy mode and native mode the ich5 ide controller supports both legacy mode and pci native mode. in legacy mode, the command and control block registers are accessible at fixed i/o addresses. while in legacy mode, the ich5 does not decode any of the native mode ranges. likewise, in native mode the ich5 does not decode any of the legacy mode ranges. the ide i/o ports involved in pio transfers are decoded by the ich5 to the ide interface when d31:f1 i/o space is enabled and ide decode is enabled through the ide_timx registers. the ide registers are implemented in the drive itself. an access to the ide registers results in the assertion of the appropriate ide chip select for the register, and the ide command strobes (pdior#/ sdior#, pdiow#/sdiow#). there are two i/o ranges for each ide cable: the command block, which corresponds to the pcs1#/scs1# chip select, and the control block, which corresponds to the pcs3#/scs3# chip select. the command block is an 8-byte range, while the control block is a 4-byte range. ? command block offset: 01f0h for primary, 0170h for secondary ? control block offset: 03f4h for primary, 0374h for secondary table 75 specifies the registers as they affect the ich5 hardware definition. note: the data register (i/o offset 00h) should be accessed using 16-bit or 32-bit i/o instructions. all other registers should be accessed using 8-bit i/o instructions. note: for accesses to the alt status register in the control block, the ich5 must always force the upper address bit (pda2 or sda2) to 1 in order to guarantee proper native mode decode by the ide device. unlike the legacy mode fixed address location, the native mode address for this register may contain a 0 in address bit 2 when it is received by the ich5. in native mode, the ich5 does not decode the legacy ranges. the same offsets are used as in table 75 . however, the base addresses are selected using the pci bars, rather than fixed i/o locations. table 75. ide legacy i/o ports: command block registers (cs1x# chip select) i/o offset register function (read) register function (write) 00h data data 01h error features 02h sector count sector count 03h sector number sector number 04h cylinder low cylinder low 05h cylinder high cylinder high 06h drive head 07h status command 176 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.16.1.3 pio ide timing modes ide data port transaction latency consists of startup latency, cycle latency, and shutdown latency. startup latency is incurred when a pci master cycle targeting the ide data port is decoded and the da[2:0] and csxx# lines are not set up. startup latency provides the setup time for the da[2:0] and csxx# lines prior to assertion of the read and write strobes (dior# and diow#). cycle latency consists of the i/o command strobe assertion length and recovery time. recovery time is provided so that transactions may occur back-to-back on the ide interface (without incurring startup and shutdown latency) without violating minimum cycle periods for the ide interface. the command strobe assertion width for the enhanced timing mode is selected by the ide_tim register and may be set to 2, 3, 4, or 5 pci clocks. the recovery time is selected by the ide_tim register and may be set to 1, 2, 3, or 4 pci clocks. if iordy is asserted when the initial sample point is reached, no wait-states are added to the command strobe assertion length. if iordy is negated when the initial sample point is reached, additional wait-states are added. since the rising edge of iordy must be synchronized, at least two additional pci clocks are added. shutdown latency is incurred after outstanding scheduled ide data port transactions (either a non-empty write post buffer or an outstanding read prefetch cycles) have completed and before other transactions can proceed. it provides hold time on the da[2:0] and csxx# lines with respect to the read and write strobes (dior# and diow#). shutdown latency is two pci clocks in duration. the ide timings for various transaction types are shown in table 76 . note that bit 2 (16-bit i/o recovery enable) of the isa i/o recovery timer register does not add wait-states to ide data port read accesses when any of the fast timing modes are enabled. 5.16.1.4 iordy masking the iordy signal can be ignored and assumed asserted at the first iordy sample point (isp) on a drive by drive basis via the idetim register. 5.16.1.5 pio 32-bit ide data port accesses a 32-bit pci transaction run to the ide data address (01f0h primary, 0170h secondary) results in two back to back 16-bit transactions to the ide data port. the 32-bit data port feature is enabled for all timings, not just enhanced timing. for compatible timings, a shutdown and startup latency is incurred between the two, 16-bit halves of the ide transaction. this guarantees that the chip selects are deasserted for at least two pci clocks between the two cycles. table 76. ide transaction timings (pci clocks) ide transaction type startup latency iordy sample point (isp) recovery time (rct) shutdown latency non-data port compatible 4 11 22 2 data port compatible 3 6 14 2 fast timing mode 2 2?5 1?4 2 intel ? 82801eb ich5 / 82801er ich5r datasheet 177 functional description 5.16.1.6 pio ide data port prefetching and posting the ich5 can be programmed via the idetim registers to allow data to be posted to and prefetched from the ide data ports. data prefetching is initiated when a data port read occurs. the read prefetch eliminates latency to the ide data ports and allows them to be performed back to back for the highest possible pio data transfer rates. the first data port read of a sector is called the demand read. subsequent data port reads from the sector are called prefetch reads. the demand read and all prefetch reads much be of the same size (16 or 32 bits). data posting is performed for writes to the ide data ports. the transaction is completed on the pci bus after the data is received by the ich5. the ich5 then runs the ide cycle to transfer the data to the drive. if the ich5 write buffer is non-empty and an unrelated (non-data or opposite channel) ide transaction occurs, that transaction will be stalled until all current data in the write buffer is transferred to the drive. 5.16.2 bus master function the ich5 can act as a pci bus master on behalf of an ide slave device. two pci bus master channels are provided, one channel for each ide connector (primary and secondary). by performing the ide data transfer as a pci bus master, the ich5 off-loads the processor and improves system performance in multitasking environments. both devices attached to a connector can be programmed for bus master transfers, but only one device per connector can be active at a time. 5.16.2.1 physical region descriptor format the physical memory region to be transferred is described by a physical region descriptor (prd). the prds are stored sequentially in a descriptor table in memory. the data transfer proceeds until all regions described by the prds in the table have been transferred. note that the ich5 bus master ide function does not support memory regions or descriptor tables located on isa. descriptor tables must not cross a 64-kb boundary. each prd entry in the table is 8 bytes in length. the first 4 bytes specify the byte address of a physical memory region. this memory region must be dword-aligned and must not cross a 64-kbyte boundary. the next two bytes specify the size or transfer count of the region in bytes (64-kbyte limit per region). a value of 0 in these two bytes indicates 64 kbytes (thus the minimum transfer count is 1). if bit 7 (eot) of the last byte is a 1, it indicates that this is the final prd in the descriptor table. bus master operation terminates when the last descriptor has been retired. when the bus master ide controller is reading data from the memory regions, bit 1 of the base address is masked and byte enables are asserted for all read transfers. when writing data, bit 1 of the base address is not masked and if set, will cause the lower word byte enables to be deasserted for the first dword transfer. the write to pci typically consists of a 32-byte cache line. if valid data ends prior to end of the cache line, the byte enables will be deasserted for invalid data. the total sum of the byte counts in every prd of the descriptor table must be equal to or greater than the size of the disk transfer request. if greater than the disk transfer request, the driver must terminate the bus master transaction (by setting bit 0 in the bus master ide command register to 0) when the drive issues an interrupt to signal transfer completion. 178 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.16.2.2 line buffer a single line buffer exists for the ich5 bus master ide interface. this buffer is not shared with any other function. the buffer is maintained in either the read state or the write state. memory writes are typically 4-dword bursts and invalid dwords have c/be[3:0]#=0fh. the line buffer allows burst data transfers to proceed at peak transfer rates. the bus master ide active bit in bus master ide status register is reset automatically when the controller has transferred all data associated with a descriptor table (as determined by eot bit in last prd). the ide interrupt status bit is set when the ide device generates an interrupt. these events may occur prior to line buffer emptying for memory writes. if either of these conditions exist, all pci master non-memory read accesses to ich5 are retried until all data in the line buffers has been transferred to memory. 5.16.2.3 bus master ide timings the timing modes used for bus master ide transfers are identical to those for pio transfers. the dma timing enable only bits in ide timing register can be used to program fast timing mode for dma transactions only. this is useful for ide devices whose dma transfer timings are faster that its pio transfer timings. the ide device dma request signal is sampled on the same pci clock that dior# or diow# is deasserted. if inactive, the dma acknowledge signal is deasserted on the next pci clock and no more transfers take place until dma request is asserted again. 5.16.2.4 interrupts legacy mode the ich5 is connected to irq14 for the primary interrupt and irq15 for the secondary interrupt. this connection is done from the isa pin, before any mask registers. this implies the following: ? bus master ide devices are connected directly off of ich5. ide interrupts cannot be communicated through pci devices or the serial stream. warning: in this mode, the ich5 does not drive the pci interrupt associated with this function. that is only used in native mode. figure 18. physical region descriptor table entry eot reserved byte count [15:1] memory region physical base address [31:1] byte 3 byte 2 byte 1 byte 0 memory region main memory o o intel ? 82801eb ich5 / 82801er ich5r datasheet 179 functional description native mode in this case both the primary and secondary channels share an interrupt. it is internally connected to pirqc# (irq18 in apic mode). the interrupt is active-low and shared. behavioral notes in native mode ? the irq14 and irq15 pins do not affect the internal irq14 and irq15 inputs to the interrupt controllers. the ide logic forces these signals inactive in such a way that the serial irq source may be used. ? the irq14 and irq15 inputs (not external irq[14:15] pins) to the interrupt controller can come from other sources (serial irq, pirqx). ? the irq14 and irq15 pins are inverted from active-high to the active-low pirq. ? when switching the ide controller to native mode, the ide interrupt pin register (see section 10.1.18 ) is masked. if an interrupt occurs while the masking is in place and the interrupt is still active when the masking ends, the interrupt is allowed to be asserted. 5.16.2.5 bus master ide operation to initiate a bus master transfer between memory and an ide device, the following steps are required: 1. software prepares a prd table in system memory. the prd table must be dword aligned and must not cross a 64-kb boundary. 2. software provides the starting address of the prd table by loading the prd table pointer register. the direction of the data transfer is specified by setting the read/write control bit. the interrupt bit and error bit in the status register are cleared. 3. software issues the appropriate dma transfer command to the disk device. 4. the bus master function is engaged by software writing a 1 to the start bit in the command register. the first entry in the prd table is fetched and loaded into two registers which are not visible by software, the current base and current count registers. these registers hold the current value of the address and byte count loaded from the prd table. the value in these registers is only valid when there is an active command to an ide device. 5. once the prd is loaded internally, the ide device will receive a dma acknowledge. 6. the controller transfers data to/from memory responding to dma requests from the ide device. the ide device and the host controller may or may not throttle the transfer several times. when the last data transfer for a region has been completed on the ide interface, the next descriptor is fetched from the table. the descriptor contents are loaded into the current base and current count registers. 7. at the end of the transfer, the ide device signals an interrupt. 8. in response to the interrupt, software resets the start/stop bit in the command register. it then reads the controller status followed by the drive status to determine if the transfer completed successfully. the last prd in a table has the end of list (eol) bit set. the pci bus master data transfers terminate when the physical region described by the last prd in the table has been completely transferred. the active bit in the status register is reset and the ddrq signal is masked. 180 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description the buffer is flushed (when in the write state) or invalidated (when in the read state) when a terminal count condition exists; that is, the current region descriptor has the eol bit set and that region has been exhausted. the buffer is also flushed (write state) or invalidated (read state) when the interrupt bit in the bus master ide status register is set. software that reads the status register and finds the error bit reset, and either the active bit reset or the interrupt bit set, can be assured that all data destined for system memory has been transferred and that data is valid in system memory. table 77 describes how to interpret the interrupt and active bits in the status register after a dma transfer has started. during concurrent dma or ultra ata transfers, the ich5 ide interface arbitrate between the primary and secondary ide cables when a prd expires. 5.16.2.6 error conditions ide devices are sector based mass storage devices. the drivers handle errors on a sector basis; either a sector is transferred successfully or it is not. a sector is 512 bytes. if the ide device does not complete the transfer due to a hardware or software error, the command will eventually be stopped by the driver setting command start bit to 0 when the driver times out the disk transaction. information in the ide device registers help isolate the cause of the problem. if the controller encounters an error while doing the bus master transfers it will stop the transfer (i.e., reset the active bit in the command register) and set the error bit in the bus master ide status register. the controller does not generate an interrupt when this happens. the device driver can use device specific information (pci configuration space status register and ide drive register) to determine what caused the error. whenever a requested transfer does not complete properly, information in the ide device registers (sector count) can be used to determine how much of the transfer was completed and to construct a new prd table to complete the requested operation. in most cases the existing prd table can be used to complete the operation. 5.16.2.7 8237-like protocol the 8237 mode dma is similar in form to dma used on the isa bus. this mode uses pins familiar to the isa bus, namely a dma request, a dma acknowledge, and i/o read/write strobes. these pins have similar characteristics to their isa counterparts in terms of when data is valid relative to strobe edges, and the polarity of the strobes, however the ich5 does not use the 8237 for this mode. table 77. interrupt/active bit interaction definition interrupt active description 0 1 dma transfer is in progress. no interrupt has been generated by the ide device. 10 the ide device generated an interrupt. the controller exhausted the physical region descriptors. this is the normal completion case where the size of the physical memory regions was equal to the ide device transfer size. 11 the ide device generated an interrupt. the controller has not reached the end of the physical memory regions. this is a valid completion case where the size of the physical memory regions was larger than the ide device transfer size. 00 this bit combination signals an error condition. if the error bit in the status register is set, then the controller has some problem transferring data to/from memory. specifics of the error have to be determined using bus-specific information. if the error bit is not set, then the prd's specified a smaller size than the ide transfer size. intel ? 82801eb ich5 / 82801er ich5r datasheet 181 functional description 5.16.3 ultra ata/33 protocol ultra ata/33 is enabled through configuration register 48h in device 31:function 1 for each ide device. the ide signal protocols are significantly different under this mode than for the 8237 mode. ultra ata/33 is a physical protocol used to transfer data between a ultra ata/33 capable ide controller (e.g., the ich5) and one or more ultra ata/33 capable ide devices. it utilizes the standard bus master ide functionality and interface to initiate and control the transfer. ultra ata/33 utilizes a ?source synchronous? signaling protocol to transfer data at rates up to 33 mb/s. the ultra ata/33 definition also incorporates a cyclic redundancy checking (crc-16) error checking protocol. 5.16.3.1 signal descriptions the ultra ata/33 protocol requires no extra signal pins on the ide connector. it does redefine a number of the standard ide control signals when in ultra ata/33 mode. these redefinitions are shown in table 78 . read cycles are defined as transferring data from the ide device to the ich5. write cycles are defined as transferring data from ich5 to ide device. the diow# signal is redefined as stop for both read and write transfers. this is always driven by the ich5 and is used to request that a transfer be stopped or as an acknowledgment to stop a request from the ide device. the dior# signal is redefined as dmardy# for transferring data from the ide device to the ich5 (read). it is used by the ich5 to signal when it is ready to transfer data and to add wait-states to the current transaction. the dior# signal is redefined as strobe for transferring data from the ich5 to the ide device (write). it is the data strobe signal driven by the ich5 on which data is transferred during each rising and falling edge transition. the iordy signal is redefined as strobe for transferring data from the ide device to the ich5 (read). it is the data strobe signal driven by the ide device on which data is transferred during each rising and falling edge transition. the iordy signal is redefined as dmardy# for transferring data from the ich5 to the ide device (write). it is used by the ide device to signal when it is ready to transfer data and to add wait-states to the current transaction. all other signals on the ide connector retain their functional definitions during ultra ata/33 operation. table 78. ultraata/33 control signal redefinitions standard ide signal definition ultraata/33read cycle definition ultra ata/33 write cycle definition intel ? ich5 primary channel signal intel ? ich5 secondary channel signal diow# stop stop pdiow# sdiow# dior# dmardy# strobe pdior# sdior# iordy strobe dmardy# piordy siordy 182 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.16.3.2 operation initial setup programming consists of enabling and performing the proper configuration of the ich5 and the ide device for ultra ata/33 operation. for the ich5, this consists of enabling synchronous dma mode and setting up appropriate synchronous dma timings. when ready to transfer data to or from an ide device, the bus master ide programming model is followed. once programmed, the drive and ich5 control the transfer of data via the ultra ata/33 protocol. the actual data transfer consists of three phases, a start-up phase, a data transfer phase, and a burst termination phase. the ide device begins the start-up phase by asserting dmarq signal. when ready to begin the transfer, the ich5 asserts dmack# signal. when dmack# signal is asserted, the host controller drives cs0# and cs1# inactive, da0?da2 low. for write cycles, the ich5 deasserts stop, waits for the ide device to assert dmardy#, and then drives the first data word and strobe signal. for read cycles, the ich5 tri-states the dd lines, deasserts stop, and asserts dmardy#. the ide device then sends the first data word and strobe. the data transfer phase continues the burst transfers with the data transmitter (ich5 ? writes, ide device ? reads) providing data and toggling strobe. data is transferred (latched by receiver) on each rising and falling edge of strobe. the transmitter can pause the burst by holding strobe high or low, resuming the burst by again toggling strobe. the receiver can pause the burst by deasserting dmardy# and resumes the transfers by asserting dmardy#. the ich5 pauses a burst transaction to prevent an internal line buffer over or under flow condition, resuming once the condition has cleared. it may also pause a transaction if the current prd byte count has expired, resuming once it has fetched the next prd. the current burst can be terminated by either the transmitter or receiver. a burst termination consists of a stop request, stop acknowledge and transfer of crc data. the ich5 can stop a burst by asserting stop, with the ide device acknowledging by deasserting dmarq. the ide device stops a burst by deasserting dmarq and the ich5 acknowledges by asserting stop. the transmitter then drives the strobe signal to a high level. the ich5 then drives the crc value onto the dd lines and deassert dmack#. the ide device latches the crc value on rising edge of dmack#. the ich5 terminates a burst transfer if it needs to service the opposite ide channel, if a programmed i/o (pio) cycle is executed to the ide channel currently running the burst, or upon transferring the last data from the final prd. 5.16.3.3 crc calculation cyclic redundancy checking (crc-16) is used for error checking on ultra ata/33 transfers. the crc value is calculated for all data by both the ich5 and the ide device over the duration of the ultra ata/33 burst transfer segment. this segment is defined as all data transferred with a valid strobe edge from ddack# assertion to ddack# deassertion. at the end of the transfer burst segment, the ich5 drives the crc value onto the dd[15:0] signals. it is then latched by the ide device on deassertion of ddack#. the ide device compares the ich5 crc value to its own and reports an error if there is a mismatch. intel ? 82801eb ich5 / 82801er ich5r datasheet 183 functional description 5.16.4 ultra ata/66 protocol in addition to ultra ata/33, the ich5 supports the ultra ata/66 protocol. the ultra ata/66 protocol is enabled via configuration bits 3:0 at offset 54h. the two protocols are similar, and are intended to be device driver compatible. the ultra ata/66 logic can achieve transfer rates of up to 66 mb/s. to achieve the higher data rate, the timings are shortened and the quality of the cable is improved to reduce reflections, noise, and inductive coupling. note that the improved cable is required and still plugs into the standard ide connector. the ultra ata/66 protocol also supports a 44 mb/s mode. 5.16.5 ultra ata/100 protocol when the ata_fast bit is set for any of the four ide devices, then the timings for the transfers to and from the corresponding device run at a higher rate. the ich5 ultra ata/100 logic can achieve read transfer rates up to 100 mb/s, and write transfer rates up to 88.9 mb/s. the cable improvements required for ultra ata/66 are sufficient for ultra ata/100, so no further cable improvements are required when implementing ultra ata/100. 5.16.6 ultra ata/33/66/100 timing the timings for ultra ata/33/66/100 modes are programmed via the synchronous dma timing register and the ide configuration register. different timings can be programmed for each drive in the system. the base clock frequency for each drive is selected in the ide configuration register. the cycle time (ct) and ready to pause (rp) time (defined as multiples of the base clock) are programmed in the synchronous dma timing register. the cycle time represents the minimum pulse width of the data strobe (strobe) signal. the ready to pause time represents the number of base clock periods that the ich5 waits from deassertion of dmardy# to the assertion of stop when it desires to stop a burst read transaction. note: the internal base clock for ultra ata/100 (mode 5) runs at 133 mhz, and the cycle time (ct) must be set for three base clocks. the ich5 thus toggles the write strobe signal every 22.5 ns, transferring two bytes of data on each strobe edge. this means that the ich5 performs mode 5 write transfers at a maximum rate of 88.9 mb/s. for read transfers, the read strobe is driven by the ata/100 device, and the ich5 supports reads at the maximum rate of 100 mb/s. 184 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.16.7 ide swap bay to support a swap bay, the ich5 allows the ide output signals to be tri-stated and input buffers to be turned off. this should be done prior to the removal of the drive. the output signals can also be driven low. this can be used to remove charge built up on the signals. configuration bits are included in the ide i/o configuration register, offset 54h in the ide pci configuration space. in an ide hot swap operation, an ide device is removed and a new one inserted while the ide interface is powered down and the rest of the system is in a fully powered-on state (so). during an ide hot swap, if the operating system executes cycles to the ide interface after it has been powered down it will cause the ich5 to hang the system that is waiting for iordy to be asserted from the drive. to correct this issue, the following bios procedures are required for performing an ide hot swap: 1. program ide sig_mode (configuration register at offset 54h) to 10b (drive low mode). 2. clear iordy sample point enable (bits 1 or 5 of ide timing reg.). this prevents the ich5 from waiting for iordy assertion when the operating system accesses the ide device after the ide drive powers down, and ensures that 0s are always be returned for read cycles that occur during hot swap operation. warning: software should not attempt to control the outputs (either tri-state or driving low), while an ide transfer is in progress. unpredictable results could occur, including a system lockup. 5.16.8 smi trapping (apm) offset 48h, bits 3:0 in the power management i/o space (see section 9.10.14 ) contain control for generating smi# on accesses to the ide i/o spaces. these bits map to the legacy ranges (1f0 ? 1f7h, 3f6h, 170 ? 177h, and 376h). if the ide controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the ide controller, and for an smi# to be generated. if an access to the bus-master ide registers occurs while trapping is enabled for the device being accessed, then the register is updated, an smi# is generated, and the device activity status bits ( section 9.10.13 ) are updated indicating that a trap occurred. to block accesses to the native ide ranges, software must use the generic power management control registers described in section 9.8.1 . intel ? 82801eb ich5 / 82801er ich5r datasheet 185 functional description 5.17 sata host controller (d31:f2) the sata function in the ich5 has dual modes of operation to support different operating system conditions. in the case of native ide enabled operating systems, the ich5 has separate pci functions for serial and parallel ata. to support legacy operating systems, there is only one pci function for both the serial and parallel ata ports. the map register, section 11.1.32 , provides the ability to share pci functions. when sharing is enabled, all decode of i/o is done through the sata registers. device 31, function 1 (ide controller) is hidden by software writing to the function disable register (d31, f0, offset f2h, bit 1), and its configuration registers are not used. the sata capability pointer register (offset 34h) will change to indicate that msi is not supported in combined mode. the ich5 sata controller features two sets of interface signals that can be independently enabled or disabled (they cannot be tri-stated or driven low). each interface is supported by an independent dma controller. the ich5 sata controller interacts with an attached mass storage device through a register interface that is equivalent to that presented by a traditional ide host adapter. the host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions. note: sata interface transfer rates are independent of udma mode settings. sata interface transfer rates will operate at the bus?s maximum speed, regardless of the udma mode reported by the sata device or the system bios. 5.17.1 theory of operation 5.17.1.1 standard ata emulation the ich5 contains a set of registers that shadow the contents of the legacy ide registers. the behavior of the command and control block registers, pio, and dma data transfers, resets, and interrupts are all emulated. 5.17.1.2 48-bit lba operation the sata host controller supports 48-bit lba through the host-to-device register fis when accesses are performed via writes to the task file. the sata host controller will ensure that the correct data is put into the correct byte of the host-to-device fis. there are special considerations when reading from the task file to support 48-bit lba operation. software may need to read all 16-bits. since the registers are only 8-bits wide and act as a fifo, a bit must be set in the device/control register, which is at offset 3f6h for primary and 376h for secondary (or their native counterparts). if software clears bit 7 of the control register before performing a read, the last item written will be returned from the fifo. if software sets bit 7 of the control register before performing a read, the first item written will be returned from the fifo. 186 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.17.2 hot swap operation dynamic hot swap (e.g., surprise removal) is not supported by the sata host controller. however, using the spc register configuration bits, and power management flows, a device can be powered down by software, and the port can then be powered off, allowing removal and insertion of a new device. note: this hot swap operation requires bios and os support. 5.17.3 intel ? raid technology configuration (intel ? 82801er ich5r only) the intel ? raid technology solution, available with the 82801er ich5 r (ich5r), offers data stripping for higher performance (raid level 0), alleviating disk bottlenecks by taking advantage of the dual independent sata controllers integrated in the ich5r. there is no loss of pci resources (request/grant pair) or add-in card slot. intel raid technology functionality requires the following items: 1. ich5r 2. intel raid technology option rom must be on the platform 3. intel ? application accelerator raid edition drivers, most recent revision. 4. two sata hard disk drives. intel raid technology is not available in the following configurations: 1. the sata controller in compatible mode. 2. intel raid technology has been disabled - d31:f0:ae bits [7:6] have been cleared 5.17.3.1 intel ? raid technology option rom the intel raid technology for sata option rom provides a pre-os user interface for the intel raid technology implementation and provides the ability for a intel raid technology volume to be used as a boot disk as well as to detect any faults in the intel raid technology volume(s) attached to the intel raid controller. 5.17.4 power management operation power management of the ich5 sata controller and ports will cover operations of the host controller and the sata wire. 5.17.4.1 power state mappings the d0 pci power management state for device is supported by the ich5 sata controller. sata devices may also have multiple power states. from parallel ata, three device states are supported through acpi. they are: ? d0 ? device is working and instantly available. intel ? 82801eb ich5 / 82801er ich5r datasheet 187 functional description ? d1 ? device enters when it receives a standby immediate command. exit latency from this state is in seconds ? d3 ? from the sata device?s perspective, no different than a d1 state, in that it is entered via the standby immediate command. however, an acpi method is also called which will reset the device and then cut its power. each of these device states are subsets of the host controller?s d0 state. finally, sata defines three phy layer power states, which have no equivalent mappings to parallel ata. they are: ? phy ready ? phy logic and pll are both on and active ? partial ? phy logic is powered, but in a reduced state. exit latency is no longer than 10 ns ? slumber ? phy logic is powered, but in a reduced state. exit latency can be up to 10 ms. since these states have much lower exit latency than the acpi d1 and d3 states, the sata controller defines these states as sub-states of the device d0 state. 5.17.4.2 power state transitions 5.17.4.2.1 partial and slumber state entry/exit the partial and slumber states save interface power when the interface is idle. the sata controller defines phy layer power management (as performed via primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. the sata controller accepts device transition types, but does not issue any transitions as a host. all received requests from a sata device will be acked. when an operation is performed to the sata controller such that it needs to use the sata cable, the controller must check whether the link is in the partial or slumber states, and if so, must issue a com_wake to bring the link back online. similarly, the sata device must perform the same action. figure 19. sata power states host = d0 device = d3 power resume latency device = d0 phy = ready device = d1 phy = slumber phy = partial phy = off (port disabled) phy = slumber phy = off (port disabled) phy = slumber phy = off (port disabled) 188 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.17.4.2.2 device d1, d3 states these states are entered after some period of time when software has determined that no commands will be sent to this device for some time. the mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to the device. the command most likely to be used in ata/atapi is the ?standby immediate? command. 5.17.4.3 smi trapping (apm) offset 48h, bits 3:0 in the power management i/o space (see section 9.10.14 ) contain control for generating smi# on accesses to the ide i/o spaces. these bits map to the legacy ranges (1f0 ? 1f7h, 3f6h, 170 ? 177h, and 376h). if the sata controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the sata controller, and for an smi# to be generated. if an access to the bus-master ide registers occurs while trapping is enabled for the device being accessed, then the register is updated, an smi# is generated, and the device activity status bits ( section 9.10.13 ) are updated indicating that a trap occurred. to block accesses to the native ide ranges, software must use the generic power management control registers described in section 9.8.9 . 5.17.5 sata interrupts table 79 summarizes interrupt behavior for msi and wire-modes. in the table ?bits? refers to the four possible interrupt bits in i/o space, which are: psts.prdis (offset 02h, bit 7), psts.i (offset 02h, bit 2), ssts.prdis (offset 0ah, bit 7), and ssts.i (offset 0ah, bit 2). 5.18 high-precision event timers this function provides a set of timers that can be used by the operating system. the timers are defined such that in the future, the operating system may be able to assign specific timers to used directly by specific applications. each timer can be configured to cause a separate interrupt. ich5 provides three timers. the three timers are implemented as a single counter each with its own comparator and value register. this counter increases monotonically. each individual timer can generate an interrupt when the value in its value register matches the value in the main counter. table 79. sata msi vs. pci irq actions interrupt register wire-mode action msi action all bits are 0 wire inactive no action one or more bits set to 1 wire active send message one or more bits set to 1, new bit gets set to 1 wire active send message one or more bits set to 1, software clears some (but not all) bits wire active send message one or more bits set to 1, software clears all bits wire inactive no action software clears one or more bits, and one or more bits is set simultaneously wire active send message intel ? 82801eb ich5 / 82801er ich5r datasheet 189 functional description the registers associated with these timers are mapped to a memory space (much like the i/o apic). however, it is not implemented as a standard pci function. the bios reports to the operating system the location of the register space. the hardware can support an assignable decode space; however, the bios sets this space prior to handing it over to the operating system (see section 6.4 ). it is not expected that the operating system will move the location of these timers once it is set by the bios. 5.18.1 timer accuracy 1. the timers are accurate over any 1 ms period to within 0.05% of the time specified in the timer resolution fields. 2. within any 100 microsecond period, the timer reports a time that is up to two ticks too early or too late. each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. the timer is monotonic. it does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). the main counter is clocked by the 14.31818 mhz clock, synchronized into the 66.666 mhz domain. this results in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. the accuracy of the main counter is as accurate as the 14.3818 mhz clock. 5.18.2 interrupt mapping mapping option #1 (legacy option) in this case, the legacy rout bit (leg_rt_cnf) is set. this forces the mapping found in table 80 . mapping option #2 (standard option) in this case, the legacy rout bit (leg_rt_cnf) is 0. each timer has its own routing control. the supported interrupt values are irq 20, 21, 22, and 23. 5.18.3 periodic vs. non-periodic modes non-periodic mode when a timer is set up for non-periodic mode, it generates a value in the main counter that matches the value in the timer?s comparator register. if the timer is set up for 32-bit mode, then it generates another interrupt when the main counter wraps around and matches this same value again. timer 0 is configurable to 32 (default) or 64-bit mode, whereas timers 1 and 2 only support 32-bit mode (see section 17.5 ). table 80. legacy routing timer 8259 mapping apic mapping comment 0irq0 irq2 in this case, the 8254 timer will not cause any interrupts 1irq8 irq8 in this case, the rtc will not cause any interrupts. 2 per irq routing field. per irq routing field 190 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description during run-time, the value in the timer?s comparator value register will not be changed by the hardware. software can change the value. warning: software must be careful when programming the comparator registers. if the value written to the register is not sufficiently far in the future, then the counter may pass the value before it reaches the register and the interrupt will be missed. all three timers support non-periodic mode. periodic mode timer 0 is the only timer that supports periodic mode. when timer 0 is set up for periodic mode, the software writes a value into the timer?s comparator value register. when the main counter value matches the value in the timer?s comparator value register, an interrupt can be generated. the hardware then automatically increases the value in the comparator value register by the last value written to that register. to make the periodic mode work properly, the main counter is typically written with a value of 0 so that the first interrupt occurs at the right point for the comparator. if the main counter is not set to 0, interrupts may not occur as expected. during run-time, the value in the timer?s comparator value register can be read by software to find out when the next periodic interrupt will be generated (not the rate at which it generates interrupts). software is expected to remember the last value written to the comparator?s value register (the rate at which interrupts are generated). if software wants to change the periodic rate, it should write a new value to the comparator value register. at the point when the timer?s comparator indicates a match, this new value is added to derive the next matching point. if the software resets the main counter, the value in the comparator?s value register needs to reset as well. this can be done by setting the timer0_val_set_cnf bit. again, to avoid race conditions, this should be done with the main counter halted. the following usage model is expected: 1. software clears the enable_cnf bit to prevent any interrupts 2. software clears the main counter by writing a value of 00h to it. 3. software sets the timer0_val_set_cnf bit. 4. software writes the new value in the timer0_comparator_val register 5. software sets the enable_cnf bit to enable interrupts. the timer 0 comparator value register cannot be programmed reliably by a single 64-bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. if the actual timer 0 comparator value needs to be reinitialized, then the following software solution will always work regardless of the environment: 1. set timer0_val_set_cnf bit 2. set the lower 32 bits of the timer0 comparator value register 3. set timer0_val_set_cnf bit 4. 4) set the upper 32 bits of the timer0 comparator value register intel ? 82801eb ich5 / 82801er ich5r datasheet 191 functional description 5.18.4 enabling the timers the bios or os pnp code should route the interrupts. this includes the legacy rout bit, interrupt rout bit (for each timer), interrupt type (to select the edge or level type for each timer) the device driver code should do the following for an available timer: 1. set the overall enable bit (offset 04h, bit 0). 2. set the timer type field (selects one-shot or periodic). 3. set the interrupt enable 4. set the comparator value 5.18.5 interrupt levels interrupts directed to the internal 8259s are active high. see section 5.9 for information regarding the polarity programming of the i/o apic for detecting internal interrupts. if the interrupts are mapped to the i/o apic and set for level-triggered mode, they can be shared with pci interrupts. this may be shared although it?s unlikely for the os to attempt to do this. if more than one timer is configured to share the same irq (using the timern_int_rout_cnf fields), then the software must configure the timers to level-triggered mode. edge-triggered interrupts cannot be shared. 5.18.6 handling interrupts if each timer has a unique interrupt and the timer has been configured for edge-triggered mode, then there are no specific steps required. no read is required to process the interrupt. if a timer has been configured to level-triggered mode, then its interrupt must be cleared by the software. this is done by reading the interrupt status register and writing a 1 back to the bit position for the interrupt to be cleared. independent of the mode, software can read the value in the main counter to see how time has passed between when the interrupt was generated and when it was first serviced. if timer 0 is set up to generate a periodic interrupt, the software can check to see how much time remains until the next interrupt by checking the timer value register. 5.18.7 issues related to 64-bit timers with 32-bit processors a 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit instructions. however, a 32-bit processor may not be able to directly read 64-bit timer. a race condition comes up if a 32-bit processor reads the 64-bit register using two separate 32-bit reads. the danger is that just after reading one half, the other half rolls over and changes the first half. if a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer. if a 32-bit processor does not want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the timern_32mode_cnf bit. this causes the timer to behave as a 32-bit timer. the upper 32-bits are always 0. 192 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.19 usb uhci host controllers (d29:f0, f1, f2, and f3) the ich5 contains four usb 2.0 full/low speed host controllers that support the standard universal host controller interface (uhci), revision 1.1. each uhci host controller (uhc) includes a root hub with two separate usb ports each, for a total of 8 usb ports. ? overcurrent detection on all eight usb ports is supported. the overcurrent inputs are 5 v tolerant, and can be used as gpis if not needed. ? the ich5?s uhci host controllers are arbitrated differently than standard pci devices to improve arbitration latency. ? the uhci controllers use the analog front end (afe) embedded cell that allows support for usb high speed signaling rates, instead of usb i/o buffers. 5.19.1 data structures in main memory this section describes the details of the data structures used to communicate control, status, and data between software and the ich5: frame lists, transfer descriptors, and queue heads. frame lists are aligned on 4-kb boundaries. transfer descriptors and queue heads are aligned on 16-byte boundaries. 5.19.1.1 frame list pointer the frame list pointer contains a link pointer to the first data object to be processed in the frame, as well as the control bits defined in table 81 . table 81. frame list pointer bit description bit description 31:4 frame list pointer (flp). this field contains the address of the first data object to be processed in the frame and corresponds to memory address signals [31:4], respectively. 3:2 reserved. these bits must be written as 0. 1 qh/td select (q). this bit indicates to the hardware whether the item referenced by the link pointer is a td (transfer descriptor) or a qh (queue head). this allows the intel ? ich5 to perform the proper type of processing on the item after it is fetched. 0 = td 1 = qh 0 terminate (t). this bit indicates to the ich5 whether the schedule for this frame has valid entries in it. 0 = pointer is valid (points to a qh or td). 1 = empty frame (pointer is invalid). intel ? 82801eb ich5 / 82801er ich5r datasheet 193 functional description 5.19.1.2 transfer descriptor (td) transfer descriptors (tds) express the characteristics of the transaction requested on usb by a client. tds are always aligned on 16-byte boundaries, and the elements of the td are shown in figure 20 . the four, different usb transfer types are supported by a small number of control bits in the descriptor that the ich5 interprets during operation. all tds have the same, basic, 32-byte structure. during operation, the ich5 hardware performs consistency checks on some fields of the td. if a consistency check fails, the ich5 halts immediately and issues an interrupt to the system. this interrupt cannot be masked within the ich5. figure 20. transfer descriptor table 82. td link pointer bits description 31:4 link pointer (lp). bits [31:4] correspond to memory address signals [31:4], respectively. this field points to another td or qh. 3 reserved. must be 0 when writing this field. 2 depth/breadth select (vf). this bit is only valid for queued tds and indicates to the hardware whether it should process in a depth first or breadth first fashion. when set to depth first, it informs the ich5 to process the next transaction in the queue rather than starting a new queue. 0 = breadth first 1 = depth first 1 qh/td select (q). this bit informs the intel ? ich5 whether the item referenced by the link pointer is another td or a qh. this allows the ich5 to perform the proper type of processing on the item after it is fetched. 0 = td 1 = qh 0 terminate (t). this bit informs the ich5 that the link pointer in this td does not point to another valid entry. when encountered in a queue context, this bit indicates to the ich5 that there are no more valid entries in the queue. a td encountered outside of a queue context with the t bit set informs the ich5 that this is the last td in the frame. 0 = link pointer field is valid. 1 = link pointer field not valid. q 0 0 1 2 3 4 31 maxlen t 7 8 15 16 23 24 10 11 14 18 19 20 rd status r 25 26 27 28 29 30 21 ich5 read only link pointer endpt device address pid actlen vf c_err ls spd iso isc r buffer pointer r = reserved intel ? ich5 read/write 194 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description table 83. td control and status (sheet 1 of 2) bit description 31:30 reserved. 29 short packet detect (spd). when a packet has this bit set to 1 and the packet is an input packet, is in a queue; and successfully completes with an actual length less than the maximum length then the td is marked inactive, the queue header is not updated and the usbint status bit (status register) is set at the end of the frame. in addition, if the interrupt is enabled, the interrupt is sent at the end of the frame. note that any error (e.g., babble or fifo error) prevents the short packet from being reported. the behavior is undefined when this bit is set with output packets or packets outside of queues. 0 = disable 1 = enable 28:27 error counter (c_err). this field is a 2-bit down counter that keeps track of the number of errors detected while executing this td. if this field is programmed with a non-zero value during setup, the intel ? ich5 decrements the count and writes it back to the td if the transaction fails. if the counter counts from 1 to 0, the ich5 marks the td inactive, sets the ?stalled? and error status bit for the error that caused the transition to 0 in the td. an interrupt is generated to host controller driver (hcd) if the decrement to 0 was caused by data buffer error, bit stuff error, or if enabled, a crc or timeout error. if hcd programs this field to 0 during setup, the ich5 will not count errors for this td and there will be no limit on the retries of this td. bits[28:27] interrupt after 00 no error limit 01 1 error 10 2 errors 11 3 errors error decrement counter error decrement counter crc error yes data buffer error yes timeout error yes stalled no 1 nak received no bit stuff error yes babble detected no 1 note: 1. detection of babble or stall automatically deactivates the td. thus, count is not decremented. 26 low speed device (ls). this bit indicates that the target device (usb data source or sink) is a low speed device, running at 1.5 mb/s, instead of at full speed (12 mb/sec). there are special restrictions on schedule placement for low speed tds. if an ich5 root hub port is connected to a full speed device and this bit is set to a 1 for a low speed transaction, the ich5 sends out a low speed preamble on that port before sending the pid. no preamble is sent if a ich5 root hub port is connected to a low speed device. 0 = full speed device 1 = low speed device 25 isochronous select (ios). the field specifies the type of the data structure. if this bit is set to a 1, then the td is an isochronous transfer. isochronous tds are always marked inactive by the hardware after execution, regardless of the results of the transaction. 0 = non-isochronous transfer descriptor 1 = isochronous transfer descriptor 24 interrupt on complete (ioc). this specifies that the ich5 should issue an interrupt on completion of the frame in which this transfer descriptor is executed. even if the active bit in the td is already cleared when the td is fetched (no transaction will occur on usb), an ioc interrupt is generated at the end of the frame. 1 = issue ioc 23 active. for ich5 schedule execution operations, see section 5.19.2 , data transfers to/from main memory. 0 = when the transaction associated with this descriptor is completed, the ich5 sets this bit to 0 indicating that the descriptor should not be executed when it is next encountered in the schedule. the active bit is also set to 0 if a stall handshake is received from the endpoint. 1 = set to 1 by software to enable the execution of a message transaction by the ich5. intel ? 82801eb ich5 / 82801er ich5r datasheet 195 functional description 22 stalled. 1 = set to a 1 by the ich5 during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this td. this can be caused by babble, the error counter counting down to 0, or reception of the stall handshake from the device during the transaction. any time that a transaction results in the stalled bit being set, the active bit is also cleared (set to 0). if a stall handshake is received from a setup transaction, a time out error will also be reported. 21 data buffer error (dbe). 1 = set to a 1 by the ich5 during status update to indicate that the ich5 is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun). when this occurs, the actual length and max length field of the td does not match. in the case of an underrun, the ich5 transmits an incorrect crc (thus, invalidating the data at the endpoint) and leaves the td active (unless error count reached 0). if a overrun condition occurs, the ich5 forces a timeout condition on the usb, invalidating the transaction at the source. 20 babble detected (babd). 1 = set to a 1 by the ich5 during status update when ?babble? is detected during the transaction generated by this descriptor. babble is unexpected bus activity for more than a preset amount of time. in addition to setting this bit, the ich5 also sets the? stalled? bit (bit 22) to a 1. since ?babble? is considered a fatal error for that transfer, setting the? stalled? bit to a 1 insures that no more transactions occur as a result of this descriptor. detection of babble causes immediate termination of the current frame. no further tds in the frame are executed. execution resumes with the next frame list index. 19 negative acknowledgment (nak) received (nakr). 1 = set to a 1 by the ich5 during status update when the ich5 receives a ?nak? packet during the transaction generated by this descriptor. if a nak handshake is received from a setup transaction, a time out error will also be reported. 18 crc/time out error (crc_tout). 1 = set to a 1 by the ich5 as follows: ? during a status update in the case that no response is received from the target device/endpoint within the time specified by the protocol chapter of the universal serial bus revision 2.0 specification . ? during a status update when a cycli redundancy check (crc) error is detected during the transaction associated with this transfer descriptor. in the transmit case (out or setup command), this is in response to the ich5 detecting a timeout from the target device/endpoint. in the receive case (in command), this is in response to the ich5?s crc checker circuitry detecting an error on the data received from the device/endpoint or a nak or stall handshake being received in response to a setup transaction. 17 bit stuff error (bse). 1 = this bit is set to a 1 by the ich5 during status update to indicate that the receive data stream contained a sequence of more than six 1s in a row. 16 bus turn around time-out (btto). 1 = this bit is set to a 1 by the ich5 during status updates to indicate that a bus time-out condition was detected for this usb transaction. this time-out is specially defined as not detecting an idle-to ?k? state start of packet (sop) transition from 16 to 18 bit times after the se0-to ide transition of previous end of packet (eop). 15:11 reserved 10:0 actual length (actlen). the actual length field is written by the ich5 at the conclusion of a usb transaction to indicate the actual number of bytes that were transferred. it can be used by the software to maintain data integrity. the value programmed in this register is encoded as n-1 (see maximum length field description in the td token). table 83. td control and status (sheet 2 of 2) bit description 196 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description table 84. td token bit description 31:21 maximum length (maxlen). the maximum length field specifies the maximum number of data bytes allowed for the transfer. the maximum length value does not include protocol bytes, such as packet id (pid) and crc. the maximum data packet is 1280 bytes. the 1280 packet length is the longest packet theoretically guaranteed to fit into a frame. actual packet maximum lengths are set by hcd according to the type and speed of the transfer. note that the maximum length allowed by the universal serial bus revision 2.0 specification is 1023 bytes. the valid encodings for this field are: 0x000 = 1 byte 0x001 = 2 bytes .... 0x3fe = 1023 bytes 0x3ff = 1024 bytes .... 0x4ff = 1280 bytes 0x7ff = 0 bytes (null data packet) note that values from 500h to 7feh are illegal and cause a consistency check failure. in the transmit case, the intel ? ich5 uses this value as a terminal count for the number of bytes it fetches from host memory. in most cases, this is the number of bytes it will actually transmit. in rare cases, the ich5 may be unable to access memory (e.g., due to excessive latency) in time to avoid underrunning the transmitter. in this instance the ich5 would transmit fewer bytes than specified in the maximum length field. 20 reserved. 19 data toggle (d). this bit is used to synchronize data transfers between a usb endpoint and the host. this bit determines which data pid is sent or expected (0=data0 and 1=data1). the data toggle bit provides a 1-bit sequence number to check whether the previous packet completed. this bit must always be 0 for isochronous tds. 18:15 endpoint (endpt). this 4-bit field extends the addressing internal to a particular device by providing 16 endpoints. this permits more flexible addressing of devices in which more than one sub-channel is required. 14:8 device address. this field identifies the specific device serving as the data source or sink. 7:0 packet identification (pid). this field contains the packet id to be used for this transaction. only the in (69h), out (e1h), and setup (2dh) tokens are allowed. any other value in this field causes a consistency check failure resulting in an immediate halt of the ich5. bits [3:0] are complements of bits [7:4]. table 85. td buffer pointer bit description 31:0 buffer pointer (buff_pnt). bits [31:0] corresponds to memory address [31:0], respectively. it points to the beginning of the buffer that will be used during this transaction. this buffer must be at least as long as the value in the maximum length field described int the td token. the data buffer may be byte-aligned. intel ? 82801eb ich5 / 82801er ich5r datasheet 197 functional description 5.19.1.3 queue head (qh) queue heads are special structures used to support the requirements of control, bulk, and interrupt transfers. since these tds are not automatically retired after each use, their maintenance requirements can be reduced by putting them into a queue. queue heads must be aligned on a 16-byte boundary, and the elements are shown in table 86 . table 86. queue head block bytes description attributes 00?03 queue head link pointer ro 04?07 queue element link pointer r/w table 87. queue head link pointer bit description 31:4 queue head link pointer (qhlp). this field contains the address of the next data object to be processed in the horizontal list and corresponds to memory address signals [31:4], respectively. 3:2 reserved. these bits must be written as 0s. 1 qh/td select (q). this bit indicates to the hardware whether the item referenced by the link pointer is another td or a qh. 0 = td 1 = qh 0 terminate (t). this bit indicates to the intel ? ich5 that this is the last qh in the schedule. if there are active tds in this queue, they are the last to be executed in this frame. 0 = pointer is valid (points to a qh or td). 1 = last qh (pointer is invalid). table 88. queue element link pointer bit description 31:4 queue element link pointer (qelp). this field contains the address of the next td or qh to be processed in this queue and corresponds to memory address signals [31:4], respectively. 3:2 reserved. 1 qh/td select (q). this bit indicates to the hardware whether the item referenced by the link pointer is another td or a qh. for entries in a queue, this bit is typically set to 0. 0 = td 1 = qh 0 terminate (t). this bit indicates to the intel ? ich5 that there are no valid tds in this queue. when hcd has new queue entries it overwrites this value with a new td pointer to the queue entry. 0 = pointer is valid. 1 = terminate (no valid queue entries). 198 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.19.2 data transfers to/from main memory the following sections describe the details on how hcd and the ich5 communicate via the schedule data structures. the discussion is organized in a top-down manner, beginning with the basics of walking the frame list, followed by a description of generic processing steps common to all transfer descriptors, and finally a discussion on transfer queuing. 5.19.2.1 executing the schedule software programs the ich5 with the starting address of the frame list and the frame list index, then causes the ich5 to execute the schedule by setting the run/stop bit in the control register to run. the ich5 processes the schedule one entry at a time: the next element in the frame list is not fetched until the current element in the frame list is retired. schedule execution proceeds in the following fashion: ? the ich5 first fetches an entry from the frame list. this entry has three fields. bit 0 indicates whether the address pointer field is valid. bit 1 indicates whether the address points to a transfer descriptor or to a queue head. the third field is the pointer itself. ? if isochronous traffic is to be moved in a given frame, the frame list entry points to a transfer descriptor. if no isochronous data is to be moved in that frame, the entry points to a queue head or the entry is marked invalid and no transfers are initiated in that frame. ? if the frame list entry indicates that it points to a transfer descriptor, the ich5 fetches the entry and begins the operations necessary to initiate a transaction on usb. each td contains a link field that points to the next entry, as well as indicating whether it is a td or a qh. ? if the frame list entry contains a pointer to a qh, the ich5 processes the information from the qh to determine the address of the next data object that it should process. ? the td/qh process continues until the millisecond allotted to the current frame expires. at this point, the ich5 fetches the next entry from the frame list. if the ich5 is not able to process all of the transfer descriptors during a given frame, those descriptors are retired by software without having been executed. intel ? 82801eb ich5 / 82801er ich5r datasheet 199 functional description 5.19.2.2 processing transfer descriptors the ich5 executes a td using the following generalized algorithm. these basic steps are common across all modes of tds. subsequent sections present processing steps unique to each td mode. 1. ich5 fetches td or qh from the current link pointer. 2. if a qh, go to 1 to fetch from the queue element link pointer. if inactive, go to 12 3. build token, actual bits are in td token. 4. if (host-to-function) then [ memory access ] issue request for data, (referenced through td.bufferpointer) wait for first chunk data arrival end if 5. [ begin usb transaction ] issue token (from token built in 2, above) and begin data transfer. if (host-to-function) then go to 6 else go to 7 end if 6. fetch data from memory (via td bufferpointer) and transfer over usb until td max-length bytes have been read and transferred. [ concurrent system memory and usb accesses ]. go to 8. 7. wait for data to arrive (from usb). write incoming bytes into memory beginning at td bufferpointer. internal hc buffer should signal end of data packet. number of bytes received must be (td max-length; the length of the memory area referenced by td bufferpointer must be (td max-length. [ concurrent system memory and usb accesses ]. 8. issue handshake based on status of data received (ack or time-out). go to 10. 9. wait for handshake, if required [ end of usb transaction ]. 10. update status [ memory access ] (td.status and td.actuallength). if the td was an isochronous td, mark the td inactive. go to 12. if not an isochronous td, and the td completed successfully, mark the td inactive. go to 11. if not successful, and the error count has not been reached, leave the td active. if the error count has been reached, mark the td inactive. go to 12. 11. write the link pointer from the current td into the element pointer field of the qh structure. if the vf bit is set in the td link pointer, go to 2. 12. proceed to next entry. 200 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.19.2.3 command register, status register, and td status bit interaction notes: 1. only if error counter counted down from 1 to 0 2. suspend mode can be entered only when run/stop bit is 0 note that if a nak or stall response is received from a setup transaction, a time out error is reported. this causes the error counter to decrement and the crc/time-out error status bit to be set within the td control and status dword during write back. if the error counter changes from 1 to 0, the active bit will be reset to 0 and stalled bit to 1 as normal. 5.19.2.4 transfer queuing transfer queues are used to implement a guaranteed data delivery stream to a usb endpoint. transfer queues are composed of two parts: a queue header (qh) and a linked list. the linked list of tds and qhs has an indeterminate length (0 to n). the qh contains two link pointers and is organized as two contiguous dwords. the first dword is a horizontal pointer (queue head link pointer), used to link a single transfer queue with either another transfer queue, or a td (target data structure depends on q bit). if the t bit is set, this qh table 89. command register, status register and td status bit interaction condition intel ? ich5 usb status register actions td status register actions crc/time out error set usb error int bit 1 , clear hc halted bit clear active bit 1 and set stall bit 1 illegal pid, pid error, max length (illegal) clear run/stop bit in command register set hc process error and hc halted bits pci master/target abort clear run/stop bit in command register set host system error and hc halted bits suspend mode clear run/stop bit in command register 2 set hc halted bit resume received and suspend mode = 1 set resume received bit run/stop = 0 clear run/stop bit in command register set hc halted bit config flag set set config flag in command register hc reset/global reset clear run/stop and config flag in command register clear usb int, usb error int, resume received, host system error, hc process error, and hc halted bits ioc = 1 in td status set usb int bit stall set usb error int bit clear active bit 1 and set stall bit bit stuff/data buffer error set usb error int bit 1 clear active bit 1 and set stall bit 1 short packet detect set usb int bit clear active bit intel ? 82801eb ich5 / 82801er ich5r datasheet 201 functional description represents the last data structure in the current frame. the t bit informs the ich5 that no further processing is required until the beginning of the next frame. the second dword is a vertical pointer (queue element link pointer) to the first data structure (td or qh) being managed by this qh. if the t bit is set, the queue is empty. this pointer may reference a td or another qh. figure 21 illustrates four example queue conditions. the first qh (on far left) is an example of an ?empty? queue; the termination bit (t bit), in the vertical link pointer field, is set to 1. the horizontal link pointer references another qh. the next queue is the expected typical configuration. the horizontal link pointer references another qh, and the vertical link pointer references a valid td. typically, the vertical pointer in a qh points to a td. however, as shown in figure 21 (third example from left side of figure) the vertical pointer could point to another qh. when this occurs, a new q context is entered and the q context just exited is null (ich5 will not update the vertical pointer field). the far right qh is an example of a frame ?termination? node. since its horizontal link pointer has its termination bit set, the ich5 assumes there is no more work to complete for the current frame. transfer queues are based on the following characteristics: ? a qh?s vertical link pointer (queue element link pointer) references the ?top? queue member. a qh?s horizontal link pointer (queue head link pointer) references the ?next? work element in the frame. ? each queue member?s link pointer references the next element within the queue. in the simplest model, the ich5 follows vertical link point to a queue element, then executes the element. if the completion status of the td satisfies the advance criteria as shown in table 90 , the ich5 advances the queue by writing the just-executed td?s link pointer back into the qh?s queue element link pointer. the next time the queue head is traversed, the next queue element will be the top element. figure 21. example queue conditions frame list pointer qt 0 1 2 31 link pointer (horiz) qt 0 1 2 31 link pointer (vert) q t indicates 'null' queue head link pointer qt td qh link pointer qt td link pointer qt td indicates 'nil' next pointer indicates 'nil' next pointer qh link pointer (horiz) qt 0 1 2 31 link pointer (vert) q t qh link pointer (horiz) qt 0 1 2 31 link pointer (vert) q t qh link pointer (horiz) qt 0 1 2 31 link pointer (vert) q t qh link pointer (horiz) qt 0 1 2 31 link pointer (vert) q t link pointer qt td link pointer qt td link pointer (horz z )=queue head link pointer field in qh dword 0 link pointer (vert)=queue element link pointer field in qh dword 1 202 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description the traversal has two options: breadth first, or depth first. a flag bit in each td (vf ? vertical traversal flag) controls whether traversal is breadth or depth first. the default mode of traversal is breadth-first. for breadth-first, the ich5 only executes the top element from each queue. the execution path is shown below: 1. qh (queue element link pointer) 2. td 3. write-back to qh (queue element link pointer) 4. qh (queue head link pointer). breadth-first is also performed for every transaction execution that fails the advance criteria. this means that if a queued td fails, the queue does not advance, and the ich5 traverses the qh?s queue head link pointer. in a depth-first traversal, the top queue element must complete successfully to satisfy the advance criteria for the queue. if the ich5 is currently processing a queue, and the advance criteria are met, and the vf bit is set, the ich5 follows the td?s link pointer to the next schedule work item. note that regardless of traversal model, when the advance criteria are met, the successful td?s link pointer is written back to the qh?s queue element link pointer. when the ich5 encounters a qh, it caches the qh internally, and sets internal state to indicate it is in a q-context. it needs this state to update the correct qh (for auto advancement) and also to make the correct decisions on how to traverse the frame list. restricting the advancement of queues to advancement criteria implements a guaranteed data delivery stream. a queue is never advanced on an error completion status (even in the event the error count was exhausted). table 90 lists the general queue advance criteria, which are based on the execution status of the td at the ?top? of a currently ?active? queue. table 91 is a decision table illustrating the valid combinations of link pointer bits and the valid actions taken when advancement criteria for a queued transfer descriptor are met. the column headings for the link pointer fields are encoded, based on the following list: table 90. queue advance criteria function-to-host (in) host-to-function (out) non-null null error/nak non-null null error/nak advance q advance q retry q element advance q advance q retry q element intel ? 82801eb ich5 / 82801er ich5r datasheet 203 functional description legends: qh.lp = queue head link pointer (or horizontal link pointer) qe.q = q bit in qe qe.lp = queue element link pointer (or vertical link pointer) qe.t = t bit in qe td.lp = td link pointer td. vf = vf bit in td qh.q = q bit in qh td.q = q bit in td qh.t = t bit in qh td. t = t bit in td q t qhlp qh qt qelp qe vf tdlp td vf q t table 91. usb schedule list traversal decision table q context qh.q qh.t qe.q qe.t td.vf td.q td.t description 0????x00 ? not in queue ? execute td. ? use td.lp to get next td 0????xx1 ? not in queue ? execute td. end of frame 0????x10 ? not in queue ? execute td. ? use td.lp to get next (qh+qe). ? set q context to 1. 100000xx ? in queue. use qe.lp to get td. ? execute td. update qe.lp with td.lp. ? use qh.lp to get next td. 1xx00100 ? in queue. use qe.lp to get td. ? execute td. update qe.lp with td.lp. ? use td.lp to get next td. 1xx00110 ? in queue. use qe.lp to get td. ? execute td. update qe.lp with td.lp. ? use td.lp to get next (qh+qe). 100x1xxx ? in queue. empty queue. ? use qh.lp to get next td 1 x x 1 0 ? ? ? ? in queue. use qe.lp to get (qh+qe) 1x1000xx ? in queue. use qe.lp to get td. ? execute td. update qe.lp with td.lp. ? end of frame 1 x 1 x 1 x x x ? in queue. empty queue. end of frame 110000xx ? in queue. use qe.lp to get td. ? execute td. update qe.lp with td.lp. ? use qh.lp to get next (qh+qe). 110x1xxx ? in queue. empty queue. ? use qh.lp to get next (qh+qe) 204 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.19.3 data encoding and bit stuffing the usb employs nrzi data encoding (non-return to zero inverted) when transmitting packets. in nrzi encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. a string of 0s causes the nrzi data to toggle each bit time. a string of 1s causes long periods with no transitions in the data. in order to ensure adequate signal transitions, bit stuffing is employed by the transmitting device when sending a packet on the usb. a 0 is inserted after every six, consecutive, 1s in the data stream before the data is nrzi encoded to force a transition in the nrzi data stream. this gives the receiver logic a data transition at least once every seven bit times to guarantee the data and clock lock. a waveform of the data encoding is shown in figure 22 . bit stuffing is enabled beginning with the sync pattern and throughout the entire transmission. the data 1 that ends the sync pattern is counted as the first one in a sequence. bit stuffing is always enforced, without exception. if required by the bit stuffing rules, a 0 bit is inserted even if it is the last bit before the end-of-packet (eop) signal. 5.19.4 bus protocol 5.19.4.1 bit ordering bits are sent out onto the bus least significant bit (lsb) first, followed by next lsb, through to the most significant bit (msb) last. 5.19.4.2 sync field all packets begin with a synchronization (sync) field, which is a coded sequence that generates a maximum edge transition density. the sync field appears on the bus as idle followed by the binary string ?kjkjkjkk,? in its nrzi encoding. it is used by the input circuitry to align incoming data with the local clock and is defined to be 8 bits in length. sync serves only as a synchronization mechanism and is not shown in the following packet diagrams. the last two bits in the sync field are a marker that is used to identify the first bit of the pid. all subsequent bits in the packet must be indexed from this point. figure 22. usb data encoding clock data bit stuffed data nrzi data intel ? 82801eb ich5 / 82801er ich5r datasheet 205 functional description 5.19.4.3 packet field formats field formats for the token, data, and handshake packets are described in the following section. the effects of nrzi coding and bit stuffing have been removed for the sake of clarity. all packets have distinct start and end of packet delimiters. packet identifier field a packet identifier (pid) immediately follows the sync field of every usb packet. a pid consists of a four bit packet type field followed by a four-bit check field as shown in table 92 . the pid indicates the type of packet and, by inference, the format of the packet and the type of error detection applied to the packet. the four-bit check field of the pid insures reliable decoding of the pid so that the remainder of the packet is interpreted correctly. the pid check field is generated by performing a 1s complement of the packet type field. any pid received with a failed check field or which decodes to a non-defined value is assumed to be corrupted and the remainder of the packet is assumed to be corrupted and is ignored by the receiver. pid types, codes, and descriptions are listed in table 93 . pids are divided into four coding groups: token, data, handshake, and special, with the first two transmitted pid bits (pid[1:0]) indicating which group. this accounts for the distribution of pid codes. table 92. pid format bit data sent bit data sent 0pid 04not(pid 0) 1pid 15not(pid 1) 2pid 26not(pid 2) 3pid 37not(pid 3) table 93. pid types pid type pid name pid[3:0] description token out b0001 address + endpoint number in host -> function transaction in b1001 address + endpoint number in function -> host transaction sof b0101 start of frame marker and frame number setup b1101 address + endpoint number in host -> function transaction for setup to a control endpoint data data0 b0011 data packet pid even data1 b1011 data packet pid odd handshake ack b0010 receiver accepts error free data packet nak b1010 rx device cannot accept data or tx device cannot send data stall b1110 endpoint is stalled special pre b1100 host-issued preamble. enables downstream bus traffic to low speed devices. 206 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.19.4.4 address fields function endpoints are addressed using the function address field and the endpoint field. address field the function address (addr) field specifies the function, via its address, that is either the source or destination of a data packet, depending on the value of the token pid. as shown in table 94 , a total of 128 addresses are specified as addr[6:0]. the addr field is specified for in, setup, and out tokens. endpoint field an additional four-bit endpoint (endp) field, shown in table 95 , permits more flexible addressing of functions in which more than one sub-channel is required. endpoint numbers are function specific. the endpoint field is defined for in, setup, and out token pids only. 5.19.4.5 frame number field the frame number field is an 11-bit field that is incremented by the host on a per frame basis. the frame number field rolls over upon reaching its maximum value of x7ff, and is sent only for sof tokens at the start of each frame. 5.19.4.6 data field the data field may range from 0 to 1023 bytes and must be an integral numbers of bytes. data bits within each byte are shifted out lsb first. 5.19.4.7 cyclic redundancy check (crc) crc is used to protect the all non-pid fields in token and data packets. in this context, these fields are considered to be protected fields. the pid is not included in the crc check of a packet containing crc. all crcs are generated over their respective fields in the transmitter before bit stuffing is performed. similarly, crcs are decoded in the receiver after stuffed bits have been removed. token and data packet crcs provide 100% coverage for all single and double bit errors. a failed crc is considered to indicate that one or more of the protected fields is corrupted and causes the receiver to ignore those fields, and, in most cases, the entire packet. table 94. address field bit data sent bit data sent 0 addr 0 4 addr 4 1 addr 1 5 addr 5 2 addr 2 6 addr 6 3 addr 3 table 95. endpoint field bit data sent 0 endp 0 1 endp 1 2 endp 2 3 endp 3 intel ? 82801eb ich5 / 82801er ich5r datasheet 207 functional description 5.19.5 packet formats 5.19.5.1 token packets table 96 shows the field formats for a token packet. a token consists of a pid, specifying either in, out, or setup packet type, and addr and endp fields. for out and setup transactions, the address and endpoint fields uniquely identify the endpoint that will receive the subsequent data packet. for in transactions, these fields uniquely identify which endpoint should transmit a data packet. only the ich5 can issue token packets. in pids define a data transaction from a function to the ich5. out and setup pids define data transactions from the ich5 to a function. token packets have a five-bit crc which covers the address and endpoint fields as shown above. the crc does not cover the pid, which has its own check field. token and sof packets are delimited by an eop after three bytes of packet field data. if a packet decodes as an otherwise valid token or sof but does not terminate with an eop after three bytes, it must be considered invalid and ignored by the receiver. 5.19.5.2 start of frame packets table 97 shows a start of frame (sof) packet. sof packets are issued by the host at a nominal rate of once every 1.00 ms 0.05. sof packets consist of a pid indicating packet type followed by an 11-bit frame number field. the sof token comprises the token-only transaction that distributes a start of frame marker and accompanying frame number at precisely timed intervals corresponding to the start of each frame. all full speed functions, including hubs, must receive and decode the sof packet. the sof token does not cause any receiving function to generate a return packet; therefore, sof delivery to any given function cannot be guaranteed. the sof packet delivers two pieces of timing information. a function is informed that a start of frame has occurred when it detects the sof pid. frame timing sensitive functions, which do not need to keep track of frame number, need only decode the sof pid; they can ignore the frame number and its crc. if a function needs to track frame number, it must comprehend both the pid and the time stamp. table 96. token format packet width pid 8 bits addr 7 bits endp 4 bits crc5 5 bits table 97. sof packet packet width pid 8 bits frame number 11 bits crc5 5 bits 208 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.19.5.3 data packets a data packet consists of a pid, a data field, and a crc as shown in table 98 . there are two types of data packets, identified by differing pids: data0 and data1. two data packet pids are defined to support data toggle synchronization. data must always be sent in integral numbers of bytes. the data crc is computed over only the data field in the packet and does not include the pid, which has its own check field. 5.19.5.4 handshake packets handshake packets consist of only a pid. handshake packets are used to report the status of a data transaction and can return values indicating successful reception of data, flow control, and stall conditions. only transaction types that support flow control can return handshakes. handshakes are always returned in the handshake phase of a transaction and may be returned, instead of data, in the data phase. handshake packets are delimited by an eop after one byte of packet field. if a packet is decoded as an otherwise valid handshake but does not terminate with an eop after one byte, it must be considered invalid and ignored by the receiver. there are three types of handshake packets: ? ack indicates that the data packet was received without bit stuff or crc errors over the data field and that the data pid was received correctly. an ack handshake is applicable only in transactions in which data has been transmitted and where a handshake is expected. ack can be returned by the host for in transactions and by a function for out transactions. ? nak indicates that a function was unable to accept data from the host (out) or that a function has no data to transmit to the host (in). nak can only be returned by functions in the data phase of in transactions or the handshake phase of out transactions. the host can never issue a nak. nak is used for flow control purposes to indicate that a function is temporarily unable to transmit or receive data, but will eventually be able to do so without need of host intervention. nak is also used by interrupt endpoints to indicate that no interrupt is pending. ? stall is returned by a function in response to an in token or after the data phase of an out. stall indicates that a function is unable to transmit or receive data, and that the condition requires host intervention to remove the stall. once a function?s endpoint is stalled, the function must continue returning stall until the condition causing the stall has been cleared through host intervention. the host is not permitted to return a stall under any condition. table 98. data packet format packet width pid 8 bits data 0?1023 bytes crc16 16 bits intel ? 82801eb ich5 / 82801er ich5r datasheet 209 functional description 5.19.5.5 handshake responses in transaction a function may respond to an in transaction with a stall or nak. if the token received was corrupted, the function issues no response. if the function can transmit data, it issues the data packet. the ich5, as the usb host, can return only one type of handshake on an in transaction, an ack. if it receives a corrupted data, or cannot accept data due to a condition such as an internal buffer overrun, it discards the data and issues no response. out transaction a function may respond to an out transaction with a stall, ack, or nak. if the transaction contained corrupted data, it issues no response. setup transaction setup defines a special type of host to function data transaction which permits the host to initialize an endpoint?s synchronization bits to those of the host. upon receiving a setup transaction, a function must accept the data. setup transactions cannot be stalled or naked and the receiving function must accept the setup transfer?s data. if a non-control endpoint receives a setup pid, it must ignore the transaction and return no response. 5.19.6 usb interrupts there are two general groups of usb interrupt sources, those resulting from execution of transactions in the schedule, and those resulting from an ich5 operation error. all transaction-based sources can be masked by software through the ich5?s interrupt enable register. additionally, individual transfer descriptors can be marked to generate an interrupt on completion. when the ich5 drives an interrupt for usb, it internally drives the pirqa# pin for usb function #0 and usb function #3, pirqd# pin for usb function #1, and the pirqc# pin for usb function #2, until all sources of the interrupt are cleared. in order to accommodate some operating systems, the interrupt pin register must contain a different value for each function of this new multi-function device. 5.19.6.1 transaction based interrupts these interrupts are not signaled until after the status for the last complete transaction in the frame has been written back to host memory. this guarantees that software can safely process through (frame list current index -1) when it is servicing an interrupt. crc error / time-out a crc/time-out error occurs when a packet transmitted from the ich5 to a usb device or a packet transmitted from a usb device to the ich5 generates a crc error. the ich5 is informed of this event by a time-out from the usb device or by the ich5?s crc checker generating an error on reception of the packet. additionally, a usb bus time-out occurs when usb devices do not respond to a transaction phase within 19-bit times of an eop. either of these conditions causes the c_err field of the td to decrement. 210 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description when the c_err field decrements to 0, the following occurs: ? the active bit in the td is cleared ? the stalled bit in the td is set ? the crc/time-out bit in the td is set. ? at the end of the frame, the usb error interrupt bit is set in the hc status register. if the crc/time out interrupt is enabled in the interrupt enable register, a hardware interrupt will be signaled to the system. interrupt on completion transfer descriptors contain a bit that can be set to cause an interrupt on their completion. the completion of the transaction associated with that block causes the usb interrupt bit in the hc status register to be set at the end of the frame in which the transfer completed. when a td is encountered with the ioc bit set to 1, the ioc bit in the hc status register is set to 1 at the end of the frame if the active bit in the td is set to 0 (even if it was set to 0 when initially read). if the ioc enable bit of interrupt enable register (bit 2 of i/o offset 04h) is set, a hardware interrupt is signaled to the system. the usb interrupt bit in the hc status register is set either when the td completes successfully or because of errors. if the completion is because of errors, the usb error bit in the hc status register is also set. short packet detect a transfer set is a collection of data which requires more than one usb transaction to completely move the data across the usb. an example might be a large print file which requires numerous tds in multiple frames to completely transfer the data. reception of a data packet that is less than the endpoint?s max packet size during control, bulk or interrupt transfers signals the completion of the transfer set, even if there are active tds remaining for this transfer set. setting the spd bit in a td indicates to the hc to set the usb interrupt bit in the hc status register at the end of the frame in which this event occurs. this feature streamlines the processing of input on these transfer types. if the short packet interrupt enable bit in the interrupt enable register is set, a hardware interrupt is signaled to the system at the end of the frame where the event occurred. serial bus babble when a device transmits on the usb for a time greater than its assigned max length, it is said to be babbling. since isochrony can be destroyed by a babbling device, this error results in the active bit in the td being cleared to 0 and the stalled and babble bits being set to one. the c_err field is not decremented for a babble. the usb error interrupt bit in the hc status register is set to 1 at the end of the frame. a hardware interrupt is signaled to the system. if an eof babble was caused by the ich5 (due to incorrect schedule for instance), the ich5 forces a bit stuff error followed by an eop and the start of the next frame. stalled this event indicates that a device/endpoint returned a stall handshake during a transaction or that the transaction ended in an error condition. the tds stalled bit is set and the active bit is cleared. reception of a stall does not decrement the error counter. a hardware interrupt is signaled to the system. intel ? 82801eb ich5 / 82801er ich5r datasheet 211 functional description data buffer error this event indicates that an overrun of incoming data or a under-run of outgoing data has occurred for this transaction. this would generally be caused by the ich5 not being able to access required data buffers in memory within necessary latency requirements. either of these conditions causes the c_err field of the td to be decremented. when c_err decrements to 0, the active bit in the td is cleared, the stalled bit is set, the usb error interrupt bit in the hc status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. bit stuff error a bit stuff error results from the detection of a sequence of more that six 1s in a row within the incoming data stream. this causes the c_err field of the td to be decremented. when the c_err field decrements to 0, the active bit in the td is cleared to 0, the stalled bit is set to 1, the usb error interrupt bit in the hc status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. 5.19.6.2 non-transaction based interrupts if an ich5 process error or system error occur, the ich5 halts and immediately issues a hardware interrupt to the system. resume received this event indicates that the ich5 received a resume signal from a device on the usb bus during a global suspend. if this interrupt is enabled in the interrupt enable register, a hardware interrupt is signaled to the system allowing the usb to be brought out of the suspend state and returned to normal operation. ich5 process error the hc monitors certain critical fields during operation to ensure that it does not process corrupted data structures. these include checking for a valid pid and verifying that the maxlength field is less than 1280. if it detects a condition that would indicate that it is processing corrupted data structures, it immediately halts processing, sets the hc process error bit in the hc status register and signals a hardware interrupt to the system. this interrupt cannot be disabled through the interrupt enable register. host system error the ich5 sets this bit to 1 when a parity error, master abort, or target abort occur. when this error occurs, the ich5 clears the run/stop bit in the command register to prevent further execution of the scheduled tds. this interrupt cannot be disabled through the interrupt enable register. 212 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.19.7 usb power management the host controller can be put into a suspended state and its power can be removed. this requires that certain bits of information are retained in the resume power plane of the ich5 so that a device on a port may wake the system. such a device may be a fax-modem, which will wake up the machine to receive a fax or take a voice message. the settings of the following bits in i/o space will be maintained when the ich5 enters the s3, s4, or s5 states. when the ich5 detects a resume event on any of its ports, it sets the corresponding usb_sts bit in acpi space. if usb is enabled as a wake/break event, the system wakes up and an sci generated. 5.19.8 usb legacy keyboard operation when a usb keyboard is plugged into the system, and a standard keyboard is not, the system may not boot, and ms-dos legacy software will not run, because the keyboard will not be identified. the ich5 implements a series of trapping operations which will snoop accesses that go to the keyboard controller, and put the expected data from the usb keyboard into the keyboard controller. note: the scheme described below assumes that the keyboard controller (8042 or equivalent) is on the lpc bus. this legacy operation is performed through smm space. figure 23 shows the enable and status path. the latched smi source (60r, 60w, 64r, 64w) is available in the status register. because the enable is after the latch, it is possible to check for other events that didn't necessarily cause an smi. it is the software's responsibility to logically and the value with the appropriate enable bits. note also that the smi is generated before the pci cycle completes (e.g., before trdy# goes active) to ensure that the processor doesn't complete the cycle before the smi is observed. this method is used on mpiix and has been validated. the logic also needs to block the accesses to the 8042. if there is an external 8042, then this is simply accomplished by not activating the 8042 cs. this is simply done by logically anding the four enables (60r, 60w, 64r, 64w) with the 4 types of accesses to determine if 8042cs should go active. an additional term is required for the ?pass-through? case. table 99. bits maintained in low power states register offset bit description command 00h 3 enter global suspend mode (egsm) status 02h 2 resume detect port status and control 10h & 12h 2 port enabled/disabled 6 resume detect 8 low speed device attached 12 suspend intel ? 82801eb ich5 / 82801er ich5r datasheet 213 functional description the state table for the diagram is shown in table 100 . figure 23. usb legacy keyboard flow diagram kbc accesses pci config read, write 60 read clear smi_60_r en_smi_on_60r comb. decoder and same for 60w, 64r, 64w smi or to individual "caused by" "bits" to pirqd# to "caused by" bit and and en_pirqd# usb_irq clear usb_irq en_smi_on_irq s d r s d r 214 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description table 100. usb legacy keyboard state transitions current state action data value next state comment idle 64h / write d1h gatestate1 standard d1 command. cycle passed through to 8042. smi# doesn't go active. pstate (offset c0, bit 6) goes to 1. idle 64h / write not d1h idle bit 3 in config register determines if cycle passed through to 8042 and if smi# generated. idle 64h / read n/a idle bit 2 in config register determines if cycle passed through to 8042 and if smi# generated. idle 60h / write don't care idle bit 1 in config register determines if cycle passed through to 8042 and if smi# generated. idle 60h / read n/a idle bit 0 in config register determines if cycle passed through to 8042 and if smi# generated. gatestate1 60h / write xxh gatestate2 cycle passed through to 8042, even if trap enabled in bit 1 in config register. no smi# generated. pstate remains 1. if data value is not dfh or ddh then the 8042 may chose to ignore it. gatestate1 64h / write d1h gatestate1 cycle passed through to 8042, even if trap enabled via bit 3 in config register. no smi# generated. pstate remains 1. stay in gatestate1 because this is part of the double-trigger sequence. gatestate1 64h / write not d1h ilde bit 3 in config space determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in config register is set, then smi# should be generated. gatestate1 60h / read n/a idle this is an invalid sequence. bit 0 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in config register is set, then smi# should be generated. gatestate1 64h / read n/a gatestate1 just stay in same state. generate an smi# if enabled in bit 2 of config register. pstate remains 1. gatestate2 64 / write ffh idle standard end of sequence. cycle passed through to 8042. pstate goes to 0. bit 7 in config space determines if smi# should be generated. gatestate2 64h / write not ffh idle improper end of sequence. bit 3 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in config register is set, then smi# should be generated. gatestate2 64h / read n/a gatestate2 just stay in same state. generate an smi# if enabled in bit 2 of config register. pstate remains 1. gatestate2 60h / write xxh idle improper end of sequence. bit 1 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in config register is set, then smi# should be generated. gatestate2 60h / read n/a idle improper end of sequence. bit 0 in config register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in config register is set, then smi# should be generated. intel ? 82801eb ich5 / 82801er ich5r datasheet 215 functional description 5.20 usb ehci host controller (d29:f7) the ich5 contains an enhanced host controller interface (ehci) compliant host controller which supports up to eight usb 2.0 high speed compliant root ports. usb 2.0 allows data transfers up to 480 mbps using the same pins as the eight usb full speed/low speed ports. the ich5 contains port-routing logic that determines whether a usb port is controlled by one of the uhci controllers or by the ehci controller. usb 2.0 based debug port is also implemented in the ich5. a summary of the key architectural differences between the usb uhci host controllers and the ehci host controller are shown in table 101 . 5.20.1 ehc initialization the following descriptions step through the expected ich5 enhanced host controller (ehc) initialization sequence in chronological order, beginning with a complete power cycle in which the suspend well and core well have been off. 5.20.1.1 power on the suspend well is a ?deeper? power plane than the core well, which means that the suspend well is always functional when the core well is functional but the core well may not be functional when the suspend well is. therefore, the suspend well reset pin (rsmrst#) deasserts before the core well reset pin (pwrok) rises. 1. the suspend well reset deasserts, leaving all registers and logic in the suspend well in the default state. however, it is not possible to read any registers until after the core well reset deasserts. note that normally the suspend well reset only occurs when a system is unplugged. in other words, suspend well resets are not easily achieved by software or the end-user. this step will typically not occur immediately before the remaining steps. 2. the core well reset deasserts, leaving all registers and logic in the core well in the default state. the ehc configuration space is accessible at this point. note that the core well reset can (and typically does) occur without the suspend well reset asserting. this means that all of the configure flag and port status and control bits (and any other suspend-well logic) may be in any valid state at this time. 5.20.1.2 bios initialization bios performs a number of platform customization steps after the core well has powered up. contact your intel field representative for additional ich5 bios information. table 101. uhci vs. ehci parameter usb uhci usb ehci accessible by i/o space memory space memory data structure single linked list separated in to periodic and asynchronous lists differential signaling voltage 3.3 v 400 mv ports per controller 2 8 216 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.20.1.3 driver initialization see chapter 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 . 5.20.1.4 ehc resets in addition to the standard ich5 hardware resets, portions of the ehc are reset by the hcreset bit and the transition from the d3hot device power management state to the d0 state. the effects of each of these resets are: if the detailed register descriptions give exceptions to these rules, those exceptions override these rules. this summary is provided to help explain the reasons for the reset policies. 5.20.2 data structures in main memory see section 3 and appendix b of the enhanced host controller interface specification for universal serial bus, revision 1.0 for details. 5.20.3 usb 2.0 enhanced host controller dma the ich5 usb 2.0 ehc implements three sources of usb packets. they are, in order of priority on usb during each microframe, 1) the usb 2.0 debug port (see section usb 2.0 based debug port), 2) the periodic dma engine, and 3) the asynchronous dma engine. the ich5 always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. if there is time left in the microframe, then the ehc performs any pending asynchronous traffic until the end of the microframe (eof1). note that the debug port traffic is only presented on one port (port #0), while the other ports are idle during this time. the following subsections describe the policies of the periodic and asynchronous dma engines. 5.20.3.1 periodic list execution the periodic dma engine contains buffering for two control structures (two transactions). by implementing two entries, the ehc is able to pipeline the memory accesses for the next transaction while executing the current transaction on the usb ports. note that a multiple-packet, high-bandwidth transaction occupies one of these buffer entries, which means that up to six, 1-kb data packets may be associated with the two buffered control structures. reset does reset does not reset comments hcreset bit set. memory space registers except structural parameters (which is written by bios). configuration registers. the hcreset must only affect registers that the ehci driver controls. pci configuration space and bios-programmed parameters can not be reset. software writes the device power state from d3hot (11b) to d0 (00b). core well registers (except bios- programmed registers). suspend well registers; bios- programmed core well registers. the d3-to-d0 transition must not cause wake information (suspend well) to be lost. it also must not clear bios-programmed registers because bios may not be invoked following the d3-to-d0 transition. intel ? 82801eb ich5 / 82801er ich5r datasheet 217 functional description 5.20.3.1.1 read policies for periodic dma the periodic dma engine performs reads for the following structures. the ehc periodic dma engine (pde) does not generate accesses to main memory unless all three of the following conditions are met. ? the hchalted bit is 0 (memory space, offset 24h, bit 12). software clears this bit indirectly by setting the run/stop bit to 1. ? the periodic schedule status bit is 1 (memory space, offset 24h, bit 14). software sets this bit indirectly by setting the periodic schedule enable bit to 1. ? the bus master enable bit is 1 (configuration space, offset 04h, bit 2). note: prefetching is limited to the current and next microframes only. note: once the pde checks the length of a periodic packet against the remaining time in the microframe (late-start check) and decides that there is not enough time to run it on the wire, then the ehc switches over to run asynchronous traffic. memory structure size (dwords) comments periodic frame list entry 1 the ehc reads the entry for each microframe. the frame list is not internally cached across microframes. itd 23 only the 64-bit addressing format is supported. sitd 9 only the 64-bit addressing format is supported. qtd 13 only the 64-bit addressing format is supported. queue head 17 only the 64-bit addressing format is supported. out data up to 257 the intel ? ich5 breaks large read requests down into smaller aligned read requests based on the setting of the read request max length field. frame span transversal node 2 218 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.20.3.1.2 write policies for periodic dma the periodic dma engine performs writes for the following reasons: notes: 1. the periodic dma engine (pde) will only generate writes after a transaction is executed on usb. 2. status writes are always performed after in data writes for the same transaction. 5.20.3.2 asynchronous list execution the asynchronous dma engine contains buffering for two control structures (two transactions). by implementing two entries, the ehc is able to pipeline the memory accesses for the next transaction while executing the current transaction on the usb ports. 5.20.3.2.1 read policies for asynchronous dma the asynchronous dma engine performs reads for the following structures. the ehc asynchronous dma engine (ade) does not generate accesses to main memory unless all four of the following conditions are met. (note that the ade may be active when the periodic schedule is actively executed, unlike the description in the enhanced host controller interface specification for universal serial bus, revision 1.0 ; since the ehc contains independent dma engines, the ade may perform memory accesses interleaved with the pde accesses.) ? the hchalted bit is 0 (memory space, offset 24h, bit 12). software clears this bit indirectly by setting the run/stop bit to 1. ? the asynchronous schedule status bit is 1 (memory space, offset 24h, bit 14). software sets this bit indirectly by setting the asynchronous schedule enable bit to 1. ? the bus master enable bit is 1 (configuration space, offset 04h, bit 2). ? the ade is not sleeping due to the detection of an empty schedule. there is not one single bit that indicates this state. however, the sleeping state is entered when the queue head with the h bit set is encountered when the reclamation bit in the usb 2.0 status register is 0. memory structure size (dwords) comments itd status write 1 only the dword that corresponds to the just-executed microframe?s status is written. all bytes of the dword are written. sitd status write 3 dwords 0c:17h are written. ioc and buffer pointer fields are re-written with the original value. interrupt queue head overlay 14 only the 64-bit addressing format is supported. dwords 0c:43h are written. interrupt queue head status write 54 dwords 14:27h are written. interrupt qtd status write 3 dwords 04:0fh are written. pid code, ioc, buffer pointers, and alt. next qtd pointers are re-written with the original value. in data up to 257 the intel ? ich5 breaks data writes down into 16 dword aligned chunks. memory structure size (dw) comments qtd 13 only the 64-bit addressing format is supported. queue head 17 only the 64-bit addressing format is supported. out data up to 129 the intel ? ich5 breaks large read requests down in to smaller aligned read requests based on the setting of the read request max length field. intel ? 82801eb ich5 / 82801er ich5r datasheet 219 functional description note: the ade does not fetch data when a qh is encountered in the ping state. an ack handshake in response to the ping results in the ade writing the qh to the out state, which results in the fetching and delivery of the out data on the next iteration through the asynchronous list. note: once the ade checks the length of an asynchronous packet against the remaining time in the microframe (late-start check) and decides that there is not enough time to run it on the wire, then the ehc stops all activity on the usb ports for the remainder of that microframe. note: once the ade detects an ?empty? asynchronous schedule as described in section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 , it implements a waking mechanism like the one in the example. the amount of time that the ade ?sleeps? is 10 s 30 ns. 5.20.3.2.2 write policies for asynchronous dma the asynchronous dma engine performs writes for the following reasons: notes: 1. the asynchronous dma engine (ade) will only generate writes after a transaction is executed on usb. 2. status writes are always performed after in data writes for the same transaction. 5.20.4 data encoding and bit stuffing see chapter 8 of the universal serial bus specification, revision 2.0. 5.20.5 packet formats see chapter 8 of the universal serial bus specification, revision 2.0 . memory structure size (dwords) comments asynchronous queue head overlay 14 only the 64-bit addressing format is supported. dwords 0c:43h are written. asynchronous queue head status write 34 dwords 14:1fh are written. asynchronous qtd status write 3 dwords 04:0fh are written. pid code, ioc, buffer pointer (page 0), and alt. next qtd pointers are re-written with the original value. in data up to 1297 the intel ? ich5 breaks data writes down into 16-dword aligned chunks. 220 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.20.6 usb 2.0 interrupts and error conditions section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 goes into detail on the ehc interrupts and the error conditions that cause them. all error conditions that the ehc detects can be reported through the ehci interrupt status bits. only ich5-specific interrupt and error-reporting behavior is documented in this section. the ehci interrupts section must be read first, followed by this section of the datasheet to fully comprehend the ehc interrupt and error-reporting functionality. ? based on the ehc?s buffer sizes and buffer management policies, the data buffer error can never occur on the ich5. ? master abort and target abort responses from hub interface on ehc-initiated read packets will be treated as fatal host errors. the ehc halts when these conditions are encountered. ? the ich5 may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. the requirement in the enhanced host controller interface specification for universal serial bus, revision 1.0 (that the status is written to memory) is met internally, even though the write may not be seen on the hub interface before the interrupt is asserted. ? since the ich5 supports the 1024-element frame list size, the frame list rollover interrupt occurs every 1024 milliseconds. ? the ich5 delivers interrupts using pirqh#. ? the ich5 does not modify the cerr count on an interrupt in when the ?do complete-split? execution criteria are not met. ? for complete-split transactions in the periodic list, the ?missed microframe? bit does not get set on a control-structure-fetch that fails the late-start test. if subsequent accesses to that control structure do not fail the late-start test, then the ?missed microframe? bit will get set and written back. 5.20.6.1 aborts on usb 2.0-initiated memory reads if a read initiated by the ehc is aborted, the ehc treats it as a fatal host error. the following actions are taken when this occurs: ? the host system error status bit is set ? the dma engines are halted after completing up to one more transaction on the usb interface ? if enabled (by the host system error enable), then an interrupt is generated ? if the status is master abort, then the received master abort bit in configuration space is set ? if the status is target abort, then the received target abort bit in configuration space is set ? if enabled (by the serr enable bit in the function?s configuration space), then the signaled system error bit in configuration bit is set. intel ? 82801eb ich5 / 82801er ich5r datasheet 221 functional description 5.20.7 usb 2.0 power management 5.20.7.1 pause feature this feature allows platforms (especially mobile systems) to dynamically enter low-power states during brief periods when the system is idle (i.e., between keystrokes). this is useful for enabling power management features like intel ? speedstep? technology in the ich5. the policies for entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. normally, when the ehc is enabled, it regularly accesses main memory while traversing the dma schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. suspending all of the enabled ports can prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the usb ports that makes this unacceptable for the purpose of dynamic power management. as a result, the ehci software drivers are allowed to pause the ehc?s dma engines when it knows that the traffic patterns of the attached devices can afford the delay. the pause only prevents the ehc from generating memory accesses; the sof packets continue to be generated on the usb ports (unlike the suspended state). 5.20.7.2 suspend feature the enhanced host controller interface (ehci) for universal serial bus specification , section 4.3 describes the details of port suspend and resume. 5.20.7.3 acpi device states the usb 2.0 function only supports the d0 and d3 pci power management states. notes regarding the ich5 implementation of the device states: 1. the ehc hardware does not inherently consume any more power when it is in the d0 state than it does in the d3 state. however, software is required to suspend or disable all ports prior to entering the d3 state such that the maximum power consumption is reduced. 2. in the d0 state, all implemented ehc features are enabled. 3. in the d3 state, accesses to the ehc memory-mapped i/o range will master abort. note that, since the debug port uses the same memory range, the debug port is only operational when the ehc is in the d0 state. 4. in the d3 state, the ehc interrupt must never assert for any reason. the internal pme# signal is used to signal wake events, etc. 5. when the device power state field is written to d0 from d3, an internal reset is generated. see section ehc resets for general rules on the effects of this reset. 6. attempts to write any other value into the device power state field other than 00b (d0 state) and 11b (d3 state) will complete normally without changing the current value in this field. 222 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.20.7.4 acpi system states the ehc behavior as it relates to other power management states in the system is summarized in the following list: ? the system is always in the s0 state when the ehc is in the d0 state. however, when the ehc is in the d3 state, the system may be in any power management state (including s0). ? when in d0, the pause feature (see section 5.20.7.1 ) enables dynamic processor low- power states to be entered. ? the pll in the ehc is disabled when entering the s3/s4/s5 states (core power turns off). ? all core well logic is reset in the s3/s4/s5 states (core power turns off). 5.20.8 interaction with uhci host controllers the enhanced host controller shares the eight usb ports with four uhci host controllers in the ich5. the uhc at d29:f0 shares ports 0 and 1; the uhc at d29:f1 shares ports 2 and 3; the uhc at d29:f2 shares ports 4 and 5; and the uhc at d29:f3 shares ports 6 and 7 with the ehc. there is very little interaction between the enhanced and the uhci controllers other than the muxing control which is provided as part of the ehc. figure 24 shows the usb port connections at a conceptual level. intel ? 82801eb ich5 / 82801er ich5r datasheet 223 functional description 5.20.8.1 port-routing logic integrated into the ehc functionality is port-routing logic, which performs the muxing between the uhci and ehci host controllers. the ich5 conceptually implements this logic as described in section 4.2 of the enhanced host controller interface specification for universal serial bus, revision 1.0. if a device is connected that is not capable of usb 2.0?s high speed signaling protocol or if the ehci software drivers are not present as indicated by the configured flag, then the uhci controller owns the port. owning the port means that the differential output is driven by the owner and the input stream is only visible to the owner. the host controller that is not the owner of the port internally sees a disconnected port. note that the port-routing logic is the only block of logic within the ich5 that observes the physical (real) connect/disconnect information. the port status logic inside each of the host controllers observes the electrical connect/disconnect information that is generated by the port-routing logic. only the differential signal pairs are muxed/demuxed between the uhci and ehci host controllers. the other usb functional signals are handled as follows: ? the overcurrent inputs (oc[7:0]#) are directly routed to both controllers. an overcurrent event is recorded in both controllers? status registers. the port-routing logic is implemented in the suspend power well so that re-enumeration and re-mapping of the usb ports is not required following entering and exiting a system sleep state in which the core power is turned off. the ich5 also allows the usb debug port traffic to be routed in and out of port #0. when in this mode, the enhanced host controller is the owner of port #0. figure 24. intel ? ich5-usb port connections uhci #4 (d29:f3) uchi #1 (d29:f0) uhci #2 (d29:f1) uhci #3 (d29:f2) enhanced host controller logic debug port port 7 port 3 port 4 port 5 port 6 port 2 port 1 port 0 224 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.20.8.2 device connects the enhanced host controller interface specification for universal serial bus, revision 1.0 describes the details of handling device connects in section 4.2. there are four general scenarios that are summarized below. 1. configure flag = 0 and a full speed/low speed-only device is connected ? in this case, the uhc is the owner of the port both before and after the connect occurs. the ehc (except for the port-routing logic) never sees the connect occur. the uhci driver handles the connection and initialization process. 2. configure flag = 0 and a high speed-capable device is connected ? in this case, the uhc is the owner of the port both before and after the connect occurs. the ehc (except for the port-routing logic) never sees the connect occur. the uhci driver handles the connection and initialization process. since the uhc does not perform the high-speed chirp handshake, the device operates in compatible mode. 3. configure flag = 1 and a full speed/low speed-only device is connected ? in this case, the ehc is the owner of the port before the connect occurs. the ehci driver handles the connection and performs the port reset. after the reset process completes, the ehc hardware has cleared (not set) the port enable bit in the ehc?s portsc register. the ehci driver then writes a 1 to the port owner bit in the same register, causing the uhc to see a connect event and the ehc to see an ?electrical? disconnect event. the uhci driver and hardware handle the connection and initialization process from that point on. the ehci driver and hardware handle the perceived disconnect. 4. configure flag = 1 and a high speed-capable device is connected ? in this case, the ehc is the owner of the port before, and remains the owner after, the connect occurs. the ehci driver handles the connection and performs the port reset. after the reset process completes, the ehc hardware has set the port enable bit in the ehc?s portsc register. the port is functional at this point. the uhc continues to see an unconnected port. intel ? 82801eb ich5 / 82801er ich5r datasheet 225 functional description 5.20.8.3 device disconnects the enhanced host controller interface specification for universal serial bus, revision 1.0 describes the details of handling device connects in section 4.2. there are three general scenarios that are summarized below. 1. configure flag = 0 and the device is disconnected ? in this case, the uhc is the owner of the port both before and after the disconnect occurs. the ehc (except for the port-routing logic) never sees a device attached. the uhci driver handles disconnection process. 2. configure flag = 1 and a full speed/low speed-capable device is disconnected ? in this case, the uhc is the owner of the port before the disconnect occurs. the disconnect is reported by the uhc and serviced by the associated uhci driver. the port-routing logic in the ehc cluster forces the port owner bit to 0, indicating that the ehc owns the unconnected port. 3. configure flag = 1 and a high speed-capable device is disconnected ? in this case, the ehc is the owner of the port before, and remains the owner after, the disconnect occurs. the ehci hardware and driver handle the disconnection process. the uhc never sees a device attached. 5.20.8.4 effect of resets on port-routing logic as mentioned above, the port routing logic is implemented in the suspend power well so that remuneration and re-mapping of the usb ports is not required following entering and exiting a system sleep state in which the core power is turned off. 5.20.9 usb 2.0 legacy keyboard operation the ich5 must support the possibility of a keyboard downstream from either a full speed/low speed or a high speed port. the description of the legacy keyboard support is unchanged from usb 1.1 (see section 5.19.8 ). the ehc provides the basic ability to generate smis on an interrupt event, along with more sophisticated control of the generation of smis. reset event effect on configure flag effect on port owner bits suspend well reset cleared (0) set (1) core well reset no effect no effect d3-to-d0 reset no effect no effect hcreset cleared (0) set (1) 226 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.20.10 usb 2.0 based debug port the ich5 supports the elimination of the legacy com ports by providing the ability for new debugger software to interact with devices on a usb 2.0 port. high-level restrictions and features are: ? must be operational before usb 2.0 drivers are loaded. ? must work even when the port is disabled. ? must work even though non-configured port is default-routed to the classic controller. note that the debug port can not be used to debug an issue that requires a full speed/low speed device on port #0 using the uhci drivers. ? must allow normal system usb 2.0 traffic in a system that may only have one usb port. ? debug port device (dpd) must be high-speed capable and connect to a high-speed port on ich5 systems. ? debug port fifo must always make forward progress (a bad status on usb is simply presented back to software). ? the debug port fifo is only given one usb access per microframe. the debug port facilitates os and device driver debug. it allows the software to communicate with an external console using a usb 2.0 connection. because the interface to this link does not go through the normal usb 2.0 stack, it allows communication with the external console during cases where the os is not loaded, the usb 2.0 software is broken, or where the usb 2.0 software is being debugged. specific features of this implementation of a debug port are: ? only works with an external usb 2.0 debug device (console) ? implemented for a specific port on the host controller ? operational anytime the port is not suspended and the host controller is in d0 power state. ? capability is interrupted when port is driving usb reset 5.20.10.1 theory of operation there are two operational modes for the usb debug port: 1. mode 1 is when the usb port is in a disabled state from the viewpoint of a standard host controller driver. in mode 1, the debug port controller is required to generate a ?keepalive? packets less than 2 ms apart to keep the attached debug device from suspending. the keepalive packet should be a standalone 32-bit sync field. 2. mode 2 is when the host controller is running (i.e., host controller?s run/stop# bit is 1). in mode 2, the normal transmission of sof packets will keep the debug device from suspending. intel ? 82801eb ich5 / 82801er ich5r datasheet 227 functional description behavioral rules 1. in both modes 1 and 2, the debug port controller must check for software requested debug transactions at least every 125 microseconds. 2. if the debug port is enabled by the debug driver, and the standard host controller driver resets the usb port, usb debug transactions are held off for the duration of the reset and until after the first sof is sent. 3. if the standard host controller driver suspends the usb port, then usb debug transactions are held off for the duration of the suspend/resume sequence and until after the first sof is sent. 4. the enabled_cnt bit in the debug register space is independent of the similar port control bit in the associated port status and control register. table 102 shows the debug port behavior related to the state of bits in the debug registers as well as bits in the associated port status and control register. table 102. debug port behavior owner_cnt enabled_ct port enable run / stop suspend debug port behavior 0xxxx debug port is not being used. normal operation. 10xxx debug port is not being used. normal operation. 1100x debug port in mode 1. sync keepalives sent plus debug traffic 1101x debug port in mode 2. sof (and only sof) is sent as keepalive. debug traffic is also sent. note that no other normal traffic is sent out this port, because the port is not enabled. 11100 illegal. host controller driver should never put controller into this state (enabled, not running and not suspended). 11101 port is suspended. no debug traffic sent. 11110 debug port in mode 2. debug traffic is interspersed with normal traffic. 11111 port is suspended. no debug traffic sent. 228 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.20.10.1.1 out transactions an out transaction sends data to the debug device. it can occur only when the following are true: ? the debug port is enabled ? the debug software sets the go_cnt bit ? the write_read#_cnt bit is set the sequence of the transaction is: 1. software sets the appropriate values in the following bits: ? usb_address_cnf ? usb_endpoint_cnf ?data_buffer[63:0] ? token_pid_cnt[7:0] ? send_pid_cnt[15:8] ? data_len_cnt ? write_read#_cnt (note: this will always be 1 for out transactions) ? go_cnt (note: this will always be 1 to initiate the transaction) 2. the debug port controller sends a token packet consisting of: ? sync ? token_pid_cnt field ? usb_address_cnt field ? usb_endpoint_cnt field ? 5-bit crc field 3. after sending the token packet, the debug port controller sends a data packet consisting of: ? sync ? send_pid_cnt field ? the number of data bytes indicated in data_len_cnt from the data_buffer ? 16-bit crc note: a data_len_cnt value of 0 is valid in which case no data bytes would be included in the packet. 4. after sending the data packet, the controller waits for a handshake response from the debug device. ? if a handshake is received, the debug port controller: ? a. places the received pid in the received_pid_sts field ? b. resets the error_good#_sts bit ? c. sets the done_sts bit ? if no handshake pid is received, the debug port controller: ? a. sets the exception_sts field to 001b ? b. sets the error_good#_sts bit ? c. sets the done_sts bit intel ? 82801eb ich5 / 82801er ich5r datasheet 229 functional description 5.20.10.1.2 in transactions an in transaction receives data from the debug device. it can occur only when the following are true: ? the debug port is enabled ? the debug software sets the go_cnt bit ? the write_read#_cnt bit is reset the sequence of the transaction is: 1. software sets the appropriate values in the following bits: ? usb_address_cnf ? usb_endpoint_cnf ? token_pid_cnt[7:0] ? data_len_cnt ? write_read#_cnt (note: this will always be 0 for in transactions) ? go_cnt (note: this will always be 1 to initiate the transaction) 2. the debug port controller sends a token packet consisting of: ?sync ? token_pid_cnt field ? usb_address_cnt field ? usb_endpoint_cnt field ? 5-bit crc field. 3. after sending the token packet, the debug port controller waits for a response from the debug device. if a response is received: ? the received pid is placed into the received_pid_sts field ? any subsequent bytes are placed into the data_buffer ? the data_len_cnt field is updated to show the number of bytes that were received after the pid. 4. if valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller: ? resets the error_good#_sts bit ? sets the done_sts bit 5. if valid packet was received from the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: ? transmits an ack handshake packet ? resets the error_good#_sts bit ? sets the done_sts bit 6. if no valid packet is received, then the debug port controller: ? sets the exception_sts field to 001b ? sets the error_good#_sts bit ? sets the done_sts bit. 230 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.20.10.1.3 debug software enabling the debug port there are two mutually exclusive conditions that debug software must address as part of its startup processing: ? the ehci has been initialized by system software ? the ehci has not been initialized by system software debug software can determine the current ?initialized? state of the ehci by examining the configure flag in the ehci usb 2.0 command register. if this flag is set, then system software has initialized the ehci. otherwise the ehci should not be considered initialized. debug software will initialize the debug port registers depending on the state the ehci. however, before this can be accomplished, debug software must determine which root usb port is designated as the debug port. determining the debug port debug software can easily determine which usb root port has been designated as the debug port by examining bits 20:23 of the ehci host controller structural parameters register. this 4-bit field represents the numeric value assigned to the debug port (i.e., 0000=port 0). debug software startup with non-initialized ehci debug software can attempt to use the debug port if after setting the owner_cnt bit, the current connect status bit in the appropriate (see determining the debug port) portsc register is set. if the current connect status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. if a device is connected to the port, then debug software must reset/enable the port. debug software does this by setting and then clearing the port reset bit the portsc register. to guarantee a successful reset, debug software should wait at least 50 ms before clearing the port reset bit. due to possible delays, this bit may not change to 0 immediately; reset is complete when this bit reads as 0. software must not continue until this bit reads 0. if a high-speed device is attached, the ehci will automatically set the port enabled/disabled bit in the portsc register and the debug software can proceed. debug software should set the enabled_cnt bit in the debug port control/status register, and then reset (clear) the port enabled/disabled bit in the portsc register (so that the system host controller driver does not see an enabled port when it is first loaded). debug software startup with initialized ehci debug software can attempt to use the debug port if the current connect status bit in the appropriate (see determining the debug port) portsc register is set. if the current connect status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. if a device is connected, then debug software must set the owner_cnt bit and then the enabled_cnt bit in the debug port control/status register. determining debug peripheral presence after enabling the debug port functionality, debug software can determine if a debug peripheral is attached by attempting to send data to the debug peripheral. if all attempts result in an error (exception bits in the debug port control/status register indicates a transaction error), then the attached device is not a debug peripheral. if the debug port peripheral is not present, then debug software may choose to terminate or it may choose to wait until a debug peripheral is connected. intel ? 82801eb ich5 / 82801er ich5r datasheet 231 functional description 5.21 smbus controller (d31:f3) the ich5 provides an smbus 2.0 compliant host controller as well as an smbus slave interface. the host controller provides a mechanism for the processor to initiate communications with smbus peripherals (slaves). the ich5 is also capable of operating in a mode in which it can communicate with i 2 c compatible devices. the ich5 can perform smbus messages with either packet error checking (pec) enabled or disabled. the actual pec calculation and checking is performed in hardware by the ich5. the slave interface allows an external master to read from or write to the ich5. write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. the ich5?s internal host controller cannot access the ich5?s internal slave interface. the ich5 smbus logic exists in device 31:function 3 configuration space, and consists of a transmit data path, and host controller. the transmit data path provides the data flow logic needed to implement the seven different smbus command protocols and is controlled by the host controller. the ich5 smbus controller logic is clocked by rtc clock. the smbus address resolution protocol (arp) is supported by using the existing host controller commands through software, except for the new host notify command (which is actually a received message). the programming model of the host controller is combined into two portions: a pci configuration portion, and a system i/o mapped portion. all static configuration, such as the i/o base address, is done via the pci configuration space. real-time programming of the host interface is done in system i/o space. 5.21.1 host controller the smbus host controller is used to send commands to other smbus slave devices. software sets up the host controller with an address, command, and, for writes, data and optional pec; and then tells the controller to start. when the controller has finished transmitting data on writes, or receiving data on reads, it generates an smi# or interrupt, if enabled. the host controller supports 8 command protocols of the smbus interface (see system management bus (smbus) specification, version 2.0 ): quick command, send byte, receive byte, write byte/word, read byte/word, process call, block read/write, block write?block read process call, and host notify. the smbus host controller requires that the various data and command fields be setup for the type of command to be sent. when software sets the start bit, the smbus host controller performs the requested transaction, and interrupts the processor (or generate an smi#) when the transaction is completed. once a start command has been issued, the values of the ?active registers? (host control, host command, transmit slave address, data 0, data 1) should not be changed or read until the interrupt status bit (intr) has been set (indicating the completion of the command). any register values needed for computation purposes should be saved prior to issuing of a new command, as the smbus host controller updates all registers while completing the new command. using the smb host controller to send commands to the ich5?s smb slave port is supported. the ich5 is fully compliant with the system management bus (smbus) specification, version 2.0 . slave functionality, including the host notify protocol, is available on the smbus pins. the smlink and smbus signals should not be tied together externally. 232 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.21.1.1 command protocols in all of the following commands, the host status register (offset 00h) is used to determine the progress of the command. while the command is in operation, the host_busy bit is set. if the command completes successfully, the intr bit will be set in the host status register. if the device does not respond with an acknowledge, and the transaction times out, the dev_err bit is set. if software sets the kill bit in the host control register while the command is running, the transaction will stop and the failed bit will be set. quick command when programmed for a quick command, the transmit slave address register is sent. the pec byte is never appended to the quick protocol. software should force the pec_en bit to 0 when performing the quick command. software must force the i2c_en bit to 0 when running this command.the format of the protocol is shown in table 103 . send byte / receive byte for the send byte command, the transmit slave address and device command registers are sent for the receive byte command, the transmit slave address register is sent. the data received is stored in the data0 register. software must force the i2c_en bit to 0 when running this command. the receive byte is similar to a send byte, the only difference is the direction of data transfer. the format of the protocol is shown in table 104 . and table 105 . table 103. quick protocol bit description 1 start condition 8:2 slave address ? 7 bits 9 read / write direction 10 acknowledge from slave 11 stop table 104. send / receive byte protocol without pec send byte protocol receive byte protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 read 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 data byte from slave 19 acknowledge from slave 19 not acknowledge 20 stop 20 stop intel ? 82801eb ich5 / 82801er ich5r datasheet 233 functional description write byte/word the first byte of a write byte/word access is the command code. the next 1 or 2 bytes are the data to be written. when programmed for a write byte/word command, the transmit slave address, device command, and data0 registers are sent. in addition, the data1 register is sent on a write word command. software must force the i2c_en bit to 0 when running this command. the format of the protocol is shown in table 106 and table 107 . table 105. send/receive byte protocol with pec send byte protocol receive byte protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 read 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 data byte from slave 19 acknowledge from slave 19 acknowledge 27:20 pec 27:20 pec from slave 28 acknowledge from slave 28 not acknowledge 29 stop 29 stop table 106. write byte/word protocol without pec write byte protocol write word protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte ? 8 bits 27:20 data byte low ? 8 bits 28 acknowledge from slave 28 acknowledge from slave 29 stop 36:29 data byte high ? 8 bits 37 acknowledge from slave 38 stop 234 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description read byte/word reading data is slightly more complicated than writing data. first the ich5 must write a command to the slave device. then it must follow that command with a repeated start condition to denote a read from that device's address. the slave then returns 1 or 2 bytes of data. software must force the i2c_en bit to 0 when running this command. when programmed for the read byte/word command, the transmit slave address and device command registers are sent. data is received into the data0 on the read byte, and the dat0 and data1 registers on the read word. the format of the protocol is shown in table 108 and table 109 . table 107. write byte/word protocol with pec write byte protocol write word protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte ? 8 bits 27:20 data byte low ? 8 bits 28 acknowledge from slave 28 acknowledge from slave 36:29 pec 36:29 data byte high ? 8 bits 37 acknowledge from slave 37 acknowledge from slave 38 stop 45:38 pec 46 acknowledge from slave 47 stop intel ? 82801eb ich5 / 82801er ich5r datasheet 235 functional description table 108. read byte/word protocol without pec read byte protocol read word protocol bit description bit description 1start 1start 8:2 slave address ? 7 bits 82 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 20 repeated start 20 repeated start 27:21 slave address ? 7 bits 27:21 slave address ? 7 bits 28 read 28 read 29 acknowledge from slave 29 acknowledge from slave 37:30 data from slave ? 8 bits 37:30 data byte low from slave ? 8 bits 38 not acknowledge 38 acknowledge 39 stop 46:39 data byte high from slave ? 8 bits 47 not acknowledge 48 stop table 109. read byte/word protocol with pec read byte protocol read word protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 20 repeated start 20 repeated start 27:21 slave address ? 7 bits 27:21 slave address ? 7 bits 28 read 28 read 29 acknowledge from slave 29 acknowledge from slave 37:30 data from slave ? 8 bits 37:30 data byte low from slave ? 8 bits 38 acknowledge 38 acknowledge 46:39 pec from slave 46:39 data byte high from slave ? 8 bits 47 not acknowledge 47 acknowledge 48 stop 55:48 pec from slave 56 not acknowledge 57 stop 236 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description process call the process call is so named because a command sends data and waits for the slave to return a value dependent on that data. the protocol is simply a write word followed by a read word, but without a second command or stop condition. when programmed for the process call command, the ich5 transmits the transmit slave address, host command, data0 and data1 registers. data received from the device is stored in the data0 and data1 registers. the process call command with i2c_en set and the pec_en bit set produces undefined results. software must force either i2c_en or pec_en to 0 when running this command. the format of the protocol is shown in table 110 and table 111 . note: for process call command, the value written into bit 0 of the transmit slave address register (smb i/o register, offset 04h) needs to be 0. table 110. process call protocol without pec bit description 1start 8:2 slave address ? 7 bits 9write 10 acknowledge from slave 18:11 command code ? 8 bits (skip this step if i2c_en bit is set) 19 acknowledge from slave (skip this step if i2c_en bit is set) 27:20 data byte low ? 8 bits 28 acknowledge from slave 36:29 data byte high ? 8 bits 37 acknowledge from slave 38 repeated start 45:39 slave address ? 7 bits 46 read 47 acknowledge from slave 55:48 data byte low from slave ? 8 bits 56 acknowledge 64:57 data byte high from slave ? 8 bits 65 not acknowledge 66 stop intel ? 82801eb ich5 / 82801er ich5r datasheet 237 functional description block read/write the ich5 contains a 32-byte buffer for read and write data which can be enabled by setting bit 1 of the auxiliary control register at offset 0dh in i/o space, as opposed to a single byte of buffering. this 32-byte buffer is filled with write data before transmission, and filled with read data on reception. in the ich5, the interrupt is generated only after a transmission or reception of 32 bytes, or when the entire byte count has been transmitted/received. this requires the ich5 to check the byte count field. currently, the byte count field is transmitted but ignored by the hardware as software will end the transfer after all bytes it cares about have been sent or received. for a block write, software must either force the i2c_en bit or both the pec_en and aac bits to 0 when running this command. smbus mode: the block write begins with a slave address and a write condition. after the command code the ich5 issues a byte count describing how many more bytes will follow in the message. if a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by 20 bytes of data. the byte count may not be 0. a block read or write is allowed to transfer a maximum of 32 data bytes. table 111. process call protocol with pec bit description 1start 8:2 slave address ? 7 bits 9write 10 acknowledge from slave 18:11 command code ? 8 bits 19 acknowledge from slave 27:20 data byte low ? 8 bits 28 acknowledge from slave 36:29 data byte high ? 8 bits 37 acknowledge from slave 38 repeated start 45:39 slave address ? 7 bits 46 read 47 acknowledge from slave 55:48 data byte low from slave ? 8 bits 56 acknowledge 64:57 data byte high from slave ? 8 bits 65 acknowledge 73:66 pec from slave 74 not acknowledge 75 stop 238 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description when programmed for a block write command, the transmit slave address, device command, and data0 (count) registers are sent. data is then sent from the block data byte register; the total data sent being the value stored in the data0 register. on block read commands, the first byte received is stored in the data0 register, and the remaining bytes are stored in the block data byte register. the format of the block read/write protocol is shown in table 112 and table 113 . note: for block write, if the i 2 c_en bit is set, the format of the command changes slightly. the ich5 will still send the number of bytes (on writes) or receive the number of bytes (on reads) indicated in the data0 register. however, it will not send the contents of the data0 register as part of the message. l table 112. block read/write protocol without pec block write protocol block read protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count ? 8 bits (skip this step if i 2 c_en bit set) 20 repeated start 28 acknowledge from slave (skip this step if i2c_en bit set) 27:21 slave address ? 7 bits 36:29 data byte 1 ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 45:3 data byte 2 ? 8 bits 37:30 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge ... data bytes / slave acknowledges... 46:39 data byte 1 from slave ? 8 bits ... data byte n ? 8 bits 47 acknowledge ... acknowledge from slave 55:48 data byte 2 from slave ? 8 bits ... stop 56 acknowledge ... data bytes from slave/acknowledge ... data byte n from slave ? 8 bits ... not acknowledge ... stop intel ? 82801eb ich5 / 82801er ich5r datasheet 239 functional description table 113. block read/write protocol with pec block write protocol block read protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count ? 8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address ? 7 bits 36:29 data byte 1 ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2 ? 8 bits 37:30 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge ... data bytes / slave acknowledges... 46:39 data byte 1 from slave ? 8 bits ... data byte n ? 8 bits 47 acknowledge ... acknowledge from slave 55:48 data byte 2 from slave ? 8 bits ... pec ? 8 bits 56 acknowledge ... acknowledge from slave ... data bytes from slave/acknowledge ... stop ... data byte n from slave ? 8 bits ... acknowledge ... pec from slave ? 8 bits ... not acknowledge ... stop 240 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description i 2 c read this command allows the ich5 to perform block reads to certain i 2 c devices, such as serial e 2 proms. the smbus block read supports the 7-bit addressing mode only. however, this does not allow access to devices using the i 2 c ?combined format? that has data bytes after the address. typically these data bytes correspond to an offset (address) within the serial memory chips. note: this command is supported independent of the setting of the i2c_en bit. the i 2 c read command with the pec_en bit set produces undefined results. software must force both the pec_en and aac bit to 0 when running this command. for i 2 c read command, the value written into bit 0 of the transmit slave address register (smb i/o register, offset 04h) needs to be 0. the format that is used for the new command is shown in table 114 . the ich5 will continue reading data from the peripheral until the nak is received. table 114. i 2 c block read bit description 1start 8:2 slave address ? 7 bits 9write 10 acknowledge from slave 18:11 send data1 register 19 acknowledge from slave 20 repeated start 27:21 slave address ? 7 bits 28 read 29 acknowledge from slave 37:30 data byte 1 from slave ? 8 bits 38 acknowledge 46:39 data byte 2 from slave ? 8 bits 47 acknowledge ? data bytes from slave / acknowledge ? data byte n from slave ? 8 bits ? not acknowledge ?stop intel ? 82801eb ich5 / 82801er ich5r datasheet 241 functional description block write?block read process call the block write-block read process call is a two-part message. the call begins with a slave address and a write condition. after the command code the host issues a write byte count (m) that describes how many more bytes will be written in the first part of the message. if a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. the write byte count (m) cannot be 0. the second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a read bit. the next byte is the read byte count (n), which may differ from the write byte count (m). the read byte count (n) cannot be 0. the combined data payload must not exceed 32 bytes. the byte length restrictions of this process call are summarized as follows: ? m 1 byte ? n 1 byte ? m + n 32 bytes the read byte count does not include the pec byte. the pec is computed on the total message beginning with the first slave address and using the normal pec computational rules. it is highly recommended that a pec byte be used with the block write-block read process call. software must do a read to the command register (offset 2h) to reset the 32byte buffer pointer prior to reading the block data register. note that there is no stop condition before the repeated start condition, and that a nack signifies the end of the read transfer. note: e32b bit in the auxiliary control register must be set when using this protocol. table 115. block write?block read process call protocol with/without pec (sheet 1 of 2) bit description 1start 8:2 slave address ? 7 bits 9write 10 acknowledge from slave 18:11 command code ? 8 bits 19 acknowledge from slave 27:20 data byte count (m) ? 8 bits 28 acknowledge from slave 36:29 data byte (1) ? 8 bits 37 acknowledge from slave 45:38 data byte (2) ? 8 bits 46 acknowledge from slave ?? data byte (m) ? 8 bits acknowledge from slave 242 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.21.1.2 i 2 c behavior when the i 2 c_en bit is set, the ich5 smbus logic will instead be set to communicate with i 2 c devices. this forces the following changes: ? the process call command will skip the command code (and its associated acknowledge) ? the block write command will skip sending the byte count (data0) in addition, the ich5 will support the new i 2 c read command. this is independent of the i 2 c_en bit. note: when operating in i 2 c mode the ich5 will not use the 32-byte buffer for block commands. repeated start slave address ? 7 bits read acknowledge from master data byte count (n) from master ? 8 bits acknowledge from slave data byte (1) from master ? 8 bits acknowledge from slave data byte (2) from master ? 8 bits acknowledge from slave ?? data byte count (n) from master ? 8 bits acknowledge from slave data byte high from slave - 8 bits acknowledge from slave (skip if no pec) pec from master (skip if no pec) not acknowledge stop table 115. block write?block read process call protocol with/without pec (sheet 2 of 2) bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 243 functional description 5.21.2 bus arbitration several masters may attempt to get on the bus at the same time by driving the smbdata line low to signal a start condition. the ich5 must continuously monitor the smbdata line. when the ich5 is attempting to drive the bus to a 1 by letting go of the smbdata line, and it samples smbdata low, then some other master is driving the bus and the ich5 must stop transferring data. if the ich5 sees that it has lost arbitration, the condition is called a collision. the ich5 will set the bus_err bit in the host status register, and if enabled, generate an interrupt or smi#. the processor is responsible for restarting the transaction. when the ich5 is a smbus master, it drives the clock. when the ich5 is sending address or command as an smbus master, or data bytes as a master on writes, it drives data relative to the clock it is also driving. it will not start toggling the clock until the start or stop condition meets proper setup and hold time. the ich5 will also guarantee minimum time between smbus transactions as a master. note: the ich5 supports the same arbitration protocol for both the smbus and the system management (smlink) interfaces. 5.21.3 bus timing 5.21.3.1 clock stretching some devices may not be able to handle their clock toggling at the rate that the ich5 as an smbus master would like. they have the capability of stretching the low time of the clock. when the ich5 attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time. the ich5 must monitor the smbus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. while the bus is still low, the high time counter must not be enabled. similarly, the low period of the clock can be stretched by an smbus master if it is not ready to send or receive data. 5.21.3.2 bus time out (intel ? ich5 as smbus master) if there is an error in the transaction, such that an smbus device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. the ich5 will discard the cycle, and set the dev_err bit. the time out minimum is 25 ms. the time-out counter inside the ich5 will start after the last bit of data is transferred by the ich5 and it is waiting for a response. the 25 ms will be a count of 800 rtc clocks. 244 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.21.4 interrupts / smi# the ich5 smbus controller uses pirqb# as its interrupt pin. however, the system can alternatively be set up to generate smi# instead of an interrupt, by setting the smbus_smi_en bit. table 117 and table 118 specify how the various enable bits in the smbus function control the generation of the interrupt, host and slave smi, and wake internal signals. the rows in the tables are additive, which means that if more than one row is true for a particular scenario then the results for all of the activated rows will occur. table 116. enable for smbalert# event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31:f3:offset 40h, bit 1) smbalert_dis (slave command i/o register, offset 11h, bit 2) result smbalert# asserted low (always reported in host status register, bit 5) x x x wake generated x1 0 slave smi# generated (smbus_smi_sts) 1 0 0 interrupt generated table 117. enables for smbus slave write and smbus host events event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31:f3:offset 40h, bit1) event slave write to wake/ smi# command xx wake generated when asleep. slave smi# generated when awake (smbus_smi_sts). slave write to smlink_slave_smi command xx slave smi# generated when in the s0 state (smbus_smi_sts) any combination of host status register [4:1] asserted 0 x none 1 0 interrupt generated 1 1 host smi# generated table 118. enables for the host notify command host_notify_intren (slave control i/o register, offset 11h, bit 0) smb_smi_en (host config register, d31:f3:off40h, bit 1) host_notify_wken (slave control i/o register, offset 11h, bit 1) result 0 x 0 none x x 1 wake generated 1 0 x interrupt generated 11x slave smi# generated (smbus_smi_sts) intel ? 82801eb ich5 / 82801er ich5r datasheet 245 functional description 5.21.5 smbalert# smbalert# is multiplexed with gpio11. when enable and the signal is asserted, the ich5 can generate an interrupt, an smi#, or a wake event from s1 ? s5. note: any event on smbalert# (regardless whether it is programmed as a gpio or not), causes the event message to be sent in heartbeat mode. 5.21.6 smbus crc generation and checking if the aac bit is set in the auxiliary control register, the ich5 automatically calculates and drives crc at the end of the transmitted packet for write cycles, and will check the crc for read cycles. it will not transmit the contents of the pec register for crc. the pec bit must not be set in the host control register if this bit is set, or unspecified behavior will result. if the read cycle results in a crc error, the dev_err bit and the crce bit in the auxiliary status register at offset 0ch will be set. 5.21.7 smbus slave interface the ich5?s smbus slave interface is accessed via the smbus. the smbus slave logic will not generate or handle receiving the pec byte and will only act as a legacy alerting protocol device. the slave interface allows the ich5 to decode cycles, and allows an external microcontroller to perform specific actions. key features and capabilities include: ? supports decode of three types of messages: byte write, byte read, and host notify. ? receive slave address register: this is the address that the ich5 decodes. a default value is provided so that the slave interface can be used without the processor having to program this register. ? receive slave data register in the smbus i/o space that includes the data written by the external microcontroller. ? registers that the external microcontroller can read to get the state of the ich5. see table 123 . ? status bits to indicate that the smbus slave logic caused an interrupt or smi# due to the reception of a message that matched the slave address. ? bit 0 of the slave status register for the host notify command ? bit 16 of the smi status register ( section 9.10.9 ) for all others if a master leaves the clock and data bits of the smbus interface at 1 for 50 s or more in the middle of a cycle, the ich5 slave logic's behavior is undefined. this is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. note: when an external micro controller accesses the smbus slave interface over the smbus a translation in the address is needed to accommodate the least significant bit used for read/write control. for example, if the ich5 slave address (rcv_slva) is left at 44h (default), the external micro controller would use an address of 88h/89h (write/read). 246 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.21.7.1 format of slave write cycle the external master performs byte write commands to the ich5 smbus slave i/f. the ?command? field (bits 11 : 18) indicate which register is being accessed. the data field (bits 20 : 27) indicate the value that should be written to that register. the write cycle format is shown in table 119 . table 120 has the values associated with the registers. note: the external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. the ich5 overwrites the old value with any new value received. a race condition is possible where the new value is being written to the register just at the time it is being read. ich5 will not attempt to cover this race condition (i.e., unpredictable results in this case). table 119. slave write cycle format bits description driven by comment 1 start condition external microcontroller 8:2 slave address ? 7 bits external microcontroller must match value in receive slave address register 9 write external microcontroller always 0 10 ack ich5 18:11 command external microcontroller this field indicates which register will be accessed. see table 120 for the register definitions 19 ack ich5 27:20 register data external microcontroller see table 120 for the register definitions 28 ack ich5 29 stop external microcontroller table 120. slave write registers register function 0 command register. see table 121 below for legal values written to this register. 1?3 reserved 4 data message byte 0 5 data message byte 1 6?7 reserved 8 frequency straps will be written on bits 3:0. bits 7:4 should be 0, but will be ignored. 9?ffh reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 247 functional description . table 121. command types command type description 0 reserved 1 wake/smi#. this command wakes the system if it is not already awake. if system is already awake, an smi# is generated. note: the smb_wak_sts bit will be set by this command, even if the system is already awake. the smi handler should then clear this bit. 2 unconditional powerdown. this command sets the pwrbtnor_sts bit, and has the same effect as the powerbutton override occurring. 3 hard reset without cycling: this command causes a hard reset of the system (does not include cycling of the power supply). this is equivalent to a write to the cf9h register with bits 2:1 set to 1, but bit 3 set to 0. 4 hard reset system. this command causes a hard reset of the system (including cycling of the power supply). this is equivalent to a write to the cf9h register with bits 3:1 set to 1. 5 disable the tco messages. this command will disable the intel ? ich5 from sending heartbeat and event messages (as described in section 5.14.2 ). once this command has been executed, heartbeat and event message reporting can only be re-enabled by assertion and deassertion of the rsmrst# signal. 6 wd reload: reload watchdog timer. 7 reserved 8 smlink_slv_smi. when ich5 detects this command type while in the s0 state, it sets the smlink_slv_smi_sts bit (see section 9.11.7 ). this command should only be used if the system is in an s0 state. if the message is received during s1?s5 states, the ich5 acknowledges it, but the smlink_slv_smi_sts bit does not get set. note: it is possible that the system transitions out of the s0 state at the same time that the smlink_slv_smi command is received. in this case, the smlink_slv_smi_sts bit may get set but not serviced before the system goes to sleep. once the system returns to s0, the smi associated with this bit would then be generated. software must be able to handle this scenario. 9?ffh reserved 248 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.21.7.2 format of read command the external master performs byte read commands to the ich5 smbus slave i/f. the ?command? field (bits 18 : 11) indicate which register is being accessed. the data field (bits 30 : 37) contain the value that should be read from that register. table 122 shows the read cycle format. table 123 shows the register mapping for the data byte. table 122. read cycle format bit description driven by comment 1 start external microcontroller 8:2 slave address ? 7 bits external microcontroller must match value in receive slave address register 9 write external microcontroller always 0 10 ack intel ? ich5 18:11 command code ? 8 bits external microcontroller indicates which register is being accessed. see table 123 . 19 ack ich5 20 repeated start external microcontroller 27:21 slave address ? 7 bits external microcontroller must match value in receive slave address register 28 read external microcontroller always 1 29 ack ich5 37:30 data byte ich5 value depends on register being accessed. see table 123 . 38 not ack external microcontroller 39 stop external microcontroller intel ? 82801eb ich5 / 82801er ich5r datasheet 249 functional description table 123. data values for slave read registers register bits description 0 7:0 reserved. 12:0 system power state ? 000 = s0 ? 001 = s1 ? 010 = reserved ?011 = s3 ? 100 = s4 ? 101 = s5 ? 110 = reserved ? 111 = reserved 17:3reserved 2 3:0 frequency strap register 27:4reserved 3 5:0 watchdog timer current value 37:6reserved 40 1 = the intruder detect (intrd_det) bit is set. this indicates that the system cover has probably been opened. 41 1 = bti temperature event occurred. this bit will be set if the intel ? ich5?s thrm# input signal is active. need to take after polarity control. 4 2 boot-status. this bit will be 1 when the processor does not fetch the first instruction. 43 this bit will be set after the tco timer times out a second time (both timeout and second_to_sts bits set). 4 6:4 reserved. 47 the bit will reflect the state of the gpi11/smbalert# signal, and will depend on the gp_inv11 bit. it does not matter if the pin is configured as gpi11 or smbalert#. ? if the gp_inv11 bit is 1, the value of register 4 bit 7 will equal the level of the gpi11/ smbalert# pin (high = 1, low = 0). ? if the gp_inv11 bit is 0, the value of register 4 bit 7 will equal the inverse of the level of the gpi11/smbalert# pin (high = 1, low = 0). 5 0 unprogrammed flash bios bit. this bit will be 1 to indicate that the first bios fetch returned ffh, which indicates that the flash bios is probably blank. 51reserved 52 cpu power failure status. 1 if the cpupwr_flr bit in the gen_pmcon_2 register is set. 57:3reserved 6 7:0 contents of the message 1 register. see section 9.11.9 . 7 7:0 contents of the message 2 register. see section 9.11.9 . 8 7:0 contents of the wdstatus register. see section 9.11.10 . 9?ffh 7:0 reserved 250 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.21.7.2.1 behavioral notes according to smbus protocol, read and write messages always begin with a start bit ? address ? write bit sequence. when the ich5 detects that the address matches the value in the receive slave address register, it will assume that the protocol is always followed and ignore the write bit (bit 9) and signal an acknowledge during bit 10 (see table 119 and table 122 ). in other words, if a start ? address ? read occurs (which is illegal for smbus read or write protocol), and the address matches the ich5?s slave address, the ich5 will still grab the cycle. also according to smbus protocol, a read cycle contains a repeated start ? address ? read sequence beginning at bit 20 (see table 122 ). once again, if the address matches the ich5?s receive slave address, it will assume that the protocol is followed, ignore bit 28, and proceed with the slave read cycle. note: an external microcontroller must not attempt to access the ich5?s smbus slave logic until at least 1 second after both rtcrst# and rsmrst# are deasserted (high). 5.21.7.3 format of host notify command the ich5 tracks and responds to the standard host notify command as specified in the system management bus (smbus) specification, version 2.0 . the host address for this command is fixed to 0001000b. if the ich5 already has data for a previously-received host notify command which has not been serviced yet by the host software (as indicated by the host_notify_sts bit), then it will nack following the host address byte of the protocol. this allows the host to communicate non-acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt. note: host software must always clear the host_notify_sts bit after completing any necessary reads of the address and data registers. table 124 shows the host notify format. table 124. host notify format bit description driven by comment 1 start external master 8:2 smb host address ? 7 bits external master always 0001_000 9 write external master always 0 10 ack (or nack) intel ? ich5 ich5 nacks if host_notify_sts is 1 17:11 device address ? 7 bits external master indicates the address of the master; loaded into the notify device address register 18 unused ? always 0 external master 7-bit-only address; this bit is inserted to complete the byte 19 ack ich5 27:20 data byte low ? 8 bits external master loaded into the notify data low byte register 28 ack ich5 36:29 data byte high ? 8 bits external master loaded into the notify data high byte register 37 ack ich5 38 stop external master intel ? 82801eb ich5 / 82801er ich5r datasheet 251 functional description 5.22 ac ?97 controller (audio d31:f5, modem d31:f6) note: all references to ac ?97 in this document refer to the ac ?97 specification , version 2.3. for further information on the operation of the ac-link protocol, see the ac ?97 specification , version 2.3 . the ich5 ac ?97 controller features include: ? independent pci functions for audio and modem. ? independent bus master logic for dual microphone input, dual pcm audio input (2-channel stereo per input), pcm audio output (2-, 4- or 6-channel audio), modem input, modem output and s/pdif output. ? 20-bit sample resolution ? multiple sample rates up to 48 khz ? 16 gpios ? single modem line ? configure up to three codecs with three ac_sdin pins table 125 shows a detailed list of features supported by the ich5 ac ?97 digital controller . table 125. features supported by intel ? ich5 (sheet 1 of 2) feature description system interface ? isochronous low latency bus master memory interface ? scatter/gather support for word-aligned buffers in memory (all mono or stereo 20-bit and 16-bit data types are supported, no 8-bit data types are supported) ? data buffer size in system memory from 3 to 65535 samples per input ? data buffer size in system memory from 0 to 65535 samples per output ? independent pci audio and modem functions with configuration and i/o spaces ? ac ?97 codec registers are shadowed in system memory via driver ? ac ?97 codec register accesses are serialized via semaphore bit in pci i/o space (new accesses are not allowed while a prior access is still in progress) power management ? power management via pci power management pci audio function ? read/write access to audio codec registers 00h?3ah and vendor registers 5ah?7eh ? 20-bit stereo pcm output, up to 48 khz (l,r, center, sub-woofer, l-rear and r-rear channels on slots 3,4,6,7,8,9,10,11) ? 16-bit stereo pcm input, up to 48 khz (l,r channels on slots 3,4) ? 16-bit mono mic in w/ or w/o mono mix, up to 48 khz (l,r channel, slots 3,4) (mono mix supports mono hardware aec reference for speakerphone) ? 16-bit mono pcm input, up to 48 khz from dedicated mic adc (slot 6) (supports speech recognition or stereo hardware aec ref for speakerphone) ? during cold reset ac_rst# is held low until after post and software deassertion of ac_rst# (supports passive pc_beep to speaker connection during post) 252 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description note: throughout this document, references to d31:f5 indicate that the audio function exists in pci device 31, function 5. references to d31:f6 indicate that the modem function exists in pci device 31, function 6. note: throughout this document references to tertiary, third, or triple codecs refer to the third codec in the system connected to the ac_sdin2 pin. the ac ?97 v2.3 specification refers to non-primary codecs as multiple secondary codecs. to avoid confusion and excess verbiage, this datasheet refers to it as the third or tertiary codec. pci modem function ? read/write access to modem codec registers 3ch?58h and vendor registers 5ah?7eh ? 16-bit mono modem line1 output and input, up to 48 khz (slot 5) ? low latency gpio[15:0] via hardwired update between slot 12 and pci i/o register ? programmable pci interrupt on modem gpio input changes via slot 12 gpio_int ? sci event generation on ac_sdin[2:0] wake-up signal ac-link ? ac ?97 2.3 ac-link interface ? variable sample rate output support via ac ?97 slotreq protocol (slots 3,4,5,6,7,8,9,10,11) ? variable sample rate input support via monitoring of slot valid tag bits (slots 3,4,5,6) ? 3.3 v digital operation meets ac ?97 2.3 dc switching levels ? ac-link i/o driver capability meets ac ?97 2.3 triple codec specifications ? codec register status reads must be returned with data in the next ac-link frame, per ac ?97 v2.3 specification . multiple codec ? triple codec addressing: all ac ?97 audio codec register accesses are addressable to codec id 00 (primary), codec id 01 (secondary), or codec id 10 (tertiary). ? modem codec addressing: all ac ?97 modem codec register accesses are addressable to codec id 00 (primary) or codec id 01 (secondary). ? triple codec receive capability via ac_sdin[2:0] pins (ac_sdin[2:0] frames are internally validated, synchronized, and or?d depending on the steer enable bit status in the sdm register) ? ac_sdin mapping to dma engine mapping capability allows for simultaneous input from two different audio codecs. notes: 1. audio codec ids are remappable and not limited to 00,01,10. 2. modem codec ids are remappable and limited to 00, 01. 3. when using multiple codecs, the modem codec must be id 01. figure 25. intel ? ich5-based audio codec ?97 specification, version 2.3 table 125. features supported by intel ? ich5 (sheet 2 of 2) feature description audio in (record) audio out (6 channel playback) pc mic.2 s/pdif* output mic.1 modem intel ? 82801eb ich5 / 82801er ich5r datasheet 253 functional description 5.22.1 pci power management this power management section applies for all ac ?97 controller functions. after a power management event is detected, the ac ?97 controller wakes the host system. the following sections describe these events and the ac ?97 controller power states. device power states the ac ?97 controller supports d0 and d3 pci power management states. the following are notes regarding the ac ?97 controller implementation of the device states: 1. the ac ?97 controller hardware does not inherently consume any more power when it is in the d0 state than it does in d3 state. however, software can halt the dma engine prior to entering these low power states such that the maximum power consumption is reduced. 2. in the d0 state, all implemented ac ?97 controller features are enabled. 3. in d3 state, accesses to the ac ?97 controller memory-mapped or i/o range results in master abort. 4. in d3 state, the ac ?97 controller interrupt must never assert for any reason. the internal pme# signal is used to signal wake events, etc. 5. when the device power state field is written from d3 hot to d0, an internal reset is generated. see section 16.1 for general rules on the effects of this reset. 6. ac97 sts bit is set only when the audio or modem resume events were detected and their respective pme enable bits were set. 7. gpio status change interrupt no longer has a direct path to the ac97 sts bit. this causes a wake up event only if the modem controller was in d3 8. resume events on ac_sdin[2:0] cause resume interrupt status bits to be set only if their respective controllers are not in d3. 9. edge detect logic prevents the interrupts from being asserted in case the ac97 controller is switched from d3 to d0 after a wake event. 10. once the interrupt status bits are set, they will cause pirqb# if their respective enable bits were set. one of the audio or the modem drivers will handle the interrupt. 5.22.2 ac-link overview the ich5 is an ac ?97 2.3 controller that communicates with companion codecs via a digital serial link called the ac-link. all digital audio/modem streams and command/status information is communicated over the ac-link. the ac-link is a bi-directional, serial pcm digital stream. it handles multiple input and output data streams, as well as control register accesses, employing a time division multiplexed (tdm) scheme. the ac-link architecture provides for data transfer through individual frames transmitted in a serial fashion. each frame is divided into 12 outgoing and 12 incoming data streams, or slots. the architecture of the ich5 ac-link allows a maximum of three codecs to be connected. figure 24 shows a three codec topology of the ac-link for the ich5. 254 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description the ac-link consists of a five signal interface between the controller and codec. table 129 indicates the ac-link signal pins on the ich5 and their associated power wells. note: power well voltage levels are 3.3 v figure 26. ac ?97 2.3 controller-codec connection intel ? ich5 primary codec ac / mc / amc ac97 ich4 d ac_sdin2 ac_sdin1 ac_rst# ac_sdout ac_sync ac_bit_clk secondary codec ac / mc / amc tertiary codec ac / mc / amc ac_sdin0 table 126. ac ?97 signals signal name type power well description ac_rst# output resume master hardware reset ac_sync output core 48 khz fixed rate sample sync ac_bit_clk input core 12.288 mhz serial data clock ac_sdout output core serial output data ac_sdin0 input resume serial input data ac_sdin1 input resume serial input data ac_sdin2 input resume serial input data intel ? 82801eb ich5 / 82801er ich5r datasheet 255 functional description ich5 core well outputs may be used as strapping options for the ich5, sampled during system reset. these signals may have weak pullups/pulldowns; however, this will not interfere with link operation. ich5 inputs integrate weak pulldowns to prevent floating traces when a secondary and/ or tertiary codec is not attached. when the shut off bit in the control register is set, all buffers will be turned off and the pins will be held in a steady state, based on these pullups/pulldowns. ac_bit_clk is fixed at 12.288 mhz and is sourced by the primary codec. it provides the necessary clocking to support the twelve 20-bit time slots. ac-link serial data is transitioned on each rising edge of ac_bit_clk. the receiver of ac-link data samples each serial bit on the falling edge of ac_bit_clk. if ac_bit_clk makes no transitions for four consecutive pci clocks, the ich5 assumes the primary codec is not present or not working. it sets bit 28 of the global status register (i/o offset 30h). all accesses to codec registers with this bit set will return data of ffh to prevent system hangs. synchronization of all ac-link data transactions is signaled by the ac ?97 controller via the ac_sync signal, as shown in figure 25 . the primary codec drives the serial bit clock onto the ac-link, which the ac ?97 controller then qualifies with the ac_sync signal to construct data frames. ac_sync, fixed at 48 khz, is derived by dividing down ac_bit_clk. ac_sync remains high for a total duration of 16 ac_bit_clks at the beginning of each frame. the portion of the frame where ac_sync is high is defined as the tag phase. the remainder of the frame where ac_sync is low is defined as the data phase. each data bit is sampled on the falling edge of ac_bit_clk. the ich5 has three ac_sdin pins allowing a single, dual, or triple codec configuration. when multiple codecs are connected, the primary, secondary, and tertiary codecs can be connected to any ac_sdin line. the ich5 does not distinguish between codecs on its ac_sdin[2:0] pins, however the registers do distinguish between ac_sdin0, ac_sdin1, and ac_sdin2 for wake events, etc. if using a modem codec it is recommended to connect it to ac_sdin1. see your platform design guide for a matrix of valid codec configurations. the ich5 does not support optional test modes as outlined in the ac ?97 specification, version 2.3 . figure 27. ac-link protocol sync bit_clk sdin slot ( 1 ) time slot "valid" bits 20.8us (48 khz) slot 1 slot 2 019 019 0 19 0 slot 3 slot 12 81.4 ns 12.288 mhz slot ( 2 ) "0" "0" "0" slot ( 12 ) ("1" = time slot contains valid pcm 19 codec read y end of previous a udio frame tag phase data phase 256 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.22.2.1 ac-link output frame (sdout) a new output frame begins with a low to high transition of ac_sync. ac_sync is synchronous to the rising edge of ac_bit_clk. on the immediately following falling edge of ac_bit_clk, the codec samples the assertion of ac_sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new frame. on the next rising edge of ac_bit_clk, the ich5 transitions ac_sdout into the first bit position of slot 0, or the valid frame bit. each new bit position is presented to the ac-link on a rising edge of ac_bit_clk, and subsequently sampled by the codec on the following falling edge of ac_bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. the output frame data phase corresponds to the multiplexed bundles of all digital output data targeting codec dac inputs and control registers. each output frame supports up to twelve outgoing data time slots. the ich5 generates 16 or 20 bits and stuffs remaining bits with 0s. the output data stream is sent with the most significant bit first, and all invalid slots are stuffed with 0s. when mono audio sample streams are output from the ich5, software must ensure both left and right sample stream time slots are filled with the same data. 5.22.2.2 output slot 0: tag phase slot 0 is considered the tag phase. the tag phase is a special,16-bit time slot wherein each bit conveys a valid tag for its corresponding time slot within the current frame. a 1 in a given bit position of slot 0, indicates that the corresponding time slot within the current frame has been assigned to a data stream and contains valid data. if a slot is tagged invalid with a 0 in the corresponding bit position of slot 0, the ich5 stuffs the corresponding slot with 0s during that slot?s active time. within slot 0, the first bit is a valid frame bit (slot 0, bit 15) which flags the validity of the entire frame. if the valid frame bit is set to 1, this indicates that the current frame contains at least one slot with valid data. when there is no transaction in progress, the ich5 deasserts the frame valid bit. note that after a write to slot 12, that slot will always stay valid, and therefore the frame valid bit remains set. the next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding twelve time slots contain valid data. bits [1:0] of slot 0 are used as codec id bits to distinguish between separate codecs on the link. using the valid bits in the tag phase allows data streams of differing sample rates to be transmitted across the link at its fixed 48 khz frame rate. the codec can control the output sample rate of the ich5 using the slotreq bits as described in the ac ?97 v2.3 specification 5.22.2.3 output slot 1: command address port the command port is used to control features and monitor status of ac ?97 functions including, but not limited to, mixer settings and power management. the control interface architecture supports up to 64, 16-bit read/write registers, addressable on even byte boundaries. only the even registers (00h, 02h, etc.) are valid. output frame slot 1 communicates control register address, and write/ read command information. intel ? 82801eb ich5 / 82801er ich5r datasheet 257 functional description in the case of the multiple codec implementation, accesses to the codecs are differentiated by the driver using address offsets 00h ? 7fh for the primary codec, address offsets 80h ? feh for the secondary codec, and address offsets 100h ? 17fh for the tertiary codec. the differentiation on the link, however, is done via the codec id bits. see section 6.20.2.23 for further details. 5.22.2.4 output slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle as indicated in slot 1, bit 19. if the current command port operation is a read, the entire slot time stuffed with 0s by the ich5. bits [19:4] contain the write data. bits [3:0] are reserved and are stuffed with 0s. 5.22.2.5 output slot 3: pcm playback left channel output frame slot 3 is the composite digital audio left playback stream. typically, this slot is composed of standard pcm (.wav) output samples digitally mixed by the host processor. the ich5 transmits sample streams of 16 bits or 20 bits and stuffs remaining bits with 0s. data in output slots 3 and 4 from the ich5 should be duplicated by software if there is only a single channel out. 5.22.2.6 output slot 4: pcm playback right channel output frame slot 4 is the composite digital audio right playback stream. typically, this slot is composed of standard pcm (.wav) output samples digitally mixed by the host processor. the ich5 transmits sample streams of 16 or 20 bits and stuffs remaining bits with 0s. data in output slots 3 and 4 from the ich5 should be duplicated by software if there is only a single channel out. 5.22.2.7 output slot 5: modem codec output frame slot 5 contains modem dac data. the modem dac output supports 16-bit resolution. at boot time, if the modem codec is supported, the ac ?97 controller driver determines the dac resolution. during normal runtime operation the ich5 stuffs trailing bit positions within this time slot with 0s. 5.22.2.8 output slot 6: pcm playback center front channel when set up for 6-channel mode, this slot is used for the front center channel. the format is the same as slots 3 and 4. if not set up for 6-channel mode, this channel is always stuffed with 0s by ich5. 5.22.2.9 output slots 7?8: pcm playback left and right rear channels when set up for 4 or 6 channel modes, slots 7 and 8 are used for the rear left and right channels. the format for these two channels are the same as slots 3 and 4. 258 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.22.2.10 output slot 9: playback sub woofer channel when set for 6-channel mode, this slot is used for the sub woofer. the format is the same as slot 3. if not set up for 6-channel mode, this channel is always stuffed with 0s by ich5. 5.22.2.11 output slots 10?11: reserved output frame slots 10 ? 11 are reserved and are always stuffed with 0s by the ich5 ac ?97 controller. 5.22.2.12 output slot 12: i/o control the 16 bits of daa and gpio control (output) and status (input) have been directly assigned to bits on slot 12 to minimize latency of access to changing conditions. the value of the bits in this slot are the values written to the gpio control register at offset 54h and d4h (in the case of a secondary codec) in the modem codec i/o space. the following rules govern the usage of slot 12. 1. slot 12 is marked invalid by default on coming out of ac-link reset, and remains invalid until a register write to 54h/d4h. 2. a write to offset 54h/d4h in codec i/o space causes the write data to be transmitted on slot 12 in the next frame, with slot 12 marked valid, and the address/data information to also be transmitted on slots 1 and 2. 3. after the first write to offset 54h/d4h, slot 12 remains valid for all following frames. the data transmitted on slot 12 is the data last written to offset 54h/d4h. any subsequent write to the register causes the new data to be sent out on the next frame. 4. slot 12 gets invalidated after the following events: pci reset, ac ?97 cold reset, warm reset, and hence a wake from s3, s4, or s5. slot 12 remains invalid until the next write to offset 54h/ d4h. 5.22.2.13 ac-link input frame (sdin) there are three ac_sdin lines on the ich5 for use with up to three codecs. each ac_sdin pin can have a codec attached. the input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac ?97 controller. as in the case for the output frame, each ac-link input frame consists of twelve time slots. a new audio input frame begins with a low to high transition of ac_sync. ac_sync is synchronous to the rising edge of ac_bit_clk. on the immediately following falling edge of ac_bit_clk, the receiver samples the assertion of ac_sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of ac_bit_clk, the codec transitions ac_sdin into the first bit position of slot 0 (codec ready bit). each new bit position is presented to ac-link on a rising edge of ac_bit_clk, and subsequently sampled by the ich5 on the following falling edge of ac_bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. ac_sdin data stream must follow the ac ?97 v2.3 specification and be msb justified with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s. ac_sdin data is sampled by the ich5 on the falling edge of ac_bit_clk. intel ? 82801eb ich5 / 82801er ich5r datasheet 259 functional description 5.22.2.14 input slot 0: tag phase input slot 0 consists of a codec ready bit (bit 15), and slot valid bits for each subsequent slot in the frame (bits [14:3]). the codec ready bit within slot 0 (bit 15) indicates whether the codec on the ac-link is ready for register access (digital domain). if the codec ready bit in slot 0 is a 0, the codec is not ready for register access. when the ac-link codec ready bit is a 1, it indicates that the ac-link and codec control and status registers are in a fully operational state. the codec ready bits are visible through the global status register of the ich5. software must further probe the powerdown control/status register in the codec to determine exactly which subsections, if any, are ready. bits [14:3] in slot 0 indicate which slots of the input stream to the ich5 contain valid data, just as in the output frame. the remaining bits in this slot are stuffed with 0s. 5.22.2.15 input slot 1: status address port / slot request bits the status port is used to monitor status of codec functions including, but not limited to, mixer settings and power management. slot 1 must echo the control register index, for historical reference, for the data to be returned in slot 2, assuming that slots 1 and 2 had been tagged valid by the codec in slot 0. for variable sample rate output, the codec examines its sample rate control registers, the state of its fifos, and the incoming sdout tag bits at the beginning of each audio output frame to determine which slotreq bits to set active (low). slotreq bits asserted during the current audio input frame signal which output slots require data from the controller in the next audio output frame. for fixed 48 khz operation the slotreq bits are always set active (low) and a sample is transferred each frame. for variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. 260 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description notes: 1. slot 3 request and slot 4 request bits must be the same value, i.e. set or cleared in tandem. this is also true for the slot 7 and slot 8 request bits, as well as the slot 6 and slot 9 request bits. as shown in table 127 , slot 1 delivers codec control register read address and multiple sample rate slot request flags for all output slots of the controller. when a slot request bit is set by the codec, the controller returns data in that slot in the next output frame. slot request bits for slots 3 and 4 are always set or cleared in tandem (i.e., both are set or cleared). when set, the input slot 1 tag bit only pertains to status address port data from a previous read. slotreq bits are always valid independent of the slot 1 tag bit. 5.22.2.16 input slot 2: status data port the status data port receives 16-bit control register read data. bit [19:4]: control register read data bit [3:0]: reserved. 5.22.2.17 input slot 3: pcm record left channel input slot 3 is the left channel input of the codec. the ich5 supports 16-bit sample resolution. samples transmitted to the ich5 must be in left/right channel order. 5.22.2.18 input slot 4: pcm record right channel input slot 4 is the right channel input of the codec. the ich5 supports 16-bit sample resolution. samples transmitted to the ich5 must be in left/right channel order. 5.22.2.19 input slot 5: modem line input slot 5 contains msb justified modem data. the ich5 supports 16-bit sample resolution. table 127. input slot 1 bit definitions bit description 19 reserved (set to 0) 18:12 control register index (stuffed with 0s if tagged invalid) 11 slot 3 request: pcm left channel (1) 10 slot 4 request: pcm right channel (1) 9 slot 5 request: modem line 1 8 slot 6 request: pcm center channel (1) 7 slot 7 request: pcm left surround (1) 6 slot 8 request: pcm right surround (1) 5 slot 9 request: pcm lfe channel (1) 4:2 slot request 10?12: not implemented 1:0 reserved (stuffed with 0s) intel ? 82801eb ich5 / 82801er ich5r datasheet 261 functional description 5.22.2.20 input slot 6: optional dedicated microphone record data input slot 6 is a third pcm system input channel available for dedicated use by a microphone. this input channel supplements a true stereo output which enables more precise echo cancellation algorithm for speakerphone applications. the ich5 supports 16-bit resolution for slot 6 input. 5.22.2.21 input slots 7?11: reserved input frame slots 7 ? 11 are reserved for future use and should be stuffed with 0s by the codec, per the ac ?97 specification, version 2.3. 5.22.2.22 input slot 12: i/o status the status of the gpios configured as inputs are to be returned on this slot in every frame. the data returned on the latest frame is accessible to software by reading the register at offset 54h/d4h in the codec i/o space. only the 16 msbs are used to return gpi status. in order for gpi events to cause an interrupt, both the 'sticky' and 'interrupt' bits must be set for that particular gpio pin in regs 50h and 52h. therefore, the interrupt will be signalled until it has been cleared by the controller, which can be much longer than one frame. reads from 54h/d4h are not transmitted across the link in slot 1 and 2. the data from the most recent slot 12 is returned on reads from offset 54h/d4h. 5.22.2.23 register access in the ich5 implementation of the ac-link, up to three codecs can be connected to the sdout pin. the following mechanism is used to address the primary, secondary, and tertiary codecs individually. the primary device uses bit 19 of slot 1 as the direction bit to specify read or write. bits [18:12] of slot 1 are used for the register index. for i/o writes to the primary codec, the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in table 128 . slot 1 is used to transmit the register address, and slot 2 is used to transmit data. for i/o reads to the primary codec, only slot 1 should be valid since only an address is transmitted. for i/o reads only slot 1 valid bit is set, while for i/o writes both slots 1 and 2 valid bits are set. the secondary and tertiary codec registers are accessed using slots 1 and 2 as described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec id bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non-zero value. this allows the secondary or tertiary codec to monitor the slot valid bits of slots 1and 2, and bits [1:0] of slot 0 to determine if the access is directed to the secondary or tertiary codec. if the register access is targeted to the secondary or tertiary codec, slot 1 and 2 will contain the address and data for the register access. since slots 1 and 2 are marked invalid, the primary codec will ignore these accesses. 262 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description when accessing the codec registers, only one i/o cycle can be pending across the ac-link at any time. the ich5 implements write posting on i/o writes across the ac-link (i.e., writes across the link are indicated as complete before they are actually sent across the link). in order to prevent a second i/o write from occurring before the first one is complete, software must monitor the cas bit in the codec access semaphore register which indicates that a codec access is pending. once the cas bit is cleared, then another codec access (read or write) can go through. the exception to this being reads to offset 54h/d4h/154h (slot 12) which are returned immediately with the most recently received slot 12 data. writes to offset 54h, d4h, and 154h (primary, secondary and tertiary codecs), get transmitted across the ac-link in slots 1 and 2 as a normal register access. slot 12 is also updated immediately to reflect the data being written. the controller does not issue back to back reads. it must get a response to the first read before issuing a second. in addition, codec reads and writes are only executed once across the link, and are not repeated. 5.22.3 ac-link low power mode the ac-link signals can be placed in a low-power mode. when the ac ?97 powerdown register (26h), is programmed to the appropriate value, both ac_bit_clk and ac_sdin will be brought to, and held at a logic low voltage level. table 128. output tag slot 0 bit primary access example secondary access example description 15 1 1 frame valid 14 1 0 slot 1 valid, command address bit (primary codec only) 13 1 0 slot 2 valid, command data bit (primary codec only) 12:3 x x slot 3?12 valid 2 0 0 reserved 1:0 00 01 codec id (00 reserved for primary; 01 indicate secondary; 10 indicate tertiary) figure 28. ac-link powerdown timing sdout tag sync bit_clk write to 0x20 data pr4 slot 12 prev. frame tag slot 12 prev. frame sdin note: bit_clk not to scale intel ? 82801eb ich5 / 82801er ich5r datasheet 263 functional description ac_bit_clk and ac_sdin transition low immediately after a write to the powerdown register (26h) with pr4 enabled. when the ac ?97 controller driver is at the point where it is ready to program the ac-link into its low-power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. the ac ?97 controller also drives ac_sync, and ac_sdout low after programming ac ?97 to this low power, halted mode once the codec has been instructed to halt, ac_bit_clk, a special wake up protocol must be used to bring the ac-link to the active mode since normal output and input frames can not be communicated in the absence of ac_bit_clk. once in a low-power mode, the ich5 provides three methods for waking up the ac-link; external wake event, cold reset and warm reset. note: before entering any low-power mode where the link interface to the codec is expected to be powered down while the rest of the system is awake, the software must set the ?shut off? bit in the control register. 5.22.3.1 external wake event codecs can signal the controller to wake the ac-link, and wake the system using ac_sdin. the minimum ac_sdin wake up pulse width is 1 us. the rising edge of ac_sdin0, ac_sdin1 or ac_sdin2 causes the ich5 to sequence through an ac-link warm reset and set the ac97_sts bit in the gpe0_sts register to wake the system. the primary codec must wait to sample ac_sync high and low before restarting ac_bit_clk as diagrammed in figure 27 . the codec that signaled the wake event must keep its ac_sdin high until it has sampled ac_sync having gone high, and then low. the ac-link protocol provides for a cold reset and a warm reset. the type of reset used depends on the system?s current power down state. unless a cold or register reset (a write to the reset register in the codec) is performed, wherein the ac ?97 codec registers are initialized to their default values, registers are required to keep state during all power down modes. once powered down, activation of the ac-link via re-assertion of the ac_sync signal must not occur for a minimum of four audio frame times following the frame in which the power down was triggered. when ac-link powers up, it indicates readiness via the codec ready bit. figure 29. sdin wake signaling sdout tag sync bit_clk write to 0x20 data pr4 slot 12 prev. frame tag slot 12 prev. frame sdin tag slot 1 slot 2 power down frame wake event sleep state new audio frame tag slot 1 slot 2 264 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description 5.22.4 ac ?97 cold reset a cold reset is achieved by asserting ac_rst# for 1 s. by driving ac_rst# low, ac_bit_clk, and ac_sdout will be activated and all codec registers will be initialized to their default power on reset values. ac_rst# is an asynchronous ac ?97 input to the codec. 5.22.5 ac ?97 warm reset a warm reset re-activates the ac-link without altering the current codec register values. a warm reset is signaled by driving ac_sync high for a minimum of 1 s in the absence of ac_bit_clk. within normal frames, ac_sync is a synchronous ac ?97 input to the codec. however, in the absence of ac_bit_clk, ac_sync is treated as an asynchronous input to the codec used in the generation of a warm reset. the codec must not respond with the activation of ac_bit_clk until ac_sync has been sampled low again by the codec. this prevents the false detection of a new frame. note: on receipt of wake up signalling from the codec, the digital controller issues an interrupt if enabled. software then has to issue a warm or cold reset to the codec by setting the appropriate bit in the global control register. 5.22.6 system reset table 129 indicates the states of the link during various system reset and sleep conditions. notes: 1. ich5 core well outputs are used as strapping options for the ich5, sampled during system reset. these signals may have weak pullups/pulldowns on them. the ich5 outputs are driven to the appropriate level prior to ac_rst# being deasserted, preventing a codec from entering test mode. straps are tied to the core well to prevent leakage during a suspend state. 2. the pull-down resistors on these signals are only enabled when the ac-link shut off bit in the ac ?97 global control register is set to 1. all other times, the pull-down resistor is disabled. 3. ac_rst# are held low during s3?s5. it cannot be programmed high during a suspend state. 4. ac_bit_clk and ac_sdin[2:0] are driven low by the codecs during normal states. if the codec is powered during suspend states it holds these signals low. however, if the codec is not present, or not powered in suspend, external pull-down resistors are required. table 129. ac-link state during pcirst# signal power plane i/o during pcirst#/ after pcirst#/ s1 s3 s4/s5 ac_rst# resume 3 output low low cold reset bit (hi) low low ac_sdout core 1 output low running low low low ac_sync core output low running low low low ac_bit_clk core input driven by codec running low 2,4 low 2,4 low 2,4 ac_sdin[2:0] resume input driven by codec running low 2,4 low 2,4 low 2,4 intel ? 82801eb ich5 / 82801er ich5r datasheet 265 functional description the transition of ac_rst# to the deasserted state only occurs under driver control. in the s1sleep state, the state of the ac_rst# signal is controlled by the ac ?97 cold reset# bit (bit 1) in the global control register. ac_rst# is asserted (low) by the ich5 under the following conditions: ? rsmrst# (system reset, including the a reset of the resume well and pcirst#) ? mechanical power up (causes pcirst#) ? write to cf9h hard reset (causes pcirst#) ? transition to s3/s4/s5 sleep states (causes pcirst#) ? write to ac ?97 cold reset# bit in the global control register. hardware never deasserts ac_rst# (i.e., never deasserts the cold reset# bit) automatically. only software can deassert the cold reset# bit and, hence, the ac_rst# signal. this bit, while it resides in the core well, remains cleared upon return from s3/s4/s5 sleep states. the ac_rst# pin remains actively driven from the resume well as indicated. 5.22.7 hardware assist to determine ac_sdin used per codec software first performs a read to one of the audio codecs. the read request goes out on ac_sdout. since under our micro-architecture only one read can be performed at a time on the link, eventually the read data will come back in on one of the ac_sdin[2:0] lines. the codec does this by indicating that status data is valid in its tag, then echoes the read address in slot 1 followed by the read data in slot 2. the new function of the ich5 hardware is to notice which ac_sdin line contains the read return data, and to set new bits in the new register indicating which ac_sdin line the register read data returned on. if it returned on ac_sdin0, bits [1:0] contain the value 00. if it returned on ac_sdin1, the bits contain the value 01, etc. ich5 hardware can set these bits every time register read data is returned from a function 5 read. no special command is necessary to cause the bits to be set. the new driver/bios software reads the bits from this register when it cares to, and can ignore it otherwise. when software is attempting to establish the codec-to-ac_sdin mapping, it will single feed the read request and not pipeline to ensure it gets the right mapping, we cannot ensure the serialization of the access. 5.22.8 software mapping of ac_sdin to dma engine once software has performed the register read to determine codec-to-ac_sdin mapping, it will then either set bits [5:4] or [7:6] in the sdata_in map register to map this codec to the dma engine. after it maps the audio codecs, it sets the ?se? (steer enable) bit, which now lets the hardware know to no longer or the ac_sdin lines, and to use the mappings in the register to steer the appropriate ac_sdin line to the correct dma engines. 266 intel ? 82801eb ich5 / 82801er ich5r datasheet functional description this page is intentionally left blank. intel ? 82801eb ich5 / 82801er ich5r datasheet 267 register and memory mapping register and memory mapping 6 the ich5 contains registers that are located in the processor?s i/o space and memory space and sets of pci configuration registers that are located in pci configuration space. this chapter describes the ich5 i/o and memory maps at the register-set level. register access is also described. register-level address maps and individual register bit descriptions are provided in the following chapters. the following notations and definitions are used in the register/instruction description chapters. ro read only. in some cases, if a register is read only, writes to this register location have no effect. however, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. see the i/o and memory map tables for details. wo write only. in some cases, if a register is write only, reads to this register location have no effect. however, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. see the i/o and memory map tables for details. r/w read/write. a register with this attribute can be read and written. r/wc read/write clear. a register bit with this attribute can be read and written. however, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. r/wo read/write-once. a register bit with this attribute can be written only once after power up. after the first write, the bit becomes read only. default when ich5 is reset, it sets its registers to predetermined default states. the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the ich5 registers accordingly. bold register bits that are highlighted in bold text indicate that the bit is implemented in the ich5. register bits that are not implemented or are hardwired will remain in plain text. 268 intel ? 82801eb ich5 / 82801er ich5r datasheet register and memory mapping 6.1 pci devices and functions the ich5 incorporates a variety of pci functions as shown in table 130 . these functions are divided into four logical devices (b0:d30, b0:d31, b0:d29 and b1:d8). d30 is the hub interface-to-pci bridge, d31 contains the pci-to-lpc bridge, ide controller, sata controller, smbus controller and the ac ?97 audio and modem controller functions and d29 contains the four usb uhci controllers and one usb ehci controller. b1:d8 is the integrated lan controller. note: from a software perspective, the integrated lan controller resides on the ich5?s external pci bus (see section 5.1.2 ). this is typically bus 1, but may be assigned a different number depending on system configuration. if for some reason, the particular system platform does not want to support any one of device 31?s functions 1?6, device 29?s functions, or device 8, they can individually be disabled. the integrated lan controller will be disabled if no platform lan connect component is detected (see section 5.2 ). when a function is disabled, it does not appear at all to the software. a disabled function will not respond to any register reads or writes. this is intended to prevent software from thinking that a function is present (and reporting it to the end-user). notes: 1. the pci to lpc bridge contains registers that control lpc, power management, system management, gpio, processor interface, rtc, interrupts, timers, dma. table 130. pci devices and functions bus:device:function function description bus 0:device 30:function 0 hub interface to pci bridge bus 0:device 31:function 0 pci to lpc bridge 1 bus 0:device 31:function 1 ide controller bus 0:device 31:function 2 new: sata controller bus 0:device 31:function 3 smbus controller bus 0:device 31:function 5 ac?97 audio controller bus 0:device 31:function 6 ac?97 modem controller bus 0:device 29:function 0 usb uhci controller #1 bus 0:device 29:function 1 usb uhci controller #2 bus 0:device 29:function 2 usb uhci controller #3 bus 0:device 29:function 3 new: usb uhci controller #4 bus 0:device 29:function 7 usb 2.0 ehci controller bus n:device 8:function 0 lan controller intel ? 82801eb ich5 / 82801er ich5r datasheet 269 register and memory mapping 6.2 pci configuration map each pci function on the ich5 has a set of pci configuration registers. the register address map tables for these register sets are included at the beginning of the chapter for the particular function. refer to table 204 for a complete list of all pci configuration registers. configuration space registers are accessed through configuration cycles on the pci bus by the host bridge using configuration mechanism #1 detailed in the pci local bus specification, revision 2.3 . some of the pci registers contain reserved bits. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. note the software does not need to perform read, merge, write operation for the configuration address register. in addition to reserved bits within a register, the configuration space contains reserved locations. software should not write to reserved pci configuration locations in the device-specific region (above address offset 3fh). 6.3 i/o map the i/o map is divided into fixed and variable address ranges. fixed ranges cannot be moved, but in some cases can be disabled. variable ranges can be moved and can also be disabled. 6.3.1 fixed i/o address ranges table 131 shows the fixed i/o decode ranges from the processor perspective. note that for each i/o range, there may be separate behavior for reads and writes. the hub interface cycles that go to target ranges that are marked as ?reserved? will not be decoded by the ich5, and will be passed to pci. if a pci master targets one of the fixed i/o target ranges, it will be positively decoded by the ich5 in medium speed. refer to table 205 for a complete list of all fixed i/o registers. address ranges that are not listed or marked ?reserved? are not decoded by the ich5 (unless assigned to one of the variable ranges). 270 intel ? 82801eb ich5 / 82801er ich5r datasheet register and memory mapping table 131. fixed i/o ranges decoded by intel ? ich5 (sheet 1 of 2) i/o address read target write target internal unit 00h?08h dma controller dma controller dma 09h?0eh reserved dma controller dma 0fh dma controller dma controller dma 10h?18h dma controller dma controller dma 19h?1eh reserved dma controller dma 1fh dma controller dma controller dma 20h?21h interrupt controller interrupt controller interrupt 24h?25h interrupt controller interrupt controller interrupt 28h?29h interrupt controller interrupt controller interrupt 2ch?2dh interrupt controller interrupt controller interrupt 2e?2f lpc sio lpc sio forwarded to lpc 30h?31h interrupt controller interrupt controller interrupt 34h?35h interrupt controller interrupt controller interrupt 38h?39h interrupt controller interrupt controller interrupt 3ch?3dh interrupt controller interrupt controller interrupt 40h?42h timer/counter timer/counter pit (8254) 43h reserved timer/counter pit 4e?4f lpc sio lpc sio forwarded to lpc 50h?52h timer/counter timer/counter pit 53h reserved timer/counter pit 60h microcontroller microcontroller forwarded to lpc 61h nmi controller nmi controller processor i/f 62h microcontroller microcontroller forwarded to lpc 63h nmi controller nmi controller processor i/f 64h microcontroller microcontroller forwarded to lpc 65h nmi controller nmi controller processor i/f 66h microcontroller microcontroller forwarded to lpc 67h nmi controller nmi controller processor i/f 70h reserved nmi and rtc controller rtc 71h rtc controller rtc controller rtc 72h rtc controller nmi and rtc controller rtc 73h rtc controller rtc controller rtc 74h rtc controller nmi and rtc controller rtc 75h rtc controller rtc controller rtc 76h rtc controller nmi and rtc controller rtc 77h rtc controller rtc controller rtc 80h dma controller dma controller and lpc or pci dma intel ? 82801eb ich5 / 82801er ich5r datasheet 271 register and memory mapping notes: 1. only if ide standard i/o space is enabled for primary channel and the ide controller is in legacy mode. otherwise, the target is pci. 2. only if ide standard i/o space is enabled for secondary channel and the ide controller is in legacy mode. otherwise, the target is pci. 3. if pos_dec_en bit is enabled, reads from f0h will not be decoded by the ich5. if pos_dec_en is not enabled, reads from f0h will forward to lpc. 81h?83h dma controller dma controller dma 84h?86h dma controller dma controller and lpc or pci dma 87h dma controller dma controller dma 88h dma controller dma controller and lpc or pci dma 89h?8bh dma controller dma controller dma 8ch?8eh dma controller dma controller and lpc or pci dma 08fh dma controller dma controller dma 90h?91h dma controller dma controller dma 92h reset generator reset generator processor i/f 93h?9fh dma controller dma controller dma a0h?a1h interrupt controller interrupt controller interrupt a4h?a5h interrupt controller interrupt controller interrupt a8h?a9h interrupt controller interrupt controller interrupt ach?adh interrupt controller interrupt controller interrupt b0h?b1h interrupt controller interrupt controller interrupt b2h?b3h power management power management power management b4h?b5h interrupt controller interrupt controller interrupt b8h?b9h interrupt controller interrupt controller interrupt bch?bdh interrupt controller interrupt controller interrupt c0h?d1h dma controller dma controller dma d2h?ddh reserved dma controller dma deh?dfh dma controller dma controller dma f0h see note 3 ferr#/ignne# / interrupt controller processor i/f 170h?177h ide controller 2 ide controller 2 forwarded to ide 1f0h?1f7h ide controller 1 ide controller 1 forwarded to ide 376h ide controller 2 ide controller 2 forwarded to ide 3f6h ide controller 1 ide controller 1 forwarded ide 4d0h?4d1h interrupt controller interrupt controller interrupt cf9h reset generator reset generator processor i/f table 131. fixed i/o ranges decoded by intel ? ich5 (sheet 2 of 2) i/o address read target write target internal unit 272 intel ? 82801eb ich5 / 82801er ich5r datasheet register and memory mapping 6.3.2 variable i/o decode ranges table 132 shows the variable i/o decode ranges. they are set using base address registers (bars) or other configuration bits in the various pci configuration spaces. the pnp software (pci or acpi) can use their configuration mechanisms to set and adjust these values. when a cycle is detected on the hub interface, the ich5 positively decodes the cycle. if the response is on the behalf of an lpc device, ich5 forwards the cycle to the lpc interface. refer to table 206 for a complete list of all variable i/o registers. warning: the variable i/o ranges should not be set to conflict with the fixed i/o ranges. unpredictable results if the configuration software allows conflicts to occur. the ich5 does not perform any checks for conflicts. table 132. variable i/o decode ranges range name mappable size (bytes) target acpi anywhere in 64 kb i/o space 64 power management ide bus master anywhere in 64 kb i/o space 16 ide unit usb uhci controller #1 anywhere in 64 kb i/o space 32 usb unit 1 smbus anywhere in 64 kb i/o space 32 smb unit ac?97 audio mixer anywhere in 64 kb i/o space 256 ac?97 unit ac?97 audio bus master anywhere in 64 kb i/o space 64 ac?97 unit ac?97 modem mixer anywhere in 64 kb i/o space 256 ac?97 unit ac?97 modem bus master anywhere in 64 kb i/o space 128 ac?97 unit tco 96 bytes above acpi base 32 tco unit gpio anywhere in 64 kb i/o space 64 gpio unit parallel port 3 ranges in 64 kb i/o space 8 lpc peripheral serial port 1 8 ranges in 64 kb i/o space 8 lpc peripheral serial port 2 8 ranges in 64 kb i/o space 8 lpc peripheral floppy disk controller 2 ranges in 64 kb i/o space 8 lpc peripheral midi 4 ranges in 64 kb i/o space 2 lpc peripheral mss 4 ranges in 64 kb i/o space 8 lpc peripheral soundblaster 2 ranges in 64 kb i/o space 32 lpc peripheral lan anywhere in 64 kb i/o space 64 lan unit usb uhci controller #2 anywhere in 64 kb i/o space 32 usb unit 2 usb uhci controller #3 anywhere in 64 kb i/o space 32 usb unit 3 usb uhci controller #4 anywhere in 64 kb i/o space 32 usb unit 4 lpc generic 1 anywhere in 64 kb i/o space 128 lpc peripheral lpc generic 2 anywhere in 64 kb i/o space 16 lpc peripheral monitors 4:7 anywhere in 64 kb i/o space 16 lpc peripheral or trap on pci native ide primary command anywhere in 64 kb i/o space 8 ide unit native ide primary control anywhere in 64 kb i/o space 4 ide unit native ide secondary command anywhere in 64 kb i/o space 8 ide unit native ide secondary control anywhere in 64 kb i/o space 4 ide unit intel ? 82801eb ich5 / 82801er ich5r datasheet 273 register and memory mapping 6.4 memory map table 133 shows (from the processor perspective) the memory ranges that the ich5 decodes. cycles that arrive from the hub interface that are not directed to any of the internal memory targets that decode directly from hub interface will be driven out on pci. the ich5 may then claim the cycle for it to be forwarded to lpc or claimed by the internal apic. if subtractive decode is enabled, the cycle can be forwarded to lpc. pci cycles generated by an external pci master are positively decoded unless they falls in the pci-to-pci bridge forwarding range (those addresses are reserved for pci peer-to-peer traffic). if the cycle is not in the i/o apic or lpc ranges, it is forwarded up the hub interface to the host controller. pci masters can not access the memory ranges for functions that decode directly from hub interface. table 133. memory decode ranges from processor perspective (sheet 1 of 2) memory range target dependency/comments 0000 0000h?000d ffffh 0010 0000h?tom (top of memory) main memory tom registers in host controller 000e 0000h?000f ffffh flash bios bit 7 in flash bios decode enable register is set fec0 0000h?fec0 0100h i/o apic inside ich5 ffc0 0000h?ffc7 ffffh ff80 0000h?ff87 ffffh flash bios bit 0 in flash bios decode enable register ffc8 0000h?ffcf ffffh ff88 0000h?ff8f ffffh flash bios bit 1 in flash bios decode enable register ffd0 0000h?ffd7 ffffh ff90 0000h?ff97 ffffh flash bios bit 2 in flash bios decode enable register is set ffd8 0000h?ffdf ffffh ff98 0000h?ff9f ffffh flash bios bit 3 in flash bios decode enable register is set ffe0 000h?ffe7 ffffh ffa0 0000h?ffa7 ffffh flash bios bit 4 in flash bios decode enable register is set ffe8 0000h?ffef ffffh ffa8 0000h?ffaf ffffh flash bios bit 5 in flash bios decode enable register is set fff0 0000h?fff7 ffffh ffb0 0000h?ffb7 ffffh flash bios bit 6 in flash bios decode enable register is set. fff8 0000h?ffff ffffh ffb8 0000h?ffbf ffffh flash bios always enabled. the top two, 64-kb blocks of this range can be swapped, as described in section 7.4.1 . ff70 0000h?ff7f ffffh ff30 0000h?ff3f ffffh flash bios bit 3 in flash bios decode enable 2 register is set ff60 0000h?ff6f ffffh ff20 0000h?ff2f ffffh flash bios bit 2 in flash bios decode enable 2 register is set ff50 0000h?ff5f ffffh ff10 0000h?ff1f ffffh flash bios bit 1 in flash bios decode enable 2 register is set ff40 0000h?ff4f ffffh ff00 0000h?ff0f ffffh flash bios bit 0 in flash bios decode enable 2 register is set 4 kb anywhere in 4 gb range integrated lan controller enable via bar in device 29:function 0 (integrated lan controller) 1 kb anywhere in 4 gb range ide expansion 2 enable via standard pci mechanism and bits in ide i/o configuration register (device 31, function 1) 274 intel ? 82801eb ich5 / 82801er ich5r datasheet register and memory mapping notes: 1. these ranges are decoded directly from hub interface. the memory cycles will not be seen on pci. 2. software must not attempt locks to memory mapped i/o ranges for usb ehci, high-precision event timers, and ide expansion. if attempted, the lock is not honored, which means potential deadlock conditions may occur. 6.4.1 boot-block update scheme the ich5 supports a ?top-block swap? mode that has the ich5 swap the top block in the flash bios (the boot block) with another location. this allows for safe update of the boot block (even if a power failure occurs). when the ?top_swap? enable bit is set, the ich5 will invert a16 for cycles targeting flash bios space. when this bit is 0, the ich5 will not invert a16. this bit is automatically set to 0 by rtcrst#, but not by pcirst#. the scheme is based on the concept that the top block is reserved as the ?boot? block, and the block immediately below the top block is reserved for doing boot-block updates. the algorithm is: 1. software copies the top block to the block immediately below the top 2. software checks that the copied block is correct. this could be done by performing a checksum calculation. 3. software sets the top_swap bit. this will invert a16 for cycles going to the flash bios. processor access to ffff_0000h through ffff_ffffh will be directed to fffe_0000h through fffe_ffffh in the flash bios, and processor accesses to fffe_0000h through fffe_ffff will be directed to ffff_0000h through ffff_ffffh. 4. software erases the top block 5. software writes the new top block 6. software checks the new top block 7. software clears the top_swap bit 8. software sets the top_swap lock-down bit if a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. this is because the top_swap bit is backed in the rtc well. note: the top-block swap mode may be forced by an external strapping option (see section 2.21.1 ). when top-block swap mode is forced in this manner, the top_swap bit cannot be cleared by software. a re-boot with the strap removed will be required to exit a forced top-block swap mode. note: top-block swap mode only affects accesses to the flash bios space, not feature space. note: the top-block swap mode has no effect on accesses below fffe_0000h. 1 kb anywhere in 4 gb range usb ehci controller 1,2 enable via standard pci mechanism (device 29, function 7) fed0 x000?fed0 x3ff high-precision event timers 1,2 bios determines the ?fixed? location which is one of four, 1-kb ranges where x (in the first column) is 0h, 1h, 2h, or 3h. all other pci none table 133. memory decode ranges from processor perspective (sheet 2 of 2) memory range target dependency/comments intel ? 82801eb ich5 / 82801er ich5r datasheet 275 lan controller registers (b1:d8:f0) lan controller registers (b1:d8:f0) 7 the ich5 integrated lan controller appears to reside at pci device 8, function 0 on the secondary side of the ich5?s virtual pci-to-pci bridge (see section 5.1.2 ). this is typically bus 1, but may be assigned a different number depending upon system configuration. the lan controller acts as both a master and a slave on the pci bus. as a master, the lan controller interacts with the system main memory to access data for transmission or deposit received data. as a slave, some of the lan controller?s control structures are accessed by the host processor to read or write information to the on-chip registers. the processor also provides the lan controller with the necessary commands and pointers that allow it to process receive and transmit data. 7.1 pci configuration registers (lan controller?b1:d8:f0) note: address locations that are not shown in table 134 should be treated as reserved (see section 6.2 for details). . table 134. lan controller pci register address map (lan controller?b1:d8:f0) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 1051h ro 04?05h pcicmd pci command 0000h ro, rw 06?07h pcists pci status 0290h ro, r/wc 08h rid revision identification see register description ro 0ah scc sub class code 00h ro 0bh bcc base class code 02h ro 0ch cls cache line size 00h r/w 0dh pmlt primary master latency timer 00h r/w 0eh headtyp header type 00h ro 10?13h csr_mem_base csr memory?mapped base address 00000008h r/w, ro 14?17h csr_io_base csr i/o?mapped base address 00000001h r/w, ro 2c?2dh svid subsystem vendor identification 0000h ro 2e?2fh sid subsystem identification 0000h ro 34h cap_ptr capabilities pointer dch ro 3ch int_ln interrupt line 00h r/w 3d int_pn interrupt pin 01h ro 3e min_gnt minimum grant 08h ro 3f max_lat maximum latency 38h ro dch cap_id capability id 01h ro ddh nxt_ptr next item pointer 00h ro de?dfh pm_cap power management capabilities fe21h ro e0?e1h pmcsr power management control/status 0000h r/w, ro, r/wc e3 pcidata pci power management data 00h ro 276 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.1.1 vid?vendor identification register (lan controller?b1:d8:f0) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16 bits 7.1.2 did?device identification register (lan controller?b1:d8:f0) offset address: 02 ? 03h attribute: ro default value: 1051h size: 16 bits bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich5 integrated lan controller. 1. if the eeprom is not present (or not properly programmed), reads to the device id return the default value of 1051h. 2. if the eeprom is present (and properly programmed) and if the value of word 23h is not 0000h or ffffh, the device id is loaded from the eeprom, word 23h after the hardware reset. (see section 7.1.14 - sid, subsystem id of lan controller for detail) intel ? 82801eb ich5 / 82801er ich5r datasheet 277 lan controller registers (b1:d8:f0) 7.1.3 pcicmd?pci command register (lan controller?b1:d8:f0) offset address: 04 ? 05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = enable 1 = disables lan controller to assert its inta signal. 9 fast back to back enable (fbe) ? ro. hardwired to 0. the integrated lan controller will not run fast back-to-back pci cycles. 8 serr# enable (serr_en) ? r/w. 0 = disable 1 = enable. allow serr# to be asserted. 7 wait cycle control (wcc) ? ro. hardwired to 0. not implemented. 6 parity error response (per) ? r/w. 0 = the lan controller will ignore pci parity errors. 1 = the integrated lan controller will take normal action when a pci parity error is detected and will enable generation of parity on the hub interface. 5 vga palette snoop (vps) ? ro. hardwired to 0. not implemented. 4 memory write and invalidate enable (mwie) ? r/w. 0 = disable. the lan controller will not use the memory write and invalidate command. 1 = enable 3 special cycle enable (sce) ? ro. hardwired to 0. the lan controller ignores special cycles. 2 bus master enable (bme) ? r/w. 0 = disable 1 = enable. the intel ? ich5?s integrated may function as a pci bus master. 1 memory space enable (mse) ? r/w. 0 = disable 1 = enable. the ich5?s integrated lan controller will respond to the memory space accesses. 0 i/o space enable (iose) ? r/w. 0 = disable 1 = enable. the ich5?s integrated lan controller will respond to the i/o space accesses. 278 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.1.4 pcists?pci status register (lan controller?b1:d8:f0) offset address: 06 ? 07h attribute: ro, r/wc default value: 0290h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = parity error not detected. 1 = the intel ? ich5?s integrated lan controller has detected a parity error on the pci bus (will be set even if parity error response is disabled in the pci command register). 14 signaled system error (sse) ? r/wc. 0 = integrated lan controller has not asserted serr# 1 = the ich5?s integrated lan controller has asserted serr#. serr# can be routed to cause nmi, smi#, or interrupt. 13 master abort status ( rma) ? r/wc. 0 = this bit is cleared by writing a 1 to the bit location. 1 = the ich5?s integrated lan controller (as a pci master) has generated a master abort. 12 received target abort (rta) ? r/wc. 0 = target abort not received. 1 = the ich5?s integrated lan controller (as a pci master) has received a target abort. 11 signaled target abort (sta) ? ro. hardwired to 0. the device will never signal target abort. 10:9 devsel# timing status (dev_sts) ? ro. 01h = medium timing. 8 data parity error detected (dped) ? r/wc. 0 = parity error not detected (conditions below are not met). 1 = all of the following three conditions have been met: 1.the lan controller is acting as bus master 2.the lan controller has asserted perr# (for reads) or detected perr# asserted (for writes) 3.the parity error response bit in the lan controller?s pci command register is set. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. the device can accept fast back-to- back transactions. 6 user definable features (udf) ? ro. hardwired to 0. not implemented. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. the device does not support 66 mhz pci. 4 capabilities list (cap_list) ? ro. 0 = the eeprom indicates that the integrated lan controller does not support pci power management. 1 = the eeprom indicates that the integrated lan controller supports pci power management. 3 interrupt status (ints) ? ro. this bit indicates that an interrupt is pending. it is independent from the state of the interrupt enable bit in the command register. 2:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 279 lan controller registers (b1:d8:f0) 7.1.5 rid?revision identification register (lan controller?b1:d8:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 7.1.6 scc?sub-class code register (lan controller?b1:d8:f0) offset address: 0ah attribute: ro default value: 00h size: 8 bits 7.1.7 bcc?base-class code register (lan controller?b1:d8:f0) offset address: 0bh attribute: ro default value: 02h size: 8 bits bit description 7:0 revision id (rid) ? ro. this field is an 8-bit value that indicates the revision number for the integrated lan controller. the three least significant bits in this register may be overridden by the id and revision id fields in the eeprom. note: refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. bit description 7:0 sub class code (scc) ? ro. this 8-bit value specifies the sub-class of the device as an ethernet controller. bit description 7:0 base class code (bcc) ? ro. this 8-bit value specifies the base class of the device as a network controller. 280 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.1.8 cls?cache line size register (lan controller?b1:d8:f0) offset address: 0ch attribute: rw default value: 00h size: 8 bits 7.1.9 pmlt?primary master latency timer register (lan controller?b1:d8:f0) offset address: 0dh attribute: r/w default value: 00h size: 8 bits 7.1.10 headtyp?header type register (lan controller?b1:d8:f0) offset address: 0eh attribute: ro default value: 00h size: 8 bits bit description 7:5 reserved 4:3 cache line size (cls) ? rw. 00 = memory write and invalidate (mwi) command will not be used by the integrated lan controller. 01 = mwi command will be used with cache line size set to 8 dwords (only set if a value of 08h is written to this register). 10 = mwi command will be used with cache line size set to 16 dwords (only set if a value of 10h is written to this register). 11 = invalid. mwi command will not be used. 2:0 reserved bit description 7:3 master latency timer count (mltc) ? r/w. this field defines the number of pci clock cycles that the integrated lan controller may own the bus while acting as bus master. 2:0 reserved bit description 7 multi-function device (mfd) ? ro. hardwired to 0 to indicate a single function device. 6:0 header type (htype) ? ro. this 7-bit field identifies the header layout of the configuration space as an ethernet controller. intel ? 82801eb ich5 / 82801er ich5r datasheet 281 lan controller registers (b1:d8:f0) 7.1.11 csr_mem_base ? csr memory-mapped base address register (lan controller?b1:d8:f0) offset address: 10 ? 13h attribute: r/w, ro default value: 00000008h size: 32 bits note: the ich5?s integrated lan controller requires one bar for memory mapping. software determines which bar (memory or i/o) is used to access the lan controller?s csr registers. 7.1.12 csr_io_base ? csr i/o-mapped base address register (lan controller?b1:d8:f0) offset address: 14 ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits note: the ich5?s integrated lan controller requires one bar for memory mapping. software determines which bar (memory or i/o) is used to access the lan controller?s csr registers. 7.1.13 svid ? subsystem vendor identification register (lan controller?b1:d8:f0) offset address: 2c ? 2d attribute: ro default value: 0000h size: 16 bits bit description 31:12 base address (mem_addr) ? r/w. this field contains the upper 20 bits of the base address provides 4 kb of memory-mapped space for the lan controller?s csr registers. 11:4 reserved 3 prefetchable (mem_pf) ? ro. hardwired to 0 to indicate that this is not a pre-fetchable memory- mapped address range. 2:1 type (mem_type) ? ro. hardwired to 00b to indicate the memory-mapped address range may be located anywhere in 32-bit address space. 0 memory-space indicator (mem_space) ? ro. hardwired to 0 to indicate that this base address maps to memory space. bit description 31:16 reserved 15:6 base address (io_addr) ? r/w. this field provides 64 bytes of i/o-mapped address space for the lan controller?s csr. 5:1 reserved 0 i/o space indicator (io_space) ? ro. hardwired to 1 to indicate that this base address maps to i/o space. bit description 15:0 subsystem vendor id (svid) ? ro. see section 7.1.14 for details. 282 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.1.14 sid ? subsystem identification register (lan controller?b1:d8:f0) offset address: 2e ? 2fh attribute: ro default value: 0000h size: 16 bits note: the ich5?s integrated lan controller provides support for configurable subsystem id and subsystem vendor id fields. after reset, the lan controller automatically reads addresses ah through ch, and 23h of the eeprom. the lan controller checks bits 15:13 in the eeprom word ah, and functions according to table 135 . notes: 1. the revision id is subject to change according to the silicon stepping. 2. the device id is loaded from word 23h only if the value of word 23h is not 0000h or ffffh 7.1.15 cap_ptr ? capabilities pointer register (lan controller?b1:d8:f0) offset address: 34h attribute: ro default value: dch size: 8 bits 7.1.16 int_ln ? interrupt line register (lan controller?b1:d8:f0) offset address: 3ch attribute: r/w default value: 00h size: 8 bits bit description 15:0 subsystem id (sid) ? ro. table 135. configuration of subsystem id and subsystem vendor id via eeprom bits 15:14 bit 13 device id vendor id revision id subsystem id subsystem vendor id 11b, 10b, 00b x 1051h 8086h 00h 0000h 0000h 01b 0b word 23h 8086h 00h word bh word ch 01b 1b word 23h word ch 80h + word ah, bits 10:8 word bh word ch bit description 7:0 capabilities pointer (cap_ptr) ? ro. hardwired to dch to indicate the offset within configuration space for the location of the power management registers. bit description 7:0 interrupt line (int_ln) ? r/w. this field identifies the system interrupt line to which the lan controller?s pci interrupt request pin (as defined in the interrupt pin register) is routed. intel ? 82801eb ich5 / 82801er ich5r datasheet 283 lan controller registers (b1:d8:f0) 7.1.17 int_pn ? interrupt pin register (lan controller?b1:d8:f0) offset address: 3dh attribute: ro default value: 01h size: 8 bits 7.1.18 min_gnt ? minimum grant register (lan controller?b1:d8:f0) offset address: 3eh attribute: ro default value: 08h size: 8 bits 7.1.19 max_lat ? maximum latency register (lan controller?b1:d8:f0) offset address: 3fh attribute: ro default value: 38h size: 8 bits 7.1.20 cap_id ? capability identification register (lan controller?b1:d8:f0) offset address: dch attribute: ro default value: 01h size: 8 bits bit description 7:0 interrupt pin (int_pn) ? ro. hardwired to 01h to indicate that the lan controller?s interrupt request is connected to pirqa#. however, in the intel ? ich5 implementation, when the lan controller interrupt is generated pirqe# will go active, not pirqa#. note that if the pirqe# signal is used as a gpio, the external visibility will be lost (though pirqe# will still go active internally). bit description 7:0 minimum grant (min_gnt) ? ro. this field indicates the amount of time (in increments of 0.25 s) that the lan controller needs to retain ownership of the pci bus when it initiates a transaction. bit description 7:0 maximum latency (max_lat) ? ro. this field defines how often (in increments of 0.25 s) the lan controller needs to access the pci bus. bit description 7:0 capability id (cap_id) ? ro. hardwired to 01h to indicate that the intel ? ich5?s integrated lan controller supports pci power management. 284 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.1.21 nxt_ptr ? next item pointer register (lan controller?b1:d8:f0) offset address: ddh attribute: ro default value: 00h size: 8 bits 7.1.22 pm_cap ? power management capabilities register (lan controller?b1:d8:f0) offset address: de ? dfh attribute: ro default value: fe21h size: 16 bits bit description 7:0 next item pointer (nxt_ptr) ? ro. hardwired to 00b to indicate that power management is the last item in the capabilities list. bit description 15:11 pme support (pme_sup) ? ro. hardwired to 11111b. this 5-bit field indicates the power states in which the lan controller may assert pme#. the lan controller supports wake-up in all power states. 10 d2 support (d2_sup) ? ro. hardwired to 1 to indicate that the lan controller supports the d2 power state. 9 d1 support (d1_sup) ? ro. hardwired to 1 to indicate that the lan controller supports the d1 power state. 8:6 auxiliary current (aux_cur) ? ro. hardwired to 000b to indicate that the lan controller implements the data registers. the auxiliary power consumption is the same as the current consumption reported in the d3 state in the data register. 5 device specific initialization (dsi) ? ro. hardwired to 1 to indicate that special initialization of this function is required (beyond the standard pci configuration header) before the generic class device driver is able to use it. dsi is required for the lan controller after d3-to-d0 reset. 4 reserved 3 pme clock (pme_clk) ? ro. hardwired to 0 to indicate that the lan controller does not require a clock to generate a power management event. 2:0 version (ver) ? ro. hardwired to 010b to indicate that the lan controller complies with of the pci power management specification, revision 1.1. intel ? 82801eb ich5 / 82801er ich5r datasheet 285 lan controller registers (b1:d8:f0) 7.1.23 pmcsr ? power management control/status register (lan controller?b1:d8:f0) offset address: e0 ? e1h attribute: ro, r/w, r/wc default value: 0000h size: 16 bits bit description 15 pme status (pme_stat) ? r/wc. 0 = software clears this bit by writing a 1 to it. this also deasserts the pme# signal and clears the pme status bit in the power management driver register. when the pme# signal is enabled, the pme# signal reflects the state of the pme status bit. 1 = set upon occurrence of a wake-up event, independent of the state of the pme enable bit. 14:13 data scale (dscale) ? ro. this field indicates the data register scaling factor. it equals 10b for registers 0 through eight and 00b for registers nine through fifteen, as selected by the ?data select? field. 12:9 data select (dsel) ? r/w. this field is used to select which data is reported through the data register and data scale field. 8 pme enable (pme_en) ? r/w. this bit enables the intel ? ich5?s integrated lan controller to assert pme#. 0 = the device will not assert pme#. 1 = enable pme# assertion when pme status is set. 7:5 reserved 4 dynamic data (dyn_dat) ? ro. hardwired to 0 to indicate that the device does not support the ability to monitor the power consumption dynamically. 3:2 reserved 1:0 power state (pwr_st) ? r/w. this 2-bit field is used to determine the current power state of the integrated lan controller, and to put it into a new power state. the definition of the field values is as follows: 00 = d0 01 = d1 10 = d2 11 = d3 286 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.1.24 pcidata ? pci power management data register (lan controller?b1:d8:f0) offset address: e3h attribute: ro default value: 00h size: 8 bits the data register is an 8-bit read only register that provides a mechanism for the ich5?s integrated lan controller to report state dependent maximum power consumption and heat dissipation. the value reported in this register depends on the value written to the data select field in the pmcsr register. the power measurements defined in this register have a dynamic range of 0 w to 2.55 w with 0.01 w resolution, scaled according to the data scale field in the pmcsr. the structure of the data register is given in table 136 . bit description 7:0 power management data (pwr_mgt) ? ro. state dependent power consumption and heat dissipation data. table 136. data register structure data select data scale data reported 0 2 d0 power consumption 1 2 d1 power consumption 2 2 d2 power consumption 3 2 d3 power consumption 4 2 d0 power dissipated 5 2 d1 power dissipated 6 2 d2 power dissipated 7 2 d3 power dissipated 8 2 common function power dissipated 9?15 0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 287 lan controller registers (b1:d8:f0) 7.2 lan control / status registers (csr) ( lan controller? b1:d8:f0) table 137. intel ? ich5 integrated lan controller csr space register address map offset mnemonic register name default type 01h?00h scb_sta system control block status word 0000h r/wc, ro 03h?02h scb_cmd system control block command word 0000h r/w, wo 07h?04h scb_genpnt system control block general pointer 0000 0000h r/w 0bh?08h port port interface 0000 0000h r/w (special) 0dh?0ch ? reserved ? ? 0eh eeprom_cntl eeprom control 00 r/w, ro, wo 0fh ? reserved ? ? 13h?10h mdt_cntl management data interface control 0000 0000h r/w (special) 17h?14h rec_dma_bc receive dma byte count 0000 0000h ro 18h early receive interrupt 00h r/w 1a?19h flow_cntl flow control 0000h ro, r/w (special) 1bh pmdr power management driver 00h r/wc 1ch gencntl general control 00h r/w 1dh gensta general status 00h ro 1eh ? reserved ? ? 1fh smb_pci smb via pci 27h r/w 20h?3ch ? reserved ? ? 288 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.2.1 scb_sta?system control block status word register (lan controller?b1:d8:f0) offset address: 00 ? 01h attribute: r/wc, ro default value: 0000h size: 16 bits the ich5?s integrated lan controller places the status of its command unit (cu) and receive unit (rc) and interrupt indications in this register for the processor to read. bit description 15 command unit (cu) executed (cx) ? r/wc. 0 = software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = interrupt signaled because the cu has completed executing a command with its interrupt bit set. 14 frame received (fr) ? r/wc. 0 = software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = interrupt signaled because the receive unit (ru) has finished receiving a frame. 13 cu not active (cna) ? r/wc. 0 = software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = the command unit left the active state or entered the idle state. there are two, distinct states of the cu. when configured to generate cna interrupt, the interrupt will be activated when the cu leaves the active state and enters either the idle or the suspended state. when configured to generate ci interrupt, an interrupt will be generated only when the cu enters the idle state. 12 receive not ready (rnr) ? r/wc. 0 = software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = interrupt signaled because the receive unit left the ready state. this may be caused by an ru abort command, a no resources situation, or set suspend bit due to a filled receive frame descriptor. 11 management data interrupt (mdi) ? r/wc. 0 = software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = set when a management data interface read or write cycle has completed. the management data interrupt is enabled through the interrupt enable bit (bit 29 in the management data interface control register in the csr). 10 software interrupt (swi) ? r/wc. 0 = software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = set when software generates an interrupt. 9 early receive (er) ? r/wc. 0 = software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = indicates the occurrence of an early receive interrupt. 8 flow control pause (fcp) ? r/wc. 0 = software acknowledges the interrupt and clears this bit by writing a 1 to the bit position. 1 = indicates flow control pause interrupt. 7:6 command unit status (cus) ? ro. 00 = idle 01 = suspended 10 = lpq (low priority queue) active 11 = hpq (high priority queue) active intel ? 82801eb ich5 / 82801er ich5r datasheet 289 lan controller registers (b1:d8:f0) 7.2.2 scb_cmd?system control block command word register (lan controller?b1:d8:f0) offset address: 02 ? 03h attribute: r/w, wo default value: 0000h size: 16 bits the processor places commands for the command and receive units in this register. interrupts are also acknowledged in this register. 5:2 receive unit status (rus) ? ro. 0000 = idle 1000 = reserved 0001 = suspended 1001 = suspended with no more rbds 0010 = no resources 1010 = no resources due to no more rbds 0011 = reserved 1011 = reserved 0100 = ready 1100 = ready with no rbds present 0101 = reserved 1101 = reserved 0110 = reserved 1110 = reserved 0111 = reserved 1111 = reserved 1:0 reserved bit description bit description 15 cx mask (cx_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of a cx interrupt. 14 fr mask (fr_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of an fr interrupt. 13 cna mask (cna_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of a cna interrupt. 12 rnr mask (rnr_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of an rnr interrupt. 11 er mask (er_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of an er interrupt. 10 fcp mask (fcp_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of an fcp interrupt. 9 software generated interrupt (si) ? wo. 0 = no effect. 1 = setting this bit causes the lan controller to generate an interrupt. 8 interrupt mask (im) ? r/w. this bit enables or disables the lan controller?s assertion of the inta# signal. this bit has higher precedence that the specific interrupt mask bits and the si bit. 0 = enable the assertion of inta#. 1 = disable the assertion of inta#. 290 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7:4 command unit command (cuc) ? r/w. valid values are listed below. all other values are reserved. 0000 = nop: does not affect the current state of the unit. 0001 = cu start : start execution of the first command on the cbl. a pointer to the first cb of the cbl should be placed in the scb general pointer before issuing this command. the cu start command should only be issued when the cu is in the idle or suspended states (never when the cu is in the active state), and all of the previously issued command blocks have been processed and completed by the cu. sometimes it is only possible to determine that all command blocks are completed by checking that the complete bit is set in all previously issued command blocks. 0010 = cu resume: resume operation of the command unit by executing the next command. this command will be ignored if the cu is idle. 0011 = cu hpq start: start execution of the first command on the high priority cbl. a pointer to the first cb of the hpq cbl should be placed in the scb general pointer before issuing this command. 0100 = load dump counters address: indicates to the device where to write dump data when using the dump statistical counters or dump and reset statistical counters commands. this command must be executed at least once before any usage of the dump statistical counters or dump and reset statistical counters commands. the address of the dump area must be placed in the general pointer register. 0101 = dump statistical counters: tells the device to dump its statistical counters to the area designated by the load dump counters address command. 0110 = load cu base: the device?s internal cu base register is loaded with the value in the csb general pointer. 0111 = dump and reset statistical counters: indicates to the device to dump its statistical counters to the area designated by the load dump counters address command, and then to clear these counters. 1010 = cu static resume: resume operation of the command unit by executing the next command. this command will be ignored if the cu is idle. this command should be used only when the cu is in the suspended state and has no pending cu resume commands. 1011 = cu hpq resume: resume execution of the first command on the hpq cbl. this command will be ignored if the hpq was never started. 3 reserved 2:0 receive unit command ( ruc) ? r/w. valid values are: 000 = nop: does not affect the current state of the unit. 001 = ru start: enables the receive unit. the pointer to the rfa must be placed in the scb general pointer before using this command. the device pre-fetches the first rfd and the first rbd (if in flexible mode) in preparation to receive incoming frames that pass its address filtering. 010 = ru resume: resume frame reception (only when in suspended state). 011 = rcv dma redirect: resume the rcv dma when configured to ?direct dma mode.? the buffers are indicated by an rbd chain which is pointed to by an offset stored in the general pointer register (this offset will be added to the ru base). 100 = ru abort: abort ru receive operation immediately. 101 = load header data size (hds): this value defines the size of the header portion of the rfds or receive buffers. the hds value is defined by the lower 14 bits of the scb general pointer, so bits 31:15 should always be set to 0s when using this command. once a load hds command is issued, the device expects only to find header rfds, or be used in ?rcv direct dma mode? until it is reset. note that the value of hds should be an even, non-zero number. 110 = load ru base: the device?s internal ru base register is loaded with the value in the scb general pointer. 111 = rbd resume: resume frame reception into the rfa. this command should only be used when the ru is already in the ?no resources due to no rbds? state or the ?suspended with no more rbds? state. bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 291 lan controller registers (b1:d8:f0) 7.2.3 scb_genpnt?system control block general pointer register (lan controller?b1:d8:f0) offset address: 04 ? 07h attribute: r/w default value: 0000 0000h size: 32 bits 7.2.4 port?port interface register (lan controller?b1:d8:f0) offset address: 08 ? 0bh attribute: r/w (special) default value: 0000 0000h size: 32 bits the port interface allows the processor to reset the ich5?s internal lan controller, or perform an internal self test. the port dword may be written as a 32-bit entity, two 16-bit entities, or four 8-bit entities. the lan controller will only accept the command after the high byte (offset 0bh) is written; therefore, the high byte must be written last. bit description 15:0 scb general pointer ? r/w. the scb general pointer register is programmed by software to point to various data structures in main memory depending on the current scb command word. bit description 31:4 pointer field (port_ptr) ? r/w (special). a 16-byte aligned address must be written to this field when issuing a self-test command to the port interface.the results of the self test will be written to the address specified by this field. 3:0 port function selection (port_func) ? r/w (special). valid values are listed below. all other values are reserved. 0000 = port software reset: completely resets the lan controller (all csr and pci registers). this command should not be used when the device is active. if a port software reset is desired, software should do a selective reset (described below), wait for the port register to be cleared (completion of the selective reset), and then issue the port software reset command. software should wait approximately 10 s after issuing this command before attempting to access the lan controller?s registers again. 0001 = self test: the self-test begins by issuing an internal selective reset followed by a general internal self-test of the lan controller. the results of the self-test are written to memory at the address specified in the pointer field of this register. the format of the self-test result is shown in table 138 . after completing the self-test and writing the results to memory, the lan controller will execute a full internal reset and will re-initialize to the default configuration. self-test does not generate an interrupt of similar indicator to the host processor upon completion. 0010 = selective reset: sets the cu and ru to the idle state, but otherwise maintains the current configuration parameters (ru and cu base, hdssize, error counters, configure information and individual/multicast addresses are preserved). software should wait approximately 10 s after issuing this command before attempting to access the lan controller?s registers again. 292 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.2.5 eeprom_cntl?eeprom control register (lan controller?b1:d8:f0) offset address: 0eh attribute: ro, r/w, wo default value: 00h size: 8 bits the eeprom control register is a 16-bit field that enables a read from and a write to the external eeprom. table 138. self-test results format bit description 31:13 reserved 12 general self-test result (self_tst) ? r/w (special). 0 = pass 1 = fail 11:6 reserved 5 diagnose result (diag_rslt) ? r/w (special). this bit provides the result of an internal diagnostic test of the serial subsystem. 0 = pass 1 = fail 4 reserved 3 register result (reg_rslt) ? r/w (special). this bit provides the result of a test of the internal parallel subsystem registers. 0 = pass 1 = fail 2 rom content result (rom_rslt) ? r/w (special). this bit provides the result of a test of the internal microcode rom. 0 = pass 1 = fail 1:0 reserved bit description 7:4 reserved 3 eeprom serial data out (eedo) ? ro. note that this bit represents ?data out? from the perspective of the eeprom device. this bit contains the value read from the eeprom when performing read operations. 2 eeprom serial data in (eedi) ? wo. note that this bit represents ?data in? from the perspective of the eeprom device. the value of this bit is written to the eeprom when performing write operations. 1 eeprom chip select (eecs) ? r/w. 0 = drives the intel ? ich5?s ee_cs signal low to disable the eeprom. this bit must be set to 0 for a minimum of 1 s between consecutive instruction cycles. 1 = drives the ich5?s ee_cs signal high, to enable the eeprom. 0 eeprom serial clock (eesk) ? r/w. toggling this bit clocks data into or out of the eeprom. software must ensure that this bit is toggled at a rate that meets the eeprom component?s minimum clock frequency specification. 0 = drives the ich5?s ee_shclk signal low. 1 = drives the ich5?s ee_shclk signal high. intel ? 82801eb ich5 / 82801er ich5r datasheet 293 lan controller registers (b1:d8:f0) 7.2.6 mdi_cntl?management data interface (mdi) control register (lan controller?b1:d8:f0) offset address: 10 ? 13h attribute: r/w (special) default value: 0000 0000h size: 32 bits the management data interface (mdi) control register is a 32-bit field and is used to read and write bits from the lan connect component. this register may be written as a 32-bit entity, two 16-bit entities, or four 8-bit entities. the lan controller will only accept the command after the high byte (offset 13h) is written; therefore, the high byte must be written last. 7.2.7 rec_dma_bc?receive dma byte count register (lan controller?b1:d8:f0) offset address: 14 ? 17h attribute: ro default value: 0000 0000h size: 32 bits bit description 31:30 these bits are reserved and should be set to 00b. 29 interrupt enable ? r/w (special). 0 = disable 1 = enables the lan controller to assert an interrupt to indicate the end of an mdi cycle. 28 ready ? r/w (special). 0 = expected to be reset by software at the same time the command is written. 1 = set by the lan controller at the end of an mdi transaction. 27:26 opcode ? r/w (special). these bits define the opcode: 00 = reserved 01 = mdi write 10 = mdi read 11 = reserved 25:21 lan connect address ? r/w (special). this field of bits contains the lan connect address. 20:16 lan connect register address ? r/w (special). this field contains the lan connect register address. 15:0 data ? r/w (special). in a write command, software places the data bits in this field, and the lan controller transfers the data to the external lan connect component. during a read command, the lan controller reads these bits serially from the lan connect, and software reads the data from this location. bit description 31:0 receive dma byte count ? ro. this field keeps track of how many bytes of receive data have been passed into host memory via dma. 294 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.2.8 erec_intr?early receive interrupt register (lan controller?b1:d8:f0) offset address: 18h attribute: r/w default value: 00h size: 8 bits the early receive interrupt register allows the internal lan controller to generate an early interrupt depending on the length of the frame. the lan controller will generate an interrupt at the end of the frame regardless of whether or not early receive interrupts are enabled. note: it is recommended that software not use this register unless receive interrupt latency is a critical performance issue in that particular software environment. using this feature may reduce receive interrupt latency, but will also result in the generation of more interrupts, which can degrade system efficiency and performance in some environments. bit description 7:0 early receive count ? r/w. when some non-zero value x is programmed into this register, the lan controller will set the er bit in the scb status word register and assert inta# when the byte count indicates that there are x quadwords remaining to be received in the current frame (based on the type/length field of the received frame). no early receive interrupt will be generated if a value of 00h (the default value) is programmed into this register. intel ? 82801eb ich5 / 82801er ich5r datasheet 295 lan controller registers (b1:d8:f0) 7.2.9 flow_cntl?flow control register (lan controller?b1:d8:f0) offset address: 19 ? 1ah attribute: ro, r/w (special) default value: 0000h size: 16 bits bit description 15:13 reserved 12 fc paused low ? ro. 0 = cleared when the fc timer reaches 0, or a pause frame is received. 1 = set when the lan controller receives a pause low command with a value greater than 0. 11 fc paused ? ro. 0 = cleared when the fc timer reaches 0. 1 = set when the lan controller receives a pause command regardless of its cause (fifo reaching flow control threshold, fetching a receive frame descriptor with its flow control pause bit set, or software writing a 1 to the xoff bit). 10 fc full ? ro. 0 = cleared when the fc timer reaches 0. 1 = set when the lan controller sends a pause command with a value greater than 0. 9 xoff ? r/w (special). this bit should only be used if the lan controller is configured to operate with ieee frame-based flow control. 0 = this bit can only be cleared by writing a 1 to the xon bit (bit 8 in this register). 1 = writing a 1 to this bit forces the xoff request to 1 and causes the lan controller to behave as if the fifo extender is full. this bit will also be set to 1 when an xoff request due to an ?rfd xoff? bit. 8 xon ? wo. this bit should only be used if the lan controller is configured to operate with ieee frame-based flow control. 0 = this bit always returns 0 on reads. 1 = writing a 1 to this bit resets the xoff request to the lan controller, clearing bit 9 in this register. 7:3 reserved 2:0 flow control threshold ? r/w. the lan controller can generate a flow control pause frame when its receive fifo is almost full. the value programmed into this field determines the number of bytes still available in the receive fifo when the pause frame is generated. free bytes bits 2:0 in receive fifocomment 000 0.50 kb fast system (recommended default) 001 1.00 kb 010 1.25 kb 011 1.50 kb 100 1.75 kb 101 2.00 kb 110 2.25 kb 111 2.50 kb slow system 296 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.2.10 pmdr?power management driver register (lan controller?b1:d8:f0) offset address: 1bh attribute: r/wc default value: 00h size: 8 bits the ich5?s internal lan controller provides an indication in the pmdr that a wake-up event has occurred. bit description 7 link status change indication ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the link status change bit is set following a change in link status. 6 magic packet ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when a magic packet is received regardless of the magic packet wake-up disable bit in the configuration command and the pme enable bit in the power management csr. 5 interesting packet ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when an ?interesting? packet is received. interesting packets are defined by the lan controller packet filters. 4:3 reserved 2 asf enabled ? ro. this bit is set to 1 when the lan controller is in asf mode. 1 tco request ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set to 1b when the lan controller is busy with tco activity. 0 pme status ? r/wc. this bit is a reflection of the pme status bit in the power management control/status register (pmcsr). 0 = software clears this bit by writing a 1 to it.this also clears the pme status bit in the pmcsr and deasserts the pme signal. 1 = set upon a wake-up event, independent of the pme enable bit. intel ? 82801eb ich5 / 82801er ich5r datasheet 297 lan controller registers (b1:d8:f0) 7.2.11 gencntl?general control register (lan controller?b1:d8:f0) offset address: 1ch attribute: r/w default value: 00h size: 8 bits 7.2.12 gensta?general status register (lan controller?b1:d8:f0) offset address: 1dh attribute: ro default value: 00h size: 8 bits bit description 7:4 reserved. these bits should be set to 0000b. 3 lan connect software reset ? r/w. 0 = cleared by software to begin normal lan connect operating mode. software must not attempt to access the lan connect interface for at least 1 ms after clearing this bit. 1 = software can set this bit to force a reset condition on the lan connect interface. 2 reserved. this bit should be set to 0. 1 deep power-down on link down enable ? r/w. 0 = disable 1 = enable. the intel ? ich5?s internal lan controller may enter a deep power-down state (sub- 3 ma) in the d2 and d3 power states while the link is down. in this state, the lan controller does not keep link integrity. this state is not supported for point-to-point connection of two end stations. 0 reserved bit description 7:3 reserved 2 duplex mode ? ro. this bit indicates the wire duplex mode. 0 = half duplex 1 = full duplex 1 speed ? ro. this bit indicates the wire speed. 0 = 10 mbps 1 = 100 mbps 0 link status indication ? ro. this bit indicates the status of the link. 0 = invalid 1 = valid 298 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) 7.2.13 smb_pci?smb via pci register (lan controller?b1:d8:f0) offset address: 1fh attribute: r/w, ro default value: 27h size: 8 bits software asserts sreq when it wants to isolate the pci-accessible smbus to the asf registers/ commands. it waits for sgnt to be asserted. at this point scli, sdao, sclo, and sdai can be toggled/read to force asf controller smbus transactions without affecting the external smbus. after all operations are completed, the bus is returned to idle (sclo=1b,sdao=1b, scli=1b, sdai=1b), sreq is released (written 0b). then sgnt goes low to indicate released control of the bus. the logic in the asf controller only asserts or deasserts sgnt at times when it determines that it is safe to switch (all smbuses that are switched in/out are idle). when in isolation mode (sgnt=1), software can access the ich5 smbus slaves that allow configuration without affecting the external smbus. this includes configuration register accesses and asf command accesses. however, this capability is not available to the external tco controller. when sgnt=0, the bit-banging and reads are reflected on the main smbus and the pcisml_sda0, pcisml_scl0 read only bits. bit description 7:6 reserved 5 pcisml_sclo ? ro. smbus clock from the asf controller. 4 pcisml_sgnt ? ro. smbus isolation grant from the asf controller. 3 pcisml_sreq ? r/w. smbus isolation request to the asf controller. 2 pcisml_sdao ? ro. smbus data from the asf controller. 1 pcisml_sdai ? r/w. smbus data to the asf controller. 0 pcisml_scli ? r/w. smbus clock to the asf controller. intel ? 82801eb ich5 / 82801er ich5r datasheet 299 lan controller registers (b1:d8:f0) 7.2.14 statistical counters (lan controller?b1:d8:f0) the ich5?s integrated lan controller provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. the counters are updated by the lan controller when it completes the processing of a frame (that is, when it has completed transmitting a frame on the link or when it has completed receiving a frame). the statistical counters are reported to the software on demand by issuing the dump statistical counters command or dump and reset statistical counters command in the scb command unit command (cuc) field. table 139. statistical counters (sheet 1 of 2) id counter description 0 transmit good frames this counter contains the number of frames that were transmitted properly on the link. it is updated only after the actual transmission on the link is completed, not when the frame was read from memory as is done for the transmit command block status. 4 transmit maximum collisions (maxcol) errors this counter contains the number of frames that were not transmitted because they encountered the configured maximum number of collisions. 8 transmit late collisions (latecol) errors this counter contains the number of frames that were not transmitted since they encountered a collision later than the configured slot time. 12 transmit underrun errors a transmit underrun occurs because the system bus cannot keep up with the transmission. this counter contains the number of frames that were either not transmitted or retransmitted due to a transmit dma underrun. if the lan controller is configured to retransmit on underrun, this counter may be updated multiple times for a single frame. 16 transmit lost carrier sense (crs) this counter contains the number of frames that were transmitted by the lan controller despite the fact that it detected the de-assertion of crs during the transmission. 20 transmit deferred this counter contains the number of frames that were deferred before transmission due to activity on the link. 24 transmit single collisions this counter contains the number of transmitted frames that encountered one collision. 28 transmit multiple collisions this counter contains the number of transmitted frames that encountered more than one collision. 32 transmit total collisions this counter contains the total number of collisions that were encountered while attempting to transmit. this count includes late collisions and frames that encountered maxcol. 36 receive good frames this counter contains the number of frames that were received properly from the link. it is updated only after the actual reception from the link is completed and all the data bytes are stored in memory. 40 receive crc errors this counter contains the number of aligned frames discarded because of a crc error. this counter is updated, if needed, regardless of the receive unit state. the receive crc errors counter is mutually exclusive of the receive alignment errors and receive short frame errors counters. 44 receive alignment errors this counter contains the number of frames that are both misaligned (for example, crs de-asserts on a non-octal boundary) and contain a crc error. the counter is updated, if needed, regardless of the receive unit state. the receive alignment errors counter is mutually exclusive of the receive crc errors and receive short frame errors counters. 300 intel ? 82801eb ich5 / 82801er ich5r datasheet lan controller registers (b1:d8:f0) the statistical counters are initially set to 0 by the ich5?s integrated lan controller after reset. they cannot be preset to anything other than 0. the lan controller increments the counters by internally reading them, incrementing them and writing them back. this process is invisible to the processor and pci bus. in addition, the counters adhere to the following rules: ? the counters are wrap-around counters. after reaching ffffffffh the counters wrap around to 0. ? the lan controller updates the required counters for each frame. it is possible for more than one counter to be updated as multiple errors can occur in a single frame. ? the counters are 32 bits wide and their behavior is fully compatible with the ieee 802.1 standard. the lan controller supports all mandatory and recommend statistics functions through the status of the receive header and directly through these statistical counters. the processor can access the counters by issuing a dump statistical counters scb command. this provides a ?snapshot,? in main memory, of the internal lan controller statistical counters. the lan controller supports 21 counters. the dump could consist of the either 16, 19, or all 21 counters, depending on the status of the extended statistics counters and tco statistics configuration bits in the configuration command. 48 receive resource errors this counter contains the number of good frames discarded due to unavailability of resources. frames intended for a host whose receive unit is in the no resources state fall into this category. if the lan controller is configured to save bad frames and the status of the received frame indicates that it is a bad frame, the receive resource errors counter is not updated. 52 receive overrun errors this counter contains the number of frames known to be lost because the local system bus was not available. if the traffic problem persists for more than one frame, the frames that follow the first are also lost; however, because there is no lost frame indicator, they are not counted. 56 receive collision detect (cdt) this counter contains the number of frames that encountered collisions during frame reception. 60 receive short frame errors this counter contains the number of received frames that are shorter than the minimum frame length. the receive short frame errors counter is mutually exclusive to the receive alignment errors and receive crc errors counters. a short frame will always increment only the receive short frame errors counter. 64 flow control transmit pause this counter contains the number of flow control frames transmitted by the lan controller. this count includes both the xoff frames transmitted and xon (pause(0)) frames transmitted. 68 flow control receive pause this counter contains the number of flow control frames received by the lan controller. this count includes both the xoff frames received and xon (pause(0)) frames received. 72 flow control receive unsupported this counter contains the number of mac control frames received by the lan controller that are not flow control pause frames. these frames are valid mac control frames that have the predefined mac control type value and a valid address but has an unsupported opcode. 76 receive tco frames this counter contains the number of tco packets received by the lan controller. 78 transmit tco frames this counter contains the number of tco packets transmitted. table 139. statistical counters (sheet 2 of 2) id counter description intel ? 82801eb ich5 / 82801er ich5r datasheet 301 hub interface to pci bridge registers (d30:f0) hub interface to pci bridge registers (d30:f0) 8 the hub interface to pci bridge resides in pci device 30, function 0 on bus #0. this portion of the ich5 implements the buffering and control logic between pci and the hub interface. the arbitration for the pci bus is handled by this pci device. the pci decoder in this device must decode the ranges for the hub interface. all register contents will be lost when core well power is removed. 8.1 pci configuration registers (d30:f0) note: address locations that are not shown in table 140 should be treated as reserved (see section 6.2 for details). . table 140. hub interface pci register address map (hub-pci?d30:f0) (sheet 1 of 2) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 244eh ro 04?05h pcicmd pci command 0001h r/w, ro 06?07h pcists pci status 0080h r/wc, ro 08h rid revision identification see register description ro 0ah scc sub class code 04h ro 0bh bcc base class code 06h ro 0dh pmlt primary master latency timer 00h ro 0eh headtyp header type 01h ro 18h pbus_num primary bus number 00h ro 19h sbus_num secondary bus number 00h r/w 1ah sub_bus_num subordinate bus number 00h r/w 1bh smlt secondary master latency timer 00h r/w 1ch iobase i/o base f0h r/w, ro 1dh iolim i/o limit 00h r/w, ro 1e?1fh secsts secondary status 0280h r/wc, ro 20?21h membase memory base fff0h r/w 22?23h memlim memory limit 0000h r/w 24?25h pref_mem_base prefetchable memory base fff0h r/w 26?27h pref_mem_mlt prefetchable memory limit 0000h r/w 30?31h iobase_hi i/o base upper 16 bits 0000h ro 302 intel ? 82801eb ich5 / 82801er ich5r datasheet hub interface to pci bridge registers (d30:f0) note: refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. 8.1.1 vid?vendor identification register (hub-pci?d30:f0) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16 bits 8.1.2 did?device identification register (hub-pci?d30:f0) offset address: 02 ? 03h attribute: ro default value: 244eh size: 16 bits 32?33h iolimit_hi i/o limit upper 16 bits 0000h ro 3ch int_ln interrupt line 00h ro 3e?3fh bridge_cnt bridge control 0000h r/w, ro 40?43h hi1_cmd hub interface 1 command control 76202802h r/w, ro 44?45h device_hide secondary pci device hiding 00 r/w 50?53h cnf policy configuration 00406402h r/w 70h mtt multi-transaction timer 20h r/w 82h pci_mast_sts pci master status 00h r/wc 90h err_cmd error command 00h r/w 92h err_sts error status 00h r/wc table 140. hub interface pci register address map (hub-pci?d30:f0) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h. bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich5 hub interface to pci bridge. intel ? 82801eb ich5 / 82801er ich5r datasheet 303 hub interface to pci bridge registers (d30:f0) 8.1.3 pcicmd?pci command register (hub-pci?d30:f0) offset address: 04 ? 05h attribute: r/w, ro default value: 0001h size: 16 bits bit description 15:10 reserved 9 fast back to back enable (fbe) ? ro. hardwired to 0. the intel ? ich5 does not support this capability. 8 serr# enable (serr_en) ? r/w. 0 = disable 1 = enable the ich5 to generate an nmi (or smi# if nmi routed to smi#) when the d30:f0 sse bit (offset 06h, bit 14) is set. 7 wait cycle control (wcc) ? ro. hardwired to 0 6 parity error response (per) ? r/w. 0 = the ich5 ignores parity errors on the hub interface. 1 = the ich5 is allowed to report parity errors detected on the hub interface. note: the hp_unsupported bit (d30:f0:40h bit 20) must be cleared in order for this bit to have any effect. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 memory write and invalidate enable (mwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0 by p2p bridge specification. 2 bus master enable (bme) ? r/w. 0 = disable 1 = enable. allows the hub interface-to-pci bridge to accept cycles from pci to run on the hub interface. note: this bit does not affect the cf8h and cfch i/o accesses. cycles that generated from the ich5?s device 31 functionality are not blocked by clearing this bit. (pc/pci cascade mode cycles may be blocked) 1 memory space enable (mse) ? r/w. the ich5 provides this bit as read/writable for software only. however, the ich5 ignores the programming of this bit, and runs hub interface memory cycles to pci. 0 i/o space enable (iose) ? r/w. the ich5 provides this bit as read/writable for software only. however, the ich5 ignores the programming of this bit and runs hub interface i/o cycles to pci that are not intended for usb, ide, or ac ?97. 304 intel ? 82801eb ich5 / 82801er ich5r datasheet hub interface to pci bridge registers (d30:f0) 8.1.4 pcists?pci status register (hub-pci?d30:f0) offset address: 06 ? 07h attribute: r/wc, ro default value: 0080h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = parity error not detected. 1 = indicates that the intel ? ich5 detected a parity error on the hub interface and the hp_unsupported bit (d30:f0:40h bit 20) is 0. this bit gets set even if the parity error response bit (d30:f0:04 bit 6) is not set. 14 signaled system error (sse) ? r/wc. 0 = error described below not detected. 1 = an address, or command parity error, or special cycles data parity error has been detected on the pci bus, and the parity error response bit (d30:f0, offset 04h, bit 6) is set. if this bit is set because of parity error and the d30:f0 serr_en bit (offset 04h, bit 8) is also set, the ich5 will generate an nmi (or smi# if nmi routed to smi#). 13 received master abort (rma) ? r/wc. 0 = master abort not received from hub interface. 1 = ich5 received a master abort from the hub interface device. 12 received target abort (rta) ? r/wc. 0 = target abort not received from hub interface. 1 = ich5 received a target abort from the hub interface device. the tco logic can cause an smi#, nmi, or interrupt based on this bit getting set. 11 signaled target abort (sta) ? r/wc. 0 = ich5 did not signal a target abort on hub interface. 1 = ich5 signals a target abort condition on the hub interface. 10:9 devsel# timing status (dev_sts) ? ro. 00h = fast timing. this register applies to the hub interface; therefore, this field does not matter. 8 master data parity error detected (mdpd) ? r/wc. since this register applies to the hub interface, the ich5 must interpret this bit differently than it is in the pci local bus specification, revision 2.3 . 0 = parity error not detected on hub interface. 1 = ich5 detects a parity error on the hub interface and the parity error response bit in the pci command register (offset 04h, bit 6) is set. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 reserved 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 305 hub interface to pci bridge registers (d30:f0) 8.1.5 rid?revision identification register (hub-pci?d30:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 8.1.6 scc?sub-class code register (hub-pci?d30:f0) offset address: 0ah attribute: ro default value: 04h size: 8 bits 8.1.7 bcc?base-class code register (hub-pci?d30:f0) offset address: 0bh attribute: ro default value: 06h size: 8 bits 8.1.8 pmlt?primary master latency timer register (hub-pci?d30:f0) offset address: 0dh attribute: ro default value: 00h size: 8 bits this register does not apply to hub interface. bit description 7:0 revision id ? ro. 8-bit value that indicates the revision number for the intel ? ich5 hub interface to pci bridge. note: refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. bit description 7:0 sub class code (scc) ? ro. this 8-bit value indicates the category of bridge for the intel ? ich5 hub interface to pci bridge. 04h = pci-to-pci bridge. bit description 7:0 base class code (bcc) ? ro. this 8-bit value indicates the type of device for the intel ? ich5 hub interface to pci bridge. 06h = bridge device. bit description 7:3 master latency timer count (mltc) ? ro. not implemented. 2:0 reserved 306 intel ? 82801eb ich5 / 82801er ich5r datasheet hub interface to pci bridge registers (d30:f0) 8.1.9 headtyp?header type register (hub-pci?d30:f0) offset address: 0eh attribute: ro default value: 01h size: 8 bits 8.1.10 pbus_num?primary bus number register (hub-pci?d30:f0) offset address: 18h attribute: ro default value: 00h size: 8 bits 8.1.11 sbus_num?secondary bus number register (hub-pci?d30:f0) offset address: 19h attribute: r/w default value: 00h size: 8 bits 8.1.12 sub_bus_num?subordinate bus number register (hub-pci?d30:f0) offset address: 1a attribute: r/w default value: 00h size: 8 bits bit description 7 multi-function device (mfd) ? ro. this bit is 0 to indicate a single function device. 6:0 header type (htype) ? ro. this 8-bit field identifies the header layout of the configuration space, which is a pci-to-pci bridge in this case. bit description 7:0 primary bus number ? ro. this field indicates the bus number of the hub interface and is hardwired to 00h. bit description 7:0 secondary bus number ? r/w. this field indicates the bus number of pci. note: when this number is equal to the primary bus number (i.e., bus #0), the intel ? ich5 will run hub interface configuration cycles to this bus number as type 1 configuration cycles on pci. bit description 7:0 subordinate bus number ? r/w. this field specifies the highest pci bus number below the hub interface to pci bridge. if a type 1 configuration cycle from the hub interface does not fall in the secondary-to-subordinate bus ranges of device 30, the intel ? ich5 indicates a master abort back to the hub interface. intel ? 82801eb ich5 / 82801er ich5r datasheet 307 hub interface to pci bridge registers (d30:f0) 8.1.13 smlt?secondary master latency timer register (hub-pci?d30:f0) offset address: 1bh attribute: r/w default value: 00h size: 8 bits this master latency timer (mlt) controls the amount of time that the ich5 will continue to burst data as a master on the pci bus. when the ich5 starts the cycle after being granted the bus, the counter is loaded and starts counting down from the assertion of frame#. if the internal grant to this device is removed, then the expiration of the mlt counter will result in the deassertion of frame#. if the internal grant has not been removed, then the ich5 can continue to own the bus. 8.1.14 iobase?i/o base register (hub-pci?d30:f0) offset address: 1ch attribute: r/w, ro default value: f0h size: 8 bits 8.1.15 iolim?i/o limit register (hub-pci?d30:f0) offset address: 1dh attribute: r/w, ro default value: 00h size: 8 bits bit description 7:3 master latency timer count (mltc) ? r/w. this 5-bit field indicates the number of pci clocks, in 8-clock increments, that the intel ? ich5 remains as master of the bus. 2:0 reserved bit description 7:4 i/o address base bits [15:12] ? r/w. i/o this field provides base bits corresponding to address lines 15:12 for 4-kb alignment. bits 11:0 are assumed to be padded to 000h. 3:0 i/o addressing capability ? ro. this field is hardwired to 0h indicating that the hub interface to pci bridge does not support 32-bit i/o addressing. this means that the i/o base and limit upper address registers must be read only. bit description 7:4 i/o address limit bits [15:12] ? r/w. i/o this field provides base bits corresponding to address lines 15:12 for 4-kb alignment. bits 11:0 are assumed to be padded to fffh. 3:0 i/o addressing capability ? ro. this field is hardwired to 0h indicating that the hub interface-to-pci bridge does not support 32-bit i/o addressing. this means that the i/o base and limit upper address registers must be read only. 308 intel ? 82801eb ich5 / 82801er ich5r datasheet hub interface to pci bridge registers (d30:f0) 8.1.16 secsts?secondary status register (hub-pci?d30:f0) offset address: 1e ? 1fh attribute: r/wc, ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = parity error not detected. 1 = intel ? ich5 detected a parity error on the pci bus. 14 received system error (sse) ? r/wc. 0 = serr# assertion not received 1 = serr# assertion is received on pci. 13 received master abort (rma) ? r/wc. 0 = no master abort. 1 = hub interface to pci cycle is master-aborted on pci. 12 received target abort (rta) ? r/wc. 0 = no target abort. 1 = hub interface to pci cycle is target-aborted on pci. for ?completion required? cycles from the hub interface, this event should also set the signaled target abort in the primary status register in this device, and the ich5 must send the ?target abort? status back to the hub interface. 11 signaled target abort (sta) ? ro. the ich5 does not generate target aborts. 10:9 devsel# timing status (dev_sts) ? ro. 01h = medium timing. 8 master data parity error detected (mdpd) ? r/wc. 0 = conditions described below not met. 1 = the ich5 sets this bit when all of the following three conditions are met: - the parity error response enable bit in the bridge control register (bit 0, offset 3eh) is set. - usb, ac ?97 or ide is a master. - perr# asserts during a write cycle or a parity error is detected internally during a read cycle. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1 to indicate that the pci to hub interface target logic is capable of receiving fast back-to-back cycles. 6 reserved 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 309 hub interface to pci bridge registers (d30:f0) 8.1.17 membase?memory base register (hub-pci?d30:f0) offset address: 20 ? 21h attribute: r/w default value: fff0h size: 16 bits this register defines the base of the hub interface to pci non-prefetchable memory range. since the ich5 forwards all hub interface memory accesses that are not taken by integrated functions to pci, the ich5 only uses this information for determining when not to accept cycles as a target. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1-mb boundary. 8.1.18 memlim?memory limit register (hub-pci?d30:f0) offset address: 22 ? 23h attribute: r/w default value: 0000h size: 16 bits this register defines the upper limit of the hub interface to pci non-prefetchable memory range. since the ich5 forwards all hub interface memory accesses to pci, the ich5 only uses this information for determining when not to accept cycles as a target. this register must be initialized by the config software. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be aligned to a 1-mb boundary. 8.1.19 pref_mem_base?prefetchable memory base register (hub-pci?d30:f0) offset address: 24 ? 25h attribute: r/w default value: fff0h size: 16-bit bit description 15:4 memory address base ? r/w. this field defines the base of the memory range for pci. these 12 bits correspond to address bits 31:20. 3:0 reserved bit description 15:4 memory address limit ? r/w. this field defines the top of the memory range for pci. these 12 bits correspond to address bits 31:20. 3:0 reserved. bit description 15:4 prefetchable memory address base ? r/w. this field defines the base address of the prefetchable memory address range for pci. these 12 bits correspond to address bits 31:20. 3:0 reserved. 310 intel ? 82801eb ich5 / 82801er ich5r datasheet hub interface to pci bridge registers (d30:f0) 8.1.20 pref_mem_mlt?prefetchable memory limit register (hub-pci?d30:f0) offset address: 26 ? 27h attribute: r/w default value: 0000h size: 16-bit 8.1.21 iobase_hi?i/o base upper 16 bits register (hub-pci?d30:f0) offset address: 30 ? 31h attribute: ro default value: 0000h size: 16 bits 8.1.22 iolim_hi?i/o limit upper 16 bits register (hub-pci?d30:f0) offset address: 32 ? 33h attribute: ro default value: 0000h size: 16 bits 8.1.23 int_ln?interrupt line register (hub-pci?d30:f0) offset address: 3ch attribute: ro default value: 00h size: 8 bits bit description 15:4 prefetchable memory address limit ? rw. this field defines the limit address of the prefetchable memory address range for pci. these 12 bits correspond to address bits 31:20. 3:0 reserved. bit description 15:0 i/o address base upper 16 bits [31:16] ? ro. not supported; hardwired to 0. bit description 15:0 i/o address limit upper 16 bits [31:16] ? ro. not supported; hardwired to 0. bit description 7:0 interrupt line routing (int_ln) ? ro. hardwired to 00h. the bridge does not generate interrupts, and interrupts from downstream devices are routed around the bridge. intel ? 82801eb ich5 / 82801er ich5r datasheet 311 hub interface to pci bridge registers (d30:f0) 8.1.24 bridge_cnt?bridge control register (hub-pci?d30:f0) offset address: 3e ? 3fh attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:12 reserved 11 discard timer serr# enable (dtse) ? r/w. the intel ? ich5 does not treat a discarded delayed transaction on the secondary interface as an error (see bit 10 in this register). therefore, this bit has no effect on the hardware. it is implemented as read/write for software compatibility. 10 discard timer status (dts) ? ro. hardwired to 0. ich5 only performs delayed transactions on behalf of pci memory reads to prefetchable memory. 9 secondary discard timer (sdt) ? r/w. this bit sets the maximum number of pci clock cycles that the ich5 waits for an initiator on pci to repeat a delayed transaction request. the counter starts once the delayed transaction completion is at the head of the queue. if the master has not repeated the transaction at least once before the counter expires, the ich5 discards the transaction from its queue. 0 = the pci master timeout value is between 2 15 and 2 16 pci clocks 1 = the pci master timeout value is between 2 10 and 2 11 pci clocks 8 primary discard timer (pdt ) ? r/w. this bit is r/w for software compatibility only. 7 fast back to back enable ? ro. hardwired to 0. the pci logic will not generate fast back-to-back cycles on the pci bus. 6 secondary bus reset ? ro. hardwired to 0. the ich5 does not follow the pci-to-pci bridge reset scheme; software-controlled resets are implemented in the pci-lpc device. 5 master abort mode ? r/w. this bit is r/w for software compatibility and has no affect on ich5 behavior. 4 vga 16-bit decode. this bit does not have any functionality relative to address decodes because the ich5 forwards the cycles to pci, independent of the decode. writes of 1 have no impact other than to force the bit to 1. writes of 0 have no impact other than to force the bit to 0. reads to this bit will return the previously written value (or 0 if no writes since reset). 3 vga enable ? r/w. 0 = no vga device on pci. 1 = indicates that the vga device is on pci. therefore, the pci to hub interface decoder will not accept memory cycles in the range a0000h?bffffh. note that the ich5 will never take i/o cycles in the vga range from pci. 2 isa enable ? r/w. the ich5 ignores this bit. however, this bit is read/write for software compatibility. since the ich5 forwards all i/o cycles that are not in the usb, ac ?97, or ide ranges to pci, this bit would have no effect. 1 serr# enable ? r/w. 0 = disable 1 = enable. if this bit is set and bit 8 in pcicmd register (d30:f0 offset 04h) is also set, the ich5 will set the sse bit in pcists register (d30:f0, offset 06h, bit 14) and also generate an nmi (or smi# if nmi routed to smi) when the serr# signal is asserted. note: the internal serr# will be generated only if the serr_en (d30:f0:04h bit 8) bit is also set. 0 parity error response enable ? r/w. 0 = disable 1 = enable the hub interface to pci bridge for parity error detection and reporting on the pci bus. 312 intel ? 82801eb ich5 / 82801er ich5r datasheet hub interface to pci bridge registers (d30:f0) 8.1.25 hi1_cmd?hub interface 1 command control register (hub-pci?d30:f0) offset address: 40 ? 43h attribute: r/w, ro default value: 76202802h size: 32 bits bit description 31:21 reserved 20 hp unsupported (hpun) ? r/w. 1 = intel ? ich5 will not check parity on the hub interface even if enabled to do so according to the parity error response bit in d30:f0:04h bit 6. 19:16 hub interface timeslice (hi_tmsl) ? r/w. this field sets the hi arbiter time-slice value with 4 base-clock granularity. a value of 0h means that the time-slice is immediately expired and that the ich5 will allow the other master?s request to be serviced after every message. 15:14 hub interface width (hi_width) ? ro. this field is hardwired to 00b, indicating that the hub interface is 8 bits wide. 13 hub interface rate valid (hi_rate_val) ? ro. hardwired to 1. 12:10 hub interface rate (hi_rate) ? ro. encoded value representing the clock-to-transfer rate of the hi1 interface: 1:4 = 010b the value is loaded at reset by sampling the capability of the device connected to the hi1 port. the value for this field is fixed for 4x mode only. 9:4 reserved. 3:1 max data (maxd) ? ro. hardwired to 001b. this field specifies the maximum amount of data that the ich5 is allowed to burst in one packet on the hub interface. the ich5 will always perform 64- byte bursts. 0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 313 hub interface to pci bridge registers (d30:f0) 8.1.26 device_hide?secondary pci device hiding register (hub-pci?d30:f0) offset address: 44 ? 45h attribute: r/w default value: 00h size: 16 bits power well: 00h this register allows software to ?hide? pci devices (0 through 5) in terms of configuration space. specifically, when pci devices (0 ? 5) are hidden, the configuration space is not accessible because the pci idsel pin does not assert. the ich5 supports the hiding of six external devices (0 through 5), which matches the number of pci request/grant pairs, and the ability to hide the integrated lan device by masking out the configuration space decode of lan controller. writing a 1 to this bit will not restrict the configuration cycle to the pci bus. this differs from bits 0 through 5 in which the configuration cycle is restricted. hiding a pci device can be useful for debugging, bug work-arounds, and system management support. devices should only be hidden during initialization before any configuration cycles are run. this guarantees that the device is not in a semi-enable state. bit description 15:9 reserved 8 hide device 8 (hide_dev8) ? r/w. same as bit 0 of this register, except for device 8 (ad24), which is hardwired to the integrated lan device. this bit will not change the way the configuration cycle appears on pci bus 7:6 reserved 5 hide device 5 (hide_dev5) ? r/w. same as bit 0 of this register, except for device 5 (ad21). 4 hide device 4 (hide_dev4) ? r/w. same as bit 0 of this register, except for device 4 (ad20). 3 hide device 3 (hide_dev3) ? r/w. same as bit 0 of this register, except for device 3 (ad19). 2 hide device 2 (hide_dev2) ? r/w. same as bit 0 of this register, except for device 2 (ad18). 1 hide device 1 (hide_dev1 ) ? r/w. same as bit 0 of this register, except for device 1 (ad17). 0 hide device 0 (hide_dev0) ? r/w. 0 = the pci configuration cycles for this slot are not affected. 1 = intel ? ich5 hides device 0 on the pci bus. this is done by masking the idsel (keeping it low) for configuration cycles to that device. since the device will not see its idsel go active, it will not respond to pci configuration cycles and the processor will think the device is not present. ad16 is used as idsel for device 0. 314 intel ? 82801eb ich5 / 82801er ich5r datasheet hub interface to pci bridge registers (d30:f0) 8.1.27 cnf?policy configuration register (hub-pci?d30:f0) offset address: 50 ? 53h attribute: r/w default value: 00406402h size: 32 bits bit description 31:24 reserved 23:20 async reads ? r/w. ich5 memory async read request. bios should set this value to 0111b. 19 bios should set this bit if the platform uses hi11. 18 bios should set this bit if the platform uses hi11. 17:16 pci prefetch ? r/w. pci prefetch request for pci reads from main memory. bios should set this value to 11b. 15:14 reserved 13 prefetch flush enable ? r/w. 0 = prefetch flush disable 1 = causes cpu to pci logic to only deliver ?demand? data for a delayed transaction if a processor- to-pci write has occurred since the delayed transaction was initiated. (default) note: this bit must be set by system bios. 12:10 reserved 9 high priority pci enable (hp_pci_en) ? r/w. 0 = all pci req#/gnt pairs have the same arbitration priority. 1 = enables a mode where the req0#/gnt0# signal pair has a higher arbitration priority. 8 hole enable (15 mb ? 16 mb) ? r/w. 0 = disable 1 = enables the 15-mb to 16-mb hole in the dram. 7:3 reserved 2 delayed transaction discard timer ? r/w. when set to 1 this bit shortens all delayed transaction discard timers from 32 s to 4 s. note: setting this bit may improve system performance issues with certain non-optimally behaved pci devices, but may violate the pci-to-pci bridge architecture specification, revision 1.1 (section 5.3.2) 1 12-clock retry enable ? r/w. system bios must set this bit for pci compliance. 0 = the intel ? ich5 inserts as many wait-states as needed to complete the pci to memory cycle. 1 = the ich5 retries a pci to memory cycle (reads or write) if the ich5 is not able to complete the transfer in 12 pci clocks. 0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 315 hub interface to pci bridge registers (d30:f0) 8.1.28 mtt?multi-transaction timer register (hub-pci?d30:f0) offset address: 70h attribute: r/w default value: 20h size: 8 bits mtt is an 8-bit register that controls the amount of time that the ich5?s arbiter allows a pci initiator to perform multiple back-to-back transactions on the pci bus. the ich5?s mtt mechanism is used to guarantee a fair share of the primary pci bandwidth to an initiator that performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence it can not use long burst transfers). the number of clocks programmed in the mtt represents the guaranteed time slice (measured in pci clocks) allotted to the current agent, after which the arbiter will grant another agent that is requesting the bus. the mtt value must be programmed with 8-clock granularity in the same manner as mlt. for example, if the mtt is programmed to 18h, then the selected value corresponds to the time period of 24 pci clocks.the default value of mtt is 20h (32 pci clocks). note: programming the a value of 00h disables this function, which could cause starvation problems for some pci master devices. programming of the mtt to anything less than 16 clocks will not allow the grant-to-frame# latency to be 16 clocks. the mtt timer will timeout before the grant-to- frame# trigger causing a re-arbitration. 8.1.29 pci_mast_sts?pci master status register (hub-pci?d30:f0) offset address: 82h attribute: r/wc default value: 00h size: 8 bits note: software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 7:3 multi-transaction timer count value ? r/w. this field specifies the amount of time that grant will remain asserted to a master continuously asserting its request for multiple transfers. this field specifies the count in an 8-clock (pci clock) granularity. 2:0 reserved bit description 7 internal pci master request status (int_mreq_sts) ? r/wc. 0 = dma controller or lpc has not requested use of the pci bus. 1 = the intel ? ich5?s internal dma controller or lpc has requested use of the pci bus. 6 internal lan master request status (lan_mreq_sts) ? r/wc. 0 = lan controller has not requested use of the pci bus. 1 = the ich5?s internal lan controller has requested use of the pci bus. 5:0 pci master request status (pci_mreq_sts) ? r/wc. allows software to see if a particular bus master has requested use of the pci bus. for example, bit 0 will be set if the ich5 has detected req0# asserted and bit 5 will be set if ich5 detected req5# asserted. 0 = associated pci master has not requested use of the pci bus. 1 = the associated pci master has requested use of the pci bus. 316 intel ? 82801eb ich5 / 82801er ich5r datasheet hub interface to pci bridge registers (d30:f0) 8.1.30 err_cmd?error command register (hub-pci?d30:f0) offset address: 90h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core this register configures the ich5?s device 30 responses to various system errors. the actual assertion of the internal serr# (routed to cause nmi# or smi#) is enabled via the pci command register. 8.1.31 err_sts?error status register (hub-pci?d30:f0) offset address: 92h attribute: r/wc default value: 00h size: 8-bit lockable: no power well: core this register records the cause of system errors in device 30. the actual assertion of serr# is enabled via the pci command register. note: software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 7:3 reserved 2 serr# enable on receiving target abort (serr_rta_en) ? r/w. 0 = disable 1 = enable. when serr_en is set, the intel ? ich5 will report serr# when serr_rta is set. 1:0 reserved bit description 7:3 reserved 2 serr# due to received target abort (serr_rta) ? r/wc. 0 = target abort not received. 1 = intel ? ich5 received a target abort. if serr_en, the ich5 will also generate an serr# when serr_rta is set. 1 reserved 0 pci parity inversion state (par_inv) ? r/wc. 0 = no parity errors on pci. 1 = parity errors may have occurred on pci. this bit can be checked as part of the nmi# service routine. intel ? 82801eb ich5 / 82801er ich5r datasheet 317 lpc interface bridge registers (d31:f0) lpc interface bridge registers (d31:f0) 9 the lpc bridge function of the ich5 resides in pci device 31:function 0. this function contains many other functional units (e.g., dma and interrupt controllers, timers, power management, system management, gpio, rtc, and lpc configuration registers). registers and functions associated with other functional units (ehci, uhci, ide, etc.) are described in their respective sections. 9.1 pci configuration registers (lpc i/f?d31:f0) note: address locations that are not shown in table 141 should be treated as reserved (see section 6.2 for details). . table 141. lpc interface pci register address map (lpc i/f?d31:f0) (sheet 1 of 2) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 24d0h ro 04?05h pcicmd pci command 000fh r/w, ro 06?07h pcists pci status 0280h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 01h ro 0bh bcc base class code 06h ro 0eh headtyp header type 80h ro 40?43h pmbase acpi base address 00000001h r/w, ro 44h acpi_cntl acpi control 00h r/w 4e?4fh bios_cntl bios control 0000h r/w 54h tco_cntl tco control 00h r/w 58?5bh gpio_base gpio base address 00000001h r/w, ro 5ch gpio_cntl gpio control 00h r/w 60?63h pirq[ n ]_rout pirq[a?d] routing control 80h r/w 64h sirq_cntl serial irq control 10h r/w 68?6bh pirq[ n ]_rout pirq[e?h] routing control 80h r/w 88h d31_err_cfg device 31 error configuration 00h r/w 8ah d31_err_sts device 31 error status 00h r/wc 90?91h pci_dma_cfg pci dma configuration 0000h r/w 318 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) note: refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. 9.1.1 vid?vendor identification register (lpc i/f?d31:f0) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16-bit lockable: no power well: core 9.1.2 did?device identification register (lpc i/f?d31:f0) offset address: 02 ? 03h attribute: ro default value: 24d0h size: 16-bit lockable: no power well: core a0?cfh power management (see section 9.8.1 ) d0?d3h gen_cntl general control 00000004h r/w, r/wo d4h gen_sta general status 0xh r/w (special), ro d5h back_cntl backed up control see register description r/w, ro d8h rtc_conf real time clock configuration 00h r/w e0h com_dec lpc i/f com port decode ranges 00h r/w e1h lpcfdd_dec lpc i/f fdd and lpt decode ranges 00h r/w e3h fb_dec_en1 flash bios decode enable 1 ffh r/w e4?e5h gen1_dec lpc i/f generic 1 decode range 1 0000h r/w e6?e7h lpc_en lpc i/f enables 00h r/w e8?ebh fb_sel1 flash bios select 1 00112233h r/w, ro ec?edh gen2_dec lpc i/f generic 2 decode range 2 0000h r/w ee?efh fb_sel2 flash bios select 2 4567h r/w f0h fb_dec_en2 flash bios decode enable 2 0fh r/w f2h func_dis function disable 00h r/w table 141. lpc interface pci register address map (lpc i/f?d31:f0) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich5 lpc bridge. intel ? 82801eb ich5 / 82801er ich5r datasheet 319 lpc interface bridge registers (d31:f0) 9.1.3 pcicmd?pci command register (lpc i/f?d31:f0) offset address: 04 ? 05h attribute: r/w, ro default value: 000fh size: 16-bit lockable: no power well: core bit description 15:10 reserved 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. 0 = disable 1 = enable. allow serr# to be generated. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? r/w. 0 = no action is taken when detecting a parity error. 1 = the intel ? ich5 will take normal action when a parity error is detected. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 1. 2 bus master enable (bme) ? ro. hardwired to 1 to indicate that bus mastering cannot be disabled for function 0 (dma/isa master). 1 memory space enable (mse) ? ro. hardwired to 1 to indicate that memory space cannot be disabled for function 0 (lpc i/f). 0 i/o space enable (iose) ? ro. hardwired to 1 to indicate that the i/o space cannot be disabled for function 0 (lpc i/f). 320 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.4 pcists?pci status register (lpc i/f?d31:f0) offset address: 06 ? 07h attribute: ro, r/wc default value: 0280h size: 16-bit lockable: no power well: core note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = perr# not active 1 = perr# signal goes active. set even if the per bit is 0. 14 signaled system error (sse) ? r/wc. 0 = serr# on function 0 not generated with serr_en set. 1 = set by the intel ? ich5 if the serr_en bit is set and the ich5 generates an serr# on function 0. the err_sts register can be read to determine the cause of the serr#. the serr# can be routed to cause smi#, nmi, or interrupt. 13 master abort status (rma) ? r/wc. 0 = master abort on pci not generated due to lpc i/f master or dma cycle. 1 = ich5 generated a master abort on pci due to lpc i/f master or dma cycles. 12 received target abort (rta) ? r/wc. 0 = target abort not received during lpc i/f master or dma cycles to pci. 1 = ich5 received a target abort during lpc i/f master or dma cycles to pci. 11 signaled target abort (sta) ? r/wc. 0 = target abort not generated on pci cycles claimed by ich5 for conditions listed below. 1 = ich5 generated a target abort condition on pci cycles claimed by the ich5 for ich5 internal registers or for going to lpc i/f. 10:9 devsel# timing status (dev_sts) ? ro. 01 = medium timing. 8 data parity error detected (dped) ? r/wc. 0 = all conditions listed below not met. 1 = set when all three of the following conditions are met: - the ich5 is the initiator of the cycle, - the ich5 asserted perr# (for reads) or observed perr# (for writes), and - the per bit is set. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1 to indicate that the ich5, as a target, can accept fast back-to-back transactions. 6 user definable features (udf). hardwired to 0. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4:0 reserved. intel ? 82801eb ich5 / 82801er ich5r datasheet 321 lpc interface bridge registers (d31:f0) 9.1.5 rid?revision identification register (lpc i/f?d31:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 9.1.6 pi?programming interface register (lpc i/f?d31:f0) offset address: 09h attribute: ro default value: 00h size: 8 bits 9.1.7 scc?sub class code register (lpc i/f?d31:f0) offset address: 0ah attribute: ro default value: 01h size: 8 bits 9.1.8 bcc?base class code register (lpc i/f?d31:f0) offset address: 0bh attribute: ro default value: 06h size: 8 bits bit description 7:0 revision id ? ro. 8-bit value that indicates the revision number for the lpc bridge. for the a-0 stepping, this value is 00h. note: refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. bit description 7:0 programming interface ? ro. bit description 7:0 sub class code ? ro. 8-bit value that indicates the category of bridge for the lpc pci bridge. bit description 7:0 base class code ? ro. 8-bit value that indicates the type of device for the lpc bridge. 06h = bridge device. 322 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.9 headtyp?header type register (lpc i/f?d31:f0) offset address: 0eh attribute: ro default value: 80h size: 8 bits 9.1.10 pmbase?acpi base address register (lpc i/f?d31:f0) offset address: 40 ? 43h attribute: r/w, ro default value: 00000001h size: 32 bit lockable: no usage: acpi, legacy power well: core sets base address for acpi i/o registers, gpio registers and tco i/o registers. these registers can be mapped anywhere in the 64-k i/o space on 128-byte boundaries. bit description 7 multi-function device ? ro. this bit is 1 to indicate a multi-function device. 6:0 header type ? ro. this 7-bit field identifies the header layout of the configuration space. bit description 31:16 reserved 15:7 base address ? r/w. this field provides 128 bytes of i/o space for acpi, gpio, and tco logic. this is placed on a 128-byte boundary. 6:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate i/o space. intel ? 82801eb ich5 / 82801er ich5r datasheet 323 lpc interface bridge registers (d31:f0) 9.1.11 acpi_cntl?acpi control register (lpc i/f ? d31:f0) offset address: 44h attribute: r/w default value: 00h size: 8 bit lockable: no usage: acpi, legacy power well: core bit description 7:5 reserved 4 acpi enable (acpi_en) ? r/w. 0 = disable 1 = decode of the i/o range pointed to by the acpi base register is enabled, and the acpi power management function is enabled. note that the apm power management ranges (b2/b3h) are always enabled and are not affected by this bit. 3 reserved 2:0 sci irq select (sci_irq_sel) ? r/w. specifies on which irq the sci will internally appear. if not using the apic, the sci must be routed to irq9?11, and that interrupt is not sharable with the serirq stream, but is shareable with other pci interrupts. if using the apic, the sci can also be mapped to irq20?23, and can be shared with other interrupts. bits sci map 000 irq9 001 irq10 010 irq11 011 reserved 100 irq20 (only available if apic enabled) 101 irq21 (only available if apic enabled) 110 irq22 (only available if apic enabled) 111 irq23 (only available if apic enabled) note: when the tco interrupt is mapped to apic interrupts 9, 10 or 11, the signal is in fact active high. when the tco interrupt is mapped to irq 20, 21, 22, or 23, the signal is active low and can be shared with pci interrupts that may be mapped to those same signals (irqs). 324 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.12 bios_cntl?bios control register (lpc i/f?d31:f0) offset address: 4e ? 4fh attribute: r/w default value: 0000h size: 16 bit lockable: no power well: core 9.1.13 tco_cntl ? tco control register (lpc i/f ? d31:f0) offset address: 54h attribute: r/w default value: 00h size: 8 bit lockable: no power well: core bit description 15:2 reserved 1 bios lock enable (ble) ? r/w. 0 = setting the bioswe will not cause sums. once set, this bit can only be cleared by a pcirst#. 1 = enables setting the bioswe bit to cause sums. 0 bios write enable (bioswe) ? r/w. 0 = only read cycles result in flash bios i/f cycles. 1 = access to the bios space is enabled for both read and write cycles. when this bit is written from a 0 to a 1 and bios lock enable (ble) is also set, an smi# is generated. this ensures that only smi code can update bios. bit description 7:4 reserved 3 tco interrupt enable (tco_int_en) ? r/w. this bit enables/disables the tco interrupt. 0 = disables tco interrupt. 1 = enables tco interrupt, as selected by the tco_int_sel field. 2:0 tco interrupt select (tco_int_sel) ? r/w. this field specifies on which irq the tco will internally appear. if not using the apic, the tco interrupt must be routed to irq9?11, and that interrupt is not sharable with the serirq stream, but is shareable with other pci interrupts. if using the apic, the tco interrupt can also be mapped to irq20?23, and can be shared with other interrupt. note that if the tcosci_en bit is set (bit 6 of the gpeo_en register), then the tco interrupt will be sent to the same interrupt as the sci, and the tco_int_sel bits will have no meaning. when the tco interrupt is mapped to apic interrupts 9, 10 or 11, the signal is in fact active high. when the tco interrupt is mapped to irq 20, 21, 22, or 23, the signal is active low and can be shared with pci interrupts that may be mapped to those same signals (irqs). bits sci map 000 irq9 001 irq10 010 irq11 011 reserved 100 irq20 (only available if apic enabled) 101 irq21 (only available if apic enabled) 110 irq22 (only available if apic enabled) 111 irq23 (only available if apic enabled) intel ? 82801eb ich5 / 82801er ich5r datasheet 325 lpc interface bridge registers (d31:f0) 9.1.14 gpio_base?gpio base address register (lpc i/f?d31:f0) offset address: 58h ? 5bh attribute: r/w, ro default value: 00000001h size: 32 bit lockable: no power well: core 9.1.15 gpio_cntl?gpio control register (lpc i/f?d31:f0) offset address: 5ch attribute: r/w default value: 00h size: 8 bit lockable: no power well: core bit description 31:16 reserved 15:6 base address ? r/w. this field provides the 64 bytes of i/o space for gpio. 5:1 reserved 0 resource type indicator ? ro. hardwired to 1 to indicate i/o space. bit description 7:5 reserved 4 gpio enable (gpio_en) ? r/w. this bit enables/disables decode of the i/o range pointed to by the gpio base register and enables/disables the gpio function. 0 = disable 1 = enable 3:0 reserved 326 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.16 pirq[n]_rout?pirq[a,b,c,d] routing control register (lpc i/f?d31:f0) offset address: pirqa ? 60h, pirqb ? 61h, attribute: r/w pirqc ? 62h, pirqd ? 63h default value: 80h size: 8 bit lockable: no power well: core bit description 7 interrupt routing enable (irqen) ? r/w. 0 = the corresponding pirq is routed to one of the isa-compatible interrupts specified in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 6:4 reserved 3:0 irq routing ? r/w. (isa compatible.) 0000 = reserved 1000 = reserved 0001 = reserved 1001 = irq9 0010 = reserved 1010 = irq10 0011 = irq3 1011 = irq11 0100 = irq4 1100 = irq12 0101 = irq5 1101 = reserved 0110 = irq6 1110 = irq14 0111 = irq7 1111 = irq15 intel ? 82801eb ich5 / 82801er ich5r datasheet 327 lpc interface bridge registers (d31:f0) 9.1.17 sirq_cntl?serial irq control register (lpc i/f?d31:f0) offset address: 64h attribute: r/w default value: 10h size: 8 bit lockable: no power well: core bit description 7 serial irq enable (sirqen) ? r/w. 0 = the buffer is input only and internally serirq will be a 1. 1 = serial irqs will be recognized. the serirq pin will be configured as serirq. 6 serial irq mode select (sirqmd) ? r/w. 0 = the serial irq machine will be in quiet mode. 1 = the serial irq machine will be in continuous mode. note: for systems using quiet mode, this bit should be set to 1 (continuous mode) for at least one frame after coming out of reset before switching back to quiet mode. failure to do so will result in the intel ? ich5 not recognizing serirq interrupts. 5:2 serial irq frame size (sirqsz) ? r/w. fixed field that indicates the size of the serirq frame. in the ich5, this field needs to be programmed to 21 frames (0100). this is an offset from a base of 17 which is the smallest data frame size. 1:0 start frame pulse width (sfpw) ? r/w. this is the number of pci clocks that the serirq pin will be driven low by the serial irq machine to signal a start frame. in continuous mode, the ich5 will drive the start frame for the number of clocks specified. in quiet mode, the ich5 will drive the start frame for the number of clocks specified minus 1, as the first clock was driven by the peripheral. 00 = 4 clocks 01 = 6 clocks 10 = 8 clocks 11 = reserved 328 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.18 pirq[n]_rout?pirq[e,f,g,h] routing control register (lpc i/f?d31:f0) offset address: pirqe ? 68h, pirqf ? 69h, attribute: r/w pirqg ? 6ah, pirqh ? 6bh default value: 80h size: 8 bit lockable: no power well: core 9.1.19 d31_err_cfg?device 31 error configuration register (lpc i/f?d31:f0) offset address: 88h attribute: r/w default value: 00h size: 8 bit lockable: no power well: core this register configures the ich5?s device 31 responses to various system errors. the actual assertion of serr# is enabled via the pci command register. . bit description 7 interrupt routing enable (irqen) ? r/w. 0 = the corresponding pirq is routed to one of the isa-compatible interrupts specified in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 6:4 reserved 3:0 irq routing ? r/w. (isa compatible.) 0000 = reserved 1000 = reserved 0001 = reserved 1001 = irq9 0010 = reserved 1010 = irq10 0011 = irq3 1011 = irq11 0100 = irq4 1100 = irq12 0101 = irq5 1101 = reserved 0110 = irq6 1110 = irq14 0111 = irq7 1111 = irq15 bit description 7:3 reserved 2 serr# on received target abort enable (serr_rta_en) ? r/w. 0 = disable. no serr# assertion on received target abort. 1 = enable. intel ? ich5 generates serr# when serr_rta is set if serr_en is set. 1 serr# on delayed transaction timeout enable (serr_dtt_en) ? r/w. 0 = disable. no serr# assertion on delayed transaction timeout. 1 = enable. ich5 generates serr# when serr_dtt bit is set if serr_en is set. 0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 329 lpc interface bridge registers (d31:f0) 9.1.20 d31_err_sts?device 31 error status register (lpc i/f?d31:f0) offset address: 8ah attribute: r/wc default value: 00h size: 8 bit lockable: no power well: core this register configures the ich5?s device 31 responses to various system errors. the actual assertion of serr# is enabled via the pci command register. note: software clears set bits in this register by writing a 1 to the bit position. 9.1.21 pci_dma_cfg?pci dma configuration register (lpc i/f?d31:f0) offset address: 90h ? 91h attribute: r/w default value: 0000h size: 16 bit lockable: no power well: core bit description 7:3 reserved 2 serr# due to received target abort (serr_rta) ? r/wc. 0 = target abort not received. 1 = the intel ? ich5 sets this bit when it receives a target abort. if serr_en, the ich5 also generates a serr# when serr_rta is set. 1 serr# due to delayed transaction timeout (serr_dtt) ? r/wc. 0 = pci master does not violate return for data time described below. 1 = when a pci master does not return for the data within 1 ms of the cycle?s completion, the ich5 clears the delayed transaction and sets this bit. if both serr_dtt_en and serr_en are set, then ich5 also generates an serr# when serr_dtt is set. 0 reserved bit description 15:14 channel 7 select ? r/w. 00 = reserved 01 = pc/pci dma 10 = reserved 11 = lpc i/f dma 13:12 channel 6 select ? r/w. same bit decode as for channel 7 11:10 channel 5 select ? r/w. same bit decode as for channel 7 9:8 reserved 7:6 channel 3 select ? r/w. same bit decode as for channel 7 5:4 channel 2 select ? r/w. same bit decode as for channel 7 3:2 channel 1 select ? r/w. same bit decode as for channel 7 1:0 channel 0 select ? r/w. same bit decode as for channel 7 330 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.22 gen_cntl ? general control register (lpc i/f ? d31:f0) offset address: d0h ? d3h attribute: r/w, r/wo default value: 00000004h size: 32 bit lockable: no power well: core bit description 31:26 reserved 25 req5#/gnt5# pc/pci protocol select (pcpcib_sel) ? r/w. 0 = the req5#/gnt5# pins function as a standard pci req/gnt signal pair. 1 = pci req5#/gnt5# signal pair will use the pc/pci protocol as reqb#/gntb. the corresponding bits in the gpio_use_sel register must also be set to a 0. if the corresponding bits in the gpio_use_sel register are set to a 1, the signals will be used as a gpi and gpo. 24 hide isa bridge (hide_isa) ? r/w. 0 = the intel ? ich5 will not prevent ad22 from asserting during config cycles to the pci-to-isa bridge. 1 = software sets this bit to 1 to disable configuration cycles from being claimed by a pci-to-isa bridge. this will prevent the os pci pnp from getting confused by seeing two isa bridges. it is required for the ich5 pci address line ad22 to connect to the pci-to-isa bridge?s idsel input. when this bit is set, the ich5 will not assert ad22 during config cycles to the pci-to-isa bridge. 23:22 reserved 21 reserved 20 reserved 19:18 scratchpad ? r/w. ich5 does not perform any action on these bits. 17 hpet address enable (hpet_addr_en ) ? r/w. 0 = disable 1 = enable. ich5 decodes the high-precision event timers memory address range selected by bits 16:15 below. 16:15 hpet address select (hpet_addr_sel) ? r/w. this 2-bit field selects 1 of 4 possible memory address ranges for the high-precision event timers functionality. the encodings are: bits [16:15]memory address range 00 fed0_0000h ? fed0_03ffh 01 fed0_1000h ? fed0_13ffh 10 fed0_2000h ? fed0_23ffh 11 fed0_3000h ? fed0_33ffh 14 reserved 13 coprocessor error enable (copr_err_en) ? r/w. 0 = ferr# will not generate irq13 nor ignne#. 1 = when ferr# is low, ich5 generates irq13 internally and holds it until an i/o write to port f0h. it will also drive ignne# active. 12 keyboard irq1 latch enable (irq1len) ? r/w. 0 = irq1 will bypass the latch. 1 = the active edge of irq1 will be latched and held until a port 60h read. 11 mouse irq12 latch enable (irq12len) ? r/w. 0 = irq12 will bypass the latch. 1 = the active edge of irq12 will be latched and held until a port 60h read. 10 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 331 lpc interface bridge registers (d31:f0) 9 top_swap lock-down ? r/wo. this bit can only be written from 0 to 1 once. 0 = a hardware reset is required to clear this bit. 1 = prevents the top-swap bit from being changed. 8 apic enable (apic_en) ? r/w. 0 = disables internal i/o (x) apic. 1 = enables the internal i/o (x) apic and its address decode. the following behavioral rules apply for bits 8 and 7 in this register: ? rule 1: if bit 8 is 0, then the ich5 will not decode any of the registers associated with the i/o apic or i/o (x) apic. the state of bit 7 is ?don?t care? in this case. ? rule 2: if bit 8 is 1 and bit 7 is 0, then the ich5 will decode the memory space associated with the i/o apic, but not the extra registers associated i/o (x) apic. ? rule 3: if bit 8 is 1 and bit 7 is 1, then the ich5 will decode the memory space associated with both the i/o apic and the i/o (x) apic. this also enables pci masters to write directly to the register to cause interrupts (pci message interrupt). note: there is no separate way to disable pci message interrupts if the i/o (x) apic is enabled. this is not considered necessary. 7 system bus message disable ? r/w. 0 = has no effect. (default) 1 = disables the ich5 ioapic controller from generating anymore system bus interrupt messages. note: it is possible for the ich5 to deliver up to 1 system bus interrupt message from the time this configuration bit is set to 1. 6 alternate access mode enable (altacc_en) ? r/w. 0 = disable (default). alt access mode allows reads to otherwise unreadable registers and writes otherwise unwritable registers. 1 = enable 5:4 reserved 3 reserved? ro. 2 dma collection buffer enable (dcb_en) ? r/w. 0 = dcb disabled. 1 = enables dma collection buffer (dcb) for lpc i/f and pc/pci dma. 1 delayed transaction enable (dte) ? r/w. 0 = disable 1 = enable. ich5 enables delayed transactions for internal register, flash bios and lpc i/f accesses. 0 positive decode enable (pos_dec_en) ? r/w. 0 = disable. the ich5 performs subtractive decode on the pci bus and forwards the cycles to lpc i/f if not to an internal register or other known target on lpc i/f. accesses to internal registers and to known lpc i/f devices are still positively decoded. 1 = enables ich5 to only perform positive decode on the pci bus. bit description 332 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.23 gen_sta?general status register (lpc i/f?d31:f0) offset address: d4h attribute: r/w (special), ro default value: 0xh size: 8 bit lockable: no power well: core bit description 7:3 reserved 2 safe mode (safe_mode) ? ro. 0 = intel ? ich5 sampled ac_sdout low on the rising edge of pwrok. 1 = ich5 sampled ac_sdout high on the rising edge of pwrok. ich5 will force freq_strap[3:0] bits to all 1s (safe mode multiplier). 1 no reboot (no_reboot) ? r/w (special). 0 = normal tco timer reboot functionality (reboot after 2nd tco timeout). this bit cannot be set to 0 by software if the strap is set to no reboot. 1 = ich5 disables the tco timer system reboot feature. this bit is set either by hardware when spkr is sampled high on the rising edge of pwrok, or by software writing a 1 to the bit. 0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 333 lpc interface bridge registers (d31:f0) 9.1.24 back_cntl?backed up control register (lpc i/f?d31:f0) offset address: d5h attribute: r/w, ro default value: size: 8 bit 0fh (upon rtcrst# assertion low) 2fh (if top swap strap is active) lockable: no power well: rtc, suspend (see bit details) bit description 7 0 = reserved. hardwired to 0 forcing the reset state of the ide pins to always be driven/tri-state (depending on the pin). 6 0 = reserved. hardwired to 0 forcing the reset state of the ide pins to always be driven/tri-state (depending on the pin). 5 top-block swap mode (top_swap) ? r/w. if intel ? ich5 is strapped for top-swap (gnta# is low at rising edge of pwrok), then this bit cannot be cleared by software. the strap jumper should be removed and the system rebooted. this bit can not be overwritten after the top-swap lock-down bit is set. 0 = ich5 will not invert a16. this bit is cleared by rtcrst# assertion, but not by any other type of reset. 1 = ich5 will invert a16 for cycles targeting flash bios space (does not affect access to flash bios feature space). 4 enables cpu bist (cpu_bist_en) ? r/w. 0 = disable 1 = the init# signal will be driven active when cpurst# is active. init# will go inactive with the same timings as the other processor interface signals (hold time after cpurst# inactive). note that cpurst# is generated by the memory controller hub, but the ich5 has a hub interface special cycle that allows the ich5 to control the assertion/deassertion of cpurst#. note: this bit is in the resume well and is reset by rsmrst#, but not by pcirst# nor cf9h writes. 3:0 cpu frequency strap (freq_strap[3:0]) ? r/w. these bits determine the internal frequency multiplier of the processor. these bits can be reset to 1111 based on an external pin strap or via the rtcrst# input signal. software must program this field based on the processor?s specified frequency. note that this field is only writable when the safe_mode bit is cleared to 0, and safe_mode is only cleared by pwrok rising edge. these bits are in the rtc well. 334 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.25 rtc_conf?real time clock configuration register (lpc i/f?d31:f0) offset address: d8h attribute: r/w, r/wo default value: 00h size: 8 bit lockable: yes power well: core bit description 7:5 reserved 4 upper 128-byte lock (u128lock) ? r/wo. 0 = access to these bytes in the upper cmos ram range have not been locked. 1 = locks reads and writes to bytes 38h?3fh in the upper 128-byte bank of the rtc cmos ram. write cycles to this range will have no effect and read cycles will not return any particular guaranteed value. this is a write once register that can only be reset by a hardware reset. 3 lower 128-byte lock (l128lock) ? r/wo. 0 = access to these bytes in the lower cmos ram range have not been locked. 1 = locks reads and writes to bytes 38h?3fh in the lower 128-byte bank of the rtc cmos ram. write cycles to this range will have no effect and read cycles will not return any particular guaranteed value. this is a write once register that can only be reset by a hardware reset. 2 upper 128-byte enable (u128e) ? r/w. 0 = disable 1 = enables access to the upper 128-byte bank of rtc cmos ram. 1:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 335 lpc interface bridge registers (d31:f0) 9.1.26 com_dec?lpc i/f communication port decode ranges register (lpc i/f?d31:f0) offset address: e0h attribute: r/w default value: 00h size: 8 bit lockable: no power well: core 9.1.27 lpcfdd_dec?lpc i/f fdd and lpt decode ranges register (lpc i/f?d31:f0) offset address: e1h attribute: r/w default value: 00h size: 8 bit lockable: no power well: core bit description 7 reserved 6:4 comb decode range ? r/w. this field determines which range to decode for the comb port. 000 = 3f8h ? 3ffh (com1) 001 = 2f8h ? 2ffh (com2) 010 = 220h ? 227h 011 = 228h ? 22fh 100 = 238h ? 23fh 101 = 2e8h ? 2efh (com4) 110 = 338h ? 33fh 111 = 3e8h ? 3efh (com3) 3 reserved 2:0 coma decode range ? r/w. this field determines which range to decode for the coma port. 000 = 3f8h ? 3ffh (com1) 001 = 2f8h ? 2ffh (com2) 010 = 220h ? 227h 011 = 228h ? 22fh 100 = 238h ? 23fh 101 = 2e8h ? 2efh (com4) 110 = 338h ? 33fh 111 = 3e8h ? 3efh (com3) bit description 7:5 reserved 4 fdd decode range ? r/w. determines which range to decode for the fdd port 0 = 3f0h ? 3f5h, 3f7h (primary) 1 = 370h ? 2ffh (secondary) 3:2 reserved 1:0 lpt decode range ? r/w. this field determines which range to decode for the lptport. 00 = 378h ? 37fh and 778h ? 77fh 01 = 278h ? 27fh (port 279h is read only) and 678h ? 67fh 10 = 3bch ?3beh and 7bch ? 7beh 11 = reserved 336 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.28 fb_dec_en1?flash bios decode enable 1 register (lpc i/f?d31:f0) offset address: e3h attribute: r/w default value: ffh size: 8 bits this register determines which memory ranges will be decoded on the pci bus and forwarded to the flash bios. the ich5 will subtractively decode cycles on pci unless pos_dec_en is set to 1. bit description 7 fb_f8_en ? r/w. this bit enables decoding two 512-kb flash bios memory ranges, and one 128-kb memory range. 0 = disable 1 = enable the following ranges for the flash bios fff80000h ? ffffffffh ffb80000h ? ffbfffffh 000e0000h ? 000fffffh 6 fb_f0_en ? r/w. this bit enables decoding two 512-kb flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios: fff00000h ? fff7ffffh ffb00000h ? ffb7ffffh 5 fb_e8_en ? r/w. this bit enables decoding two 512-kb flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios: ffe80000h ? ffeffffh ffa80000h ? ffafffffh 4 fb_e0_en ? r/w. this bit enables decoding two 512-kb flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios: ffe00000h ? ffe7ffffh ffa00000h ? ffa7ffffh 3 fb_d8_en ? r/w. this bit enables decoding two 512-kb flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios ffd80000h ? ffdfffffh ff980000h ? ff9fffffh 2 fb_d0_en ? r/w. this bit enables decoding two 512-kb flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios ffd00000h ? ffd7ffffh ff900000h ? ff97ffffh 1 fb_c8_en ? r/w. this bit enables decoding two 512-kb flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios ffc80000h ? ffcfffffh ff880000h ? ff8fffffh 0 fb_c0_en ? r/w. this bit enables decoding two 512-kb flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios ffc00000h ? ffc7ffffh ff800000h ? ff87ffffh intel ? 82801eb ich5 / 82801er ich5r datasheet 337 lpc interface bridge registers (d31:f0) 9.1.29 gen1_dec?lpc i/f generic decode range 1 register (lpc i/f?d31:f0) offset address: e4h ? e5h attribute: r/w default value: 0000h size: 16 bit lockable: yes power well: core 9.1.30 lpc_en?lpc i/f enables register (lpc i/f?d31:f0) offset address: e6h ? e7h attribute: r/w default value: 00h size: 16 bit lockable: yes power well: core bit description 15:7 generic i/o decode range 1 base address (gen1_base) ? r/w. this address is aligned on a 128-byte boundary, and must have address lines 31:16 as 0. note that this generic decode is for i/o addresses only, not memory addresses. the size of this range is 128 bytes. 6:1 reserved 0 generic decode range 1 enable (gen1_en) ? r/w. 0 = disable 1 = enable the gen1 i/o range to be forwarded to the lpc i/f bit description 15:14 reserved 13 cnf2_lpc_en ? r/w. 0 = disable 1 = enables the decoding of the i/o locations 4eh and 4fh to the lpc interface. this range is used for a microcontroller. 12 cnf1_lpc_en ? r/w. 0 = disable 1 = enables the decoding of the i/o locations 2eh and 2fh to the lpc interface. this range is used for super i/o devices. 11 mc_lpc_en ? r/w. 0 = disable 1 = enables the decoding of the i/o locations 62h and 66h to the lpc interface. this range is used for a microcontroller. 10 kbc_lpc_en ? r/w. 0 = disable 1 = enables the decoding of the i/o locations 60h and 64h to the lpc interface. this range is used for a microcontroller. 9 gameh_lpc_en ? r/w. 0 = disable 1 = enables the decoding of the i/o locations 208h to 20fh to the lpc interface. this range is used for a gameport. 8 gamel_lpc_en ? r/w. 0 = disable 1 = enables the decoding of the i/o locations 200h to 207h to the lpc interface. this range is used for a gameport. 338 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 7:4 reserved 3 fdd_lpc_en ? r/w. 0 = disable 1 = enables the decoding of the fdd range to the lpc interface. this range is selected in the lpc_fdd/lpt decode range register. 2 lpt_lpc_en ? r/w. 0 = disable 1 = enables the decoding of the lptrange to the lpc interface. this range is selected in the lpc_fdd/lpt decode range register. 1 comb_lpc_en ? r/w. 0 = disable 1 = enables the decoding of the comb range to the lpc interface. this range is selected in the lpc_com decode range register. 0 coma_lpc_en ? r/w. 0 = disable 1 = enables the decoding of the coma range to the lpc interface. this range is selected in the lpc_com decode range register. bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 339 lpc interface bridge registers (d31:f0) 9.1.31 fb_sel1?flash bios select 1 register (lpc i/f?d31:f0) offset address: e8h attribute: r/w, ro default value: 00112233h size: 32 bits bit description 31:28 fb_f8_idsel ? ro. idsel for two, 512-kb flash bios memory ranges and one 128-kb memory range. this field is fixed at 0000. the idsel programmed in this field addresses the following memory ranges: fff8 0000h ? ffff ffffh ffb8 0000h ? ffbf ffffh 000e 0000h ? 000f ffffh 27:24 fb_f0_idsel ? r/w. idsel for two, 512-kb flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: fff0 0000h ? fff7 ffffh ffb0 0000h ? ffb7 ffffh 23:20 fb_e8_idsel ? r/w. idsel for two, 512-kb flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: ffe8 0000h ? ffef ffffh ffa8 0000h ? ffaf ffffh 19:16 fb_e0_idsel ? r/w. idsel for two, 512-kb flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: ffe0 0000h ? ffe7 ffffh ffa0 0000h ? ffa7 ffffh 15:12 fb_d8_idsel ? r/w. idsel for two, 512-kb flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: ffd8 0000h ? ffdf ffffh ff98 0000h ? ff9f ffffh 11:8 fb_d0_idsel ? r/w. idsel for two, 512-kb flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: ffd0 0000h ? ffd7 ffffh ff90 0000h ? ff97 ffffh 7:4 fb_c8_idsel ? r/w. idsel for two, 512-kb flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: ffc8 0000h ? ffcf ffffh ff88 0000h ? ff8f ffffh 3:0 fb_c0_idsel ? r/w. idsel for two, 512-kb flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: ffc0 0000h ? ffc7 ffffh ff80 0000h ? ff87 ffffh 340 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.32 gen2_dec?lpc i/f generic decode range 2 register (lpc i/f?d31:f0) offset address: ech ? edh attribute: r/w default value: 0000h size: 16 bit lockable: yes power well: core 9.1.33 fb_sel2?flash bios select 2 register (lpc i/f?d31:f0) offset address: eeh ? efh attribute: r/w default value: 4567h size: 32 bits bit description 15:4 generic i/o decode range 2 base address (gen2_base) ? r/w. this address is aligned on a 64-byte boundary, and must have address lines 31:16 as 0. note that this generic decode is for i/o addresses only, not memory addresses. the size of this range is 16 bytes. 3:1 reserved. read as 0 0 generic i/o decode range 2 enable (gen2_en) ? r/w. 0 = disable 1 = accesses to the gen2 i/o range will be forwarded to the lpc i/f bit description 15:12 fb_70_idsel ? r/w. idsel for two, 1-m flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: ff70 0000h ? ff7f ffffh ff30 0000h ? ff3f ffffh 11:8 fb_60_idsel ? r/w. idsel for two, 1-m flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: ff60 0000h ? ff6f ffffh ff20 0000h ? ff2f ffffh 7:4 fb_50_idsel ? r/w. idsel for two, 1-m flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: ff50 0000h ? ff5f ffffh ff10 0000h ? ff1f ffffh 3:0 fb_40_idsel ? r/w. idsel for two, 1-m flash bios memory ranges. the idsel programmed in this field addresses the following memory ranges: ff40 0000h ? ff4f ffffh ff00 0000h ? ff0f ffffh intel ? 82801eb ich5 / 82801er ich5r datasheet 341 lpc interface bridge registers (d31:f0) 9.1.34 fb_dec_en2?flash bios decode enable 2 register (lpc i/f?d31:f0) offset address: f0h attribute: r/w default value: 0fh size: 8 bits this register determines which memory ranges will be decoded on the pci bus and forwarded to the flash bios. the ich5 will subtractively decode cycles on pci unless pos_dec_en is set to 1. bit description 7:4 reserved 3 fb_70_en ? r/w. enables decoding two, 1-m flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios ff70 0000h ? ff7f ffffh ff30 0000h ? ff3f ffffh 2 fb_60_en ? r/w. enables decoding two, 1-m flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios ff60 0000h ? ff6f ffffh ff20 0000h ? ff2f ffffh 1 fb_50_en ? r/w. enables decoding two, 1-m flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios ff50 0000h ? ff5f ffffh ff10 0000h ? ff1f ffffh 0 fb_40_en ? r/w. enables decoding two, 1-m flash bios memory ranges. 0 = disable 1 = enable the following ranges for the flash bios ff40 0000h ? ff4f ffffh ff00 0000h ? ff0f ffffh 342 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.1.35 func_dis?function disable register (lpc i/f?d31:f0) offset address: f2h attribute: r/w default value: 00h size: 16 bits lockable: no power well: core bit description 15 d29_f7_disable ? r/w. software sets this bit to disable the usb ehci controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = usb ehci controller is enabled 1 = usb ehci controller is disabled 14 lpc bridge disable (d31f0d) ? r/w. software sets this to 1 to disable the lpc bridge. 0 = enable 1 = disable. when disabled, the following spaces will no longer be decoded by the lpc bridge: ?device 31, function 0 configuration space ?memory cycles below 16 mb (100000h) ?i/o cycles below 64 kb (100h) ?the internal i/oxapic at fec0_0000 to fecf_ffff note: memory cycles in the lpc bios range below 4 gb will still be decoded when this bit is set, but the aliases at the top of 1 mb (the e and f segment) no longer will be decoded. 13:12 reserved 11 d29_f3_disable ? r/w. software sets this bit to disable the usb uhci controller #4 function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = usb uhci controller #4 is enabled 1 = usb uhci controller #4 is disabled 10 d29_f2_disable ? r/w. software sets this bit to disable the usb uhci controller #3 function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = usb uhci controller #3 is enabled 1 = usb uhci controller #3 is disabled 9 d29_f1_disable ? r/w. software sets this bit to disable the usb uhci controller #2 function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = usb uhci controller #2 is enabled 1 = usb uhci controller #2 is disabled 8 d29_f0_disable ? r/w. software sets this bit to disable the usb uhci controller #1 function.bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = usb uhci controller #1 is enabled 1 = usb uhci controller #1 is disabled 7 reserved 6 d31_f6_disable ? r/w. software sets this bit to disable the ac ?97 modem controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = ac?97 modem is enabled 1 = ac?97 modem is disabled intel ? 82801eb ich5 / 82801er ich5r datasheet 343 lpc interface bridge registers (d31:f0) note: 1. software must always disable all functionality within the function before disabling the configuration space. 2. configuration writes to internal devices, when the devices are disabled, are illegal and may cause undefined results. 5 d31_f5_disable ? r/w. software sets this bit to disable the ac ?97 audio controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = ac ?97 audio controller is enabled 1 = ac ?97 audio controller is disabled 4 reserved 3 d31_f3_disable ? r/w. software sets this bit to disable the smbus host controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = smbus controller is enabled 1 = smbus controller is disabled 2 d31_f2_disable ? r/w. software sets this bit to disable the sata host controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = sata controller is enabled 1 = sata controller is disabled 1 d31_f1_disable ? r/w. software sets this bit to disable the ide controller function. bios must not enable i/o or memory address space decode, interrupt generation, or any other functionality of functions that are to be disabled . 0 = ide controller is enabled 1 = ide controller is disabled 0 smb_for_bios ? r/w. this bit is used in conjunction with bit 3 in this register. 0 = no effect. 1 = allows the smbus i/o space to be accessible by software when bit 3 in this register is set. the pci configuration space is hidden in this case. note that if bit 3 is set alone, the decode of both smbus pci configuration and i/o space will be disabled. bit description 344 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.2 dma i/o registers (lpc i/f?d31:f0) table 142. dma registers (sheet 1 of 2) port alias register name default type 00h 10h channel 0 dma base & current address undefined r/w 01h 11h channel 0 dma base & current count undefined r/w 02h 12h channel 1 dma base & current address undefined r/w 03h 13h channel 1 dma base & current count undefined r/w 04h 14h channel 2 dma base & current address undefined r/w 05h 15h channel 2 dma base & current count undefined r/w 06h 16h channel 3 dma base & current address undefined r/w 07h 17h channel 3 dma base & current count undefined r/w 08h 18h channel 0?3 dma command undefined wo channel 0?3 dma status undefined ro 0ah 1ah channel 0?3 dma write single mask 000001xxb wo 0bh 1bh channel 0?3 dma channel mode 000000xxb wo 0ch 1ch channel 0?3 dma clear byte pointer undefined wo 0dh 1dh channel 0?3 dma master clear undefined wo 0eh 1eh channel 0?3 dma clear mask undefined wo 0fh 1fh channel 0?3 dma write all mask 0fh r/w 80h 90h reserved page undefined r/w 81h 91h channel 2 dma memory low page undefined r/w 82h ? channel 3 dma memory low page undefined r/w 83h 93h channel 1 dma memory low page undefined r/w 84h?86h 94h?96h reserved pages undefined r/w 87h 97h channel 0 dma memory low page undefined r/w 88h 98h reserved page undefined r/w 89h 99h channel 6 dma memory low page undefined r/w 8ah 9ah channel 7 dma memory low page undefined r/w 8bh 9bh channel 5 dma memory low page undefined r/w 8ch?8eh 9ch?9eh reserved page undefined r/w 8fh 9fh refresh low page undefined r/w c0h c1h channel 4 dma base & current address undefined r/w c2h c3h channel 4 dma base & current count undefined r/w c4h c5h channel 5 dma base & current address undefined r/w c6h c7h channel 5 dma base & current count undefined r/w c8h c9h channel 6 dma base & current address undefined r/w cah cbh channel 6 dma base & current count undefined r/w cch cdh channel 7 dma base & current address undefined r/w intel ? 82801eb ich5 / 82801er ich5r datasheet 345 lpc interface bridge registers (d31:f0) 9.2.1 dmabase_ca?dma base and current address registers (lpc i/f?d31:f0) i/o address: ch. #0 = 00h; ch. #1 = 02h attribute: r/w ch. #2 = 04h; ch. #3 = 06h size: 16 bit (per channel), ch. #5 = c4h ch. #6 = c8h but accessed in two 8-bit ch. #7 = cch; quantities default value: undef lockable: no power well: core ceh cfh channel 7 dma base & current count undefined r/w d0h d1h channel 4?7 dma command undefined wo channel 4?7 dma status undefined ro d4h d5h channel 4?7 dma write single mask 000001xxb wo d6h d7h channel 4?7 dma channel mode 000000xxb wo d8h d9h channel 4?7 dma clear byte pointer undefined wo dah dbh channel 4?7 dma master clear undefined wo dch ddh channel 4?7 dma clear mask undefined wo deh dfh channel 4?7 dma write all mask 0fh r/w table 142. dma registers (sheet 2 of 2) port alias register name default type bit description 15:0 base and current address ? r/w. this register determines the address for the transfers to be performed. the address specified points to two separate registers. on writes, the value is stored in the base address register and copied to the current address register. on reads, the value is returned from the current address register. the address increments/decrements in the current address register after each transfer, depending on the mode of the transfer. if the channel is in auto-initialize mode, the current address register will be reloaded from the base address register after a terminal count is generated. for transfers to/from a 16-bit slave (channel?s 5-7), the address is shifted left one bit location. bit 15 will be shifted into bit 16. the register is accessed in 8 bit quantities. the byte is pointed to by the current byte pointer flip/flop. before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first 346 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.2.2 dmabase_cc?dma base and current count registers (lpc i/f?d31:f0) i/o address: ch. #0 = 01h; ch. #1 = 03h attribute: r/w ch. #2 = 05h; ch. #3 = 07h size: 16-bit (per channel), ch. #5 = c6h; ch. #6 = cah but accessed in two 8-bit ch. #7 = ceh; quantities default value: undefined lockable: no power well: core 9.2.3 dmamem_lp?dma memory low page registers (lpc i/f?d31:f0) i/o address: ch. #0 = 87h; ch. #1 = 83h ch. #2 = 81h; ch. #3 = 82h ch. #5 = 8bh; ch. #6 = 89h ch. #7 = 8ah; attribute: r/w default value: undefined size: 8-bit lockable: no power well: core bit description 15:0 base and current count ? r/w. this register determines the number of transfers to be performed. the address specified points to two separate registers. on writes, the value is stored in the base count register and copied to the current count register. on reads, the value is returned from the current count register. the actual number of transfers is one more than the number programmed in the base count register (i.e., programming a count of 4h results in 5 transfers). the count is decrements in the current count register after each transfer. when the value in the register rolls from 0 to ffffh, a terminal count is generated. if the channel is in auto-initialize mode, the current count register will be reloaded from the base count register after a terminal count is generated. for transfers to/from an 8-bit slave (channels 0?3), the count register indicates the number of bytes to be transferred. for transfers to/from a 16-bit slave (channels 5?7), the count register indicates the number of words to be transferred. the register is accessed in 8 bit quantities. the byte is pointed to by the current byte pointer flip/flop. before accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first. bit description 7:0 dma low page (isa address bits [23:16]) ? r/w. this register works in conjunction with the dma controller's current address register to define the complete 24-bit address for the dma channel. this register remains static throughout the dma transfer. bit 16 of this register is ignored when in 16 bit i/o count by words mode as it is replaced by the bit 15 shifted out from the current address register. intel ? 82801eb ich5 / 82801er ich5r datasheet 347 lpc interface bridge registers (d31:f0) 9.2.4 dmacmd?dma command register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 08h; ch. #4 ? 7 = d0h attribute: wo default value: undefined size: 8-bit lockable: no power well: core 9.2.5 dmasta?dma status register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 08h; ch. #4 ? 7 = d0h attribute: ro default value: undefined size: 8-bit lockable: no power well: core bit description 7:5 reserved. must be 0. 4 dma group arbitration priority ? wo. each channel group is individually assigned either fixed or rotating arbitration priority. at part reset, each group is initialized in fixed priority. 0 = fixed priority to the channel group 1 = rotating priority to the group. 3 reserved. must be 0 2 dma channel group enable ? wo. both channel groups are enabled following part reset. 0 = enable the dma channel group. 1 = disable. disabling channel group 4?7 also disables channel group 0?3, which is cascaded through channel 4. 1:0 reserved. must be 0. bit description 7:4 channel request status ? ro. when a valid dma request is pending for a channel, the corresponding bit is set to 1. when a dma request is not pending for a particular channel, the corresponding bit is set to 0. the source of the dreq may be hardware or a software request. note that channel 4 is the cascade channel, so the request status of channel 4 is a logical or of the request status for channels 0 through 3. 4 = channel 0 5 = channel 1 (5) 6 = channel 2 (6) 7 = channel 3 (7) 3:0 channel terminal count status ? ro. when a channel reaches terminal count (tc), its status bit is set to 1. if tc has not been reached, the status bit is set to 0. channel 4 is programmed for cascade, so the tc bit response for channel 4 is irrelevant: 0 = channel 0 1 = channel 1 (5) 2 = channel 2 (6) 3 = channel 3 (7) 348 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.2.6 dma_wrsmsk?dma write single mask register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0ah; ch. #4 ? 7 = d4h attribute: wo default value: 0000 01xx size: 8-bit lockable: no power well: core bit description 7:3 reserved. must be 0. 2 channel mask select ? wo. 0 = enable dreq for the selected channel. the channel is selected through bits [1:0]. therefore, only one channel can be masked / unmasked at a time. 1 = disable dreq for the selected channel. 1:0 dma channel select ? wo. these bits select the dma channel mode register to program. 00 = channel 0 (4) 01 = channel 1 (5) 10 = channel 2 (6) 11 = channel 3 (7) intel ? 82801eb ich5 / 82801er ich5r datasheet 349 lpc interface bridge registers (d31:f0) 9.2.7 dmach_mode?dma channel mode register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0bh; ch. #4 ? 7 = d6h attribute: wo default value: 0000 00xx size: 8-bit lockable: no power well: core 9.2.8 dma clear byte pointer register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0ch; ch. #4 ? 7 = d8h attribute: wo default value: xxxx xxxx size: 8-bit lockable: no power well: core bit description 7:6 dma transfer mode ? wo. each dma channel can be programmed in one of four different modes: 00 = demand mode 01 = single mode 10 = reserved 11 = cascade mode 5 address increment/decrement select ? wo. this bit controls address increment/decrement during dma transfers. 0 = address increment. (default after part reset or master clear) 1 = address decrement. 4 autoinitialize enable ? wo. 0 = autoinitialize feature is disabled and dma transfers terminate on a terminal count. a part reset or master clear disables autoinitialization. 1 = dma restores the base address and count registers to the current registers following a terminal count (tc). 3:2 dma transfer type ? wo. these bits represent the direction of the dma transfer. when the channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type is irrelevant. 00 = verify ? no i/o or memory strobes generated 01 = write ? data transferred from the i/o devices to memory 10 = read ? data transferred from memory to the i/o device 11 = illegal 1:0 dma channel select ? wo. these bits select the dma channel mode register that will be written by bits [7:2]. 00 = channel 0 (4) 01 = channel 1 (5) 10 = channel 2 (6) 11 = channel 3 (7) bit description 7:0 clear byte pointer ? wo. no specific pattern. command enabled with a write to the i/o port address. writing to this register initializes the byte pointer flip/flop to a known state. it clears the internal latch used to address the upper or lower byte of the 16-bit address and word count registers. the latch is also cleared by part reset and by the master clear command. this command precedes the first access to a 16-bit dma controller register. the first access to a 16-bit register will then access the significant byte, and the second access automatically accesses the most significant byte. 350 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.2.9 dma master clear register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0dh; ch. #4 ? 7 = dah attribute: wo default value: xxxx xxxx size: 8-bit 9.2.10 dma_clmsk?dma clear mask register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0eh; ch. #4 ? 7 = dch attribute: wo default value: xxxx xxxx size: 8-bit lockable: no power well: core 9.2.11 dma_wrmsk?dma write all mask register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0fh; ch. #4 ? 7 = deh attribute: r/w default value: 0000 1111 size: 8-bit lockable: no power well: core bit description 7:0 master clear ? wo. no specific pattern. enabled with a write to the port. this has the same effect as the hardware reset. the command, status, request, and byte pointer flip/flop registers are cleared and the mask register is set. bit description 7:0 clear mask register ? wo. no specific pattern. command enabled with a write to the port. bit description 7:4 reserved. must be 0. 3:0 channel mask bits ? r/w. this register permits all four channels to be simultaneously enabled/ disabled instead of enabling/disabling each channel individually, as is the case with the mask register ? write single mask bit. in addition, this register has a read path to allow the status of the channel mask bits to be read. a channel's mask bit is automatically set to 1 when the current byte/ word count register reaches terminal count (unless the channel is in auto-initialization mode). setting the bit(s) to a 1 disables the corresponding dreq(s). setting the bit(s) to a 0 enables the corresponding dreq(s). bits [3:0] are set to 1 upon part reset or master clear. when read, bits [3:0] indicate the dma channel [3:0] ([7:4]) mask status. bit 0 = channel 0 (4) 1 = masked, 0 = not masked bit 1 = channel 1 (5) 1 = masked, 0 = not masked bit 2 = channel 2 (6) 1 = masked, 0 = not masked bit 3 = channel 3 (7) 1 = masked, 0 = not masked note: disabling channel 4 also disables channels 0?3 due to the cascade of channel?s 0 ? 3 through channel 4. intel ? 82801eb ich5 / 82801er ich5r datasheet 351 lpc interface bridge registers (d31:f0) 9.3 timer i/o registers (lpc i/f?d31:f0) port aliases register name default value type 40h 50h counter 0 interval time status byte format 0xxxxxxxb ro counter 0 counter access port undefined r/w 41h 51h counter 1 interval time status byte format 0xxxxxxxb ro counter 1 counter access port undefined r/w 42h 52h counter 2 interval time status byte format 0xxxxxxxb ro counter 2 counter access port undefined r/w 43h 53h timer control word undefined wo timer control word register xxxxxxx0b wo counter latch command x0h wo 352 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.3.1 tcw?timer control word register (lpc i/f?d31:f0) i/o address: 43h attribute: wo default value: all bits undefined size: 8 bits this register is programmed prior to any counter being accessed to specify counter modes. following part reset, the control words for each register are undefined and each counter output is 0. each timer must be programmed to bring it into a known state. there are two special commands that can be issued to the counters through this register, the read back command and the counter latch command. when these commands are chosen, several bits within this register are redefined. these register formats are described below. bit description 7:6 counter select ? wo. the counter selection bits select the counter the control word acts upon as shown below. the read back command is selected when bits[7:6] are both 1. 00 = counter 0 select 01 = counter 1 select 10 = counter 2 select 11 = read back command 5:4 read/write select ? wo. these bits are the read/write control bits. the actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb 3:1 counter mode selection ? wo. these bits select one of six possible modes of operation for the selected counter. 000 = mode 0 out signal on end of count (=0) 001 = mode 1 hardware retriggerable one-shot x10 = mode 2 rate generator (divide by n counter) x11 = mode 3 square wave output 100 = mode 4 software triggered strobe 101 = mode 5 hardware triggered strobe 0 binary/bcd countdown select ? wo. 0 = binary countdown is used. the largest possible binary count is 2 16 1 = binary coded decimal (bcd) count is used. the largest possible bcd count is 10 4 intel ? 82801eb ich5 / 82801er ich5r datasheet 353 lpc interface bridge registers (d31:f0) 9.3.1.1 rdbk_cmd?read back command (lpc i/f?d31:f0) the read back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. status and/or count may be latched in any or all of the counters by selecting the counter during the register write. the count and status remain latched until read, and further latch commands are ignored until the count is read. both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to 0. if both are latched, the first read operation from that counter returns the latched status. the next one or two reads, depending on whether the counter is programmed for one or two byte counts, returns the latched count. subsequent reads return an unlatched count. 9.3.1.2 ltch_cmd?counter latch command (lpc i/f?d31:f0) the counter latch command latches the current count value. this command is used to insure that the count read from the counter is accurate. the count value is then read from each counter?s count register through the counter ports access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2). the count must be read according to the programmed format (i.e., if the counter is programmed for two byte counts, two bytes must be read). the two bytes do not have to be read one right after the other (read, write, or programming operations for other counters may be inserted between the reads). if a counter is latched once and then latched again before the count is read, the second counter latch command is ignored. bit description 7:6 read back command. must be 11 to select the read back command 5 latch count of selected counters. 0 = current count value of the selected counters will be latched 1 = current count will not be latched 4 latch status of selected counters. 0 = status of the selected counters will be latched 1 = status will not be latched 3 counter 2 select. 1 = counter 2 count and/or status will be latched 2 counter 1 select. 1 = counter 1 count and/or status will be latched 1 counter 0 select. 1 = counter 0 count and/or status will be latched 0 reserved. must be 0. bit description 7:6 counter selection. these bits select the counter for latching. if 11 is written, then the write is interpreted as a read back command. 00 = counter 0 01 = counter 1 10 = counter 2 5:4 counter latch command. 00 = selects the counter latch command. 3:0 reserved. must be 0. 354 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.3.2 sbyte_fmt?interval timer status byte format register (lpc i/f?d31:f0) i/o address: counter 0 = 40h, counter 1 = 41h, attribute: ro counter 2 = 42h size: 8 bits per counter default value: bits[6:0] undefined, bit 7=0 each counter?s status byte can be read following a read back command. if latch status is chosen (bit 4=0, read back command) as a read back option for a given counter, the next read from the counter's counter access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. the status byte returns the following: bit description 7 counter out pin state ? ro. 0 = out pin of the counter is also a 0 1 = out pin of the counter is also a 1 6 count register status ? ro. this bit indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). the exact time this happens depends on the counter mode, but until the count is loaded into the counting element (ce), the count value will be incorrect. 0 = count has been transferred from cr to ce and is available for reading. 1 = null count. count has not been transferred from cr to ce and is not yet available for reading. 5:4 read/write selection status ? ro. these reflect the read/write selection made through bits[5:4] of the control register. the binary codes returned during the status read match the codes used to program the counter read/write selection. 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb 3:1 mode selection status ? ro. these bits return the counter mode programming. the binary code returned matches the code used to program the counter mode, as listed under the bit function above. 000 = mode 0 out signal on end of count (=0) 001 = mode 1 hardware retriggerable one-shot x10 = mode 2 rate generator (divide by n counter) x11 = mode 3 square wave output 100 = mode 4 software triggered strobe 101 = mode 5 hardware triggered strobe 0 countdown type status ? ro. this bit reflects the current countdown type. 0 = binary countdown 1 = binary coded decimal (bcd) countdown. intel ? 82801eb ich5 / 82801er ich5r datasheet 355 lpc interface bridge registers (d31:f0) 9.3.3 counter access ports register (lpc i/f?d31:f0) i/o address: counter 0 ? 40h, counter 1 ? 41h, attribute: r/w counter 2 ? 42h default value: all bits undefined size: 8 bit 9.4 8259 interrupt controller (pic) registers (lpc i/f?d31:f0) 9.4.1 interrupt controller i/o map (lpc i/f?d31:f0) the interrupt controller registers are located at 20h and 21h for the master controller (irq 0 ? 7), and at a0h and a1h for the slave controller (irq 8 ? 13). these registers have multiple functions, depending upon the data written to them. table 143 shows the different register possibilities for each address. note: refer to note addressing active-low interrupt sources in 8259 interrupt controllers section ( section 5.8 ). bit description 7:0 counter port ? r/w. each counter port address is used to program the 16-bit count register. the order of programming, either lsb only, msb only, or lsb then msb, is defined with the interval counter control register at port 43h. the counter port is also used to read the current count from the count register, and return the status of the counter programming following a read back command. table 143. pic registers (lpc i/f?d31:f0) port aliases register name default value type 20h 24h, 28h, 2ch, 30h, 34h, 38h, 3ch master pic icw1 init. cmd word 1 undefined wo master pic ocw2 op ctrl word 2 001xxxxxb wo master pic ocw3 op ctrl word 3 x01xxx10b wo 21h 25h, 29h, 2dh, 31h, 35h, 39h, 3dh master pic icw2 init. cmd word 2 undefined wo master pic icw3 init. cmd word 3 undefined wo master pic icw4 init. cmd word 4 01h wo master pic ocw1 op ctrl word 1 00h r/w a0h a4h, a8h, ach, b0h, b4h, b8h, bch slave pic icw1 init. cmd word 1 undefined wo slave pic ocw2 op ctrl word 2 001xxxxxb wo slave pic ocw3 op ctrl word 3 x01xxx10b wo a1h a5h, a9h, adh, b1h, b5h, b9h, bdh slave pic icw2 init. cmd word 2 undefined wo slave pic icw3 init. cmd word 3 undefined wo slave pic icw4 init. cmd word 4 01h wo slave pic ocw1 op ctrl word 1 00h r/w 4d0h ? master pic edge/level triggered 00h r/w 4d1h ? slave pic edge/level triggered 00h r/w 356 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.4.2 icw1?initialization command word 1 register (lpc i/f?d31:f0) offset address: master controller ? 20h attribute: wo slave controller ? a0h size: 8 bit /controller default value: all bits undefined a write to initialization command word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. the interrupt mask register is cleared. 2. irq7 input is assigned priority 7. 3. the slave mode address is set to 7. 4. special mask mode is cleared and status read is set to irr. once this write occurs, the controller expects writes to icw2, icw3, and icw4 to complete the initialization sequence. bit description 7:5 icw/ocw select ? wo. these bits are mcs-85 specific, and not needed. 000 = should be programmed to 000b 4 icw/ocw select ? wo. 1 = this bit must be a 1 to select icw1 and enable the icw2, icw3, and icw4 sequence. 3 edge/level bank select (ltim) ? wo. disabled. replaced by the edge/level triggered control registers (elcr). 2 adi ? wo. 0 = ignored for the intel ? ich5. should be programmed to 0. 1 single or cascade (sngl) ? wo. 0 = must be programmed to a 0 to indicate two controllers operating in cascade mode. 0 icw4 write required (ic4) ? wo. 1 = this bit must be programmed to a 1 to indicate that icw4 needs to be programmed. intel ? 82801eb ich5 / 82801er ich5r datasheet 357 lpc interface bridge registers (d31:f0) 9.4.3 icw2?initialization command word 2 register (lpc i/f?d31:f0) offset address: master controller ? 21h attribute: wo slave controller ? a1h size: 8 bit /controller default value: all bits undefined icw2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. the value programmed for bits[7:3] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each irq on the controller. typical isa icw2 values are 08h for the master controller and 70h for the slave controller. 9.4.4 icw3?master controller initialization command word 3 register (lpc i/f?d31:f0) offset address: 21h attribute: wo default value: all bits undefined size: 8 bits bit description 7:3 interrupt vector base address ? wo. bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. 2:0 interrupt request level ? wo. when writing icw2, these bits should all be 0. during an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. this is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second inta# cycle. the code is a three bit binary code: code master interrupt slave interrupt 000 irq0 irq8 001 irq1 irq9 010 irq2 irq10 011 irq3 irq11 100 irq4 irq12 101 irq5 irq13 110 irq6 irq14 111 irq7 irq15 bit description 7:3 0 = these bits must be programmed to 0. 2 cascaded interrupt controller irq connection ? wo. this bit indicates that the slave controller is cascaded on irq2. when irq8#?irq15 is asserted, it goes through the slave controller?s priority resolver. the slave controller?s intr output onto irq2. irq2 then goes through the master controller?s priority solver. if it wins, the intr signal is asserted to the processor, and the returning interrupt acknowledge returns the interrupt vector for the slave controller. 1 = this bit must always be programmed to a 1. 1:0 0 = these bits must be programmed to 0. 358 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.4.5 icw3?slave controller initialization command word 3 register (lpc i/f?d31:f0) offset address: a1h attribute: wo default value: all bits undefined size: 8 bits 9.4.6 icw4?initialization command word 4 register (lpc i/f?d31:f0) offset address: master controller ? 021h attribute: wo slave controller ? 0a1h size: 8 bits bit description 7:3 0 = these bits must be programmed to 0. 2:0 slave identification code ? wo. these bits are compared against the slave identification code broadcast by the master controller from the trailing edge of the first internal inta# pulse to the trailing edge of the second internal inta# pulse. these bits must be programmed to 02h to match the code broadcast by the master controller. when 02h is broadcast by the master controller during the inta# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector. bit description 7:5 0 = these bits must be programmed to 0. 4 special fully nested mode (sfnm) ? wo. 0 = should normally be disabled by writing a 0 to this bit. 1 = special fully nested mode is programmed. 3 buffered mode (buf) ? wo. 0 = must be programmed to 0 for the intel ? ich5. this is non-buffered mode. 2 master/slave in buffered mode ? wo. not used. 0 = should always be programmed to 0. 1 automatic end of interrupt (aeoi) ? wo. 0 = this bit should normally be programmed to 0. this is the normal end of interrupt. 1 = automatic end of interrupt (aeoi) mode is programmed. 0 microprocessor mode ? wo. 1 = must be programmed to 1 to indicate that the controller is operating in an intel architecture-based system. intel ? 82801eb ich5 / 82801er ich5r datasheet 359 lpc interface bridge registers (d31:f0) 9.4.7 ocw1?operational control word 1 (interrupt mask) register (lpc i/f?d31:f0) offset address: master controller ? 021h attribute: r/w slave controller ? 0a1h size: 8 bits default value: 00h 9.4.8 ocw2?operational control word 2 register (lpc i/f?d31:f0) offset address: master controller ? 020h attribute: wo slave controller ? 0a0h size: 8 bits default value: bit[4:0]=undefined, bit[7:5]=001 following a part reset or icw initialization, the controller enters the fully nested mode of operation. non-specific eoi without rotation is the default. both rotation mode and specific eoi mode are disabled following initialization. bit description 7:0 interrupt request mask ? r/w. when a 1 is written to any bit in this register, the corresponding irq line is masked. when a 0 is written to any bit in this register, the corresponding irq mask bit is cleared, and interrupt requests will again be accepted by the controller. masking irq2 on the master controller will also mask the interrupt requests from the slave controller. bit description 7:5 rotate and eoi codes (r, sl, eoi) ? wo. these three bits control the rotate and end of interrupt modes and combinations of the two. 000 = rotate in auto eoi mode (clear) 001 = non-specific eoi command 010 = no operation 011 = ? specific eoi command 100 = rotate in auto eoi mode (set) 101 = rotate on non-specific eoi command 110 = ? set priority command 111 = ? rotate on specific eoi command ? l0 ? l2 are used 4:3 ocw2 select ? wo. when selecting ocw2, bits 4:3 = 00 2:0 interrupt level select (l2, l1, l0) ? wo. l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active. a simple binary code, outlined below, selects the channel for the command to act upon. when the sl bit is inactive, these bits do not have a defined function; programming l2, l1 and l0 to 0 is sufficient in this case. bits interrupt level bits interrupt level 000 irq0/8 100 irq4/12 001 irq1/9 101 irq5/13 010 irq2/10 110 irq6/14 011 irq3/11 111 irq7/15 360 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.4.9 ocw3?operational control word 3 register (lpc i/f?d31:f0) offset address: master controller ? 020h attribute: wo slave controller ? 0a0h size: 8 bits default value: bit[6,0]=0, bit[7,4:2]=undefined, bit[5,1]=1 bit description 7 reserved. must be 0. 6 special mask mode (smm) ? wo. 1 = the special mask mode can be used by an interrupt service routine to dynamically alter the system priority structure while the routine is executing, through selective enabling/disabling of the other channel's mask bits. bit 5, the esmm bit, must be set for this bit to have any meaning. 5 enable special mask mode (esmm) ? wo. 0 = disable. the smm bit becomes a ?don't care?. 1 = enable the smm bit to set or reset the special mask mode. 4:3 ocw3 select ? wo. when selecting ocw3, bits 4:3 = 01 2 poll mode command ? wo. 0 = disable. poll command is not issued. 1 = enable. the next i/o read to the interrupt controller is treated as an interrupt acknowledge cycle. an encoded byte is driven onto the data bus, representing the highest priority level requesting service. 1:0 register read command ? wo. these bits provide control for reading the in-service register (isr) and the interrupt request register (irr). when bit 1=0, bit 0 will not affect the register read selection. when bit 1=1, bit 0 selects the register status returned following an ocw3 read. if bit 0=0, the irr will be read. if bit 0=1, the isr will be read. following icw initialization, the default ocw3 port address read will be ?read irr?. to retain the current selection (read isr or read irr), always write a 0 to bit 1 when programming this register. the selected register can be read repeatedly without reprogramming ocw3. to select a new status register, ocw3 must be reprogrammed prior to attempting the read. 00 = no action 01 = no action 10 = read irq register 11 = read is register intel ? 82801eb ich5 / 82801er ich5r datasheet 361 lpc interface bridge registers (d31:f0) 9.4.10 elcr1?master controller edge/level triggered register (lpc i/f?d31:f0) offset address: 4d0h attribute: r/w default value: 00h size: 8 bits in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high level. the cascade channel, irq2, the heart beat timer (irq0), and the keyboard controller (irq1), cannot be put into level mode. bit description 7 irq7 ecl ? r/w. 0 = edge 1 = level 6 irq6 ecl ? r/w. 0 = edge 1 = level 5 irq5 ecl ? r/w. 0 = edge 1 = level 4 irq4 ecl ? r/w. 0 = edge 1 = level 3 irq3 ecl ? r/w. 0 = edge 1 = level 2:0 reserved. must be 0. 362 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.4.11 elcr2?slave controller edge/level triggered register (lpc i/f?d31:f0) offset address: 4d1h attribute: r/w default value: 00h size: 8 bits in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high level. the real time clock, irq8#, and the floating point error interrupt, irq13, cannot be programmed for level mode. bit description 7 irq15 ecl ? r/w. 0 = edge 1 = level 6 irq14 ecl ? r/w. 0 = edge 1 = level 5 reserved. must be 0. 4 irq12 ecl ? r/w. 0 = edge 1 = level 3 irq11 ecl ? r/w. 0 = edge 1 = level 2 irq10 ecl ? r/w. 0 = edge 1 = level 1 irq9 ecl ? r/w. 0 = edge 1 = level 0 reserved. must be 0. intel ? 82801eb ich5 / 82801er ich5r datasheet 363 lpc interface bridge registers (d31:f0) 9.5 advanced interrupt controller (apic)(d31:f0) 9.5.1 apic register map (lpc i/f?d31:f0) the apic is accessed via an indirect addressing scheme. two registers are visible by software for manipulation of most of the apic registers. these registers are mapped into memory space. the registers are shown in table 144 . table 145 lists the registers which can be accessed within the apic via the index register. when accessing these registers, accesses must be done a dword at a time. for example, software should never access byte 2 from the data register before accessing bytes 0 and 1. the hardware will not attempt to recover from a bad programming model in this case. 9.5.2 ind?index register (lpc i/f?d31:f0) memory address fec0_0000h attribute: r/w default value: 00h size: 8 bits the index register will select which apic indirect register to be manipulated by software. the selector values for the indirect registers are listed in table 145 . software will program this register to select the desired apic internal register. . table 144. apic direct registers (lpc i/f?d31:f0) address mnemonic register name size type fec0_0000h ind index 8 bits r/w fec0_0010h dat data 32 bits r/w feco_0020h irqpa irq pin assertion 32 bits wo feco_0040h eoir eoi 32 bits wo table 145. apic indirect registers (lpc i/f?d31:f0) index mnemonic register name size type 00 id identification 32 bits r/w 01 ver version 32 bits ro 02?0f ? reserved ? ro 10?11 redir_tbl0 redirection table 0 64 bits r/w, ro 12?13 redir_tbl1 redirection table 1 64 bits r/w, ro ... ... ... ... ... 3e?3f redir_tbl23 redirection table 23 64 bits r/w, ro 40?ff ? reserved ? ro bit description 7:0 apic index ? r/w. this is an 8-bit pointer into the i/o apic register table. 364 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.5.3 dat?data register (lpc i/f?d31:f0) memory address fec0_0010h attribute: r/w default value: 00000000h size: 32 bits this is a 32-bit register specifying the data to be read or written to the register pointed to by the index register. this register can only be accessed in dword quantities. 9.5.4 irqpa?irq pin assertion register (lpc i/f?d31:f0) memory address fec0_0020h attribute: wo default value: n/a size: 32 bits the irq pin assertion register is present to provide a mechanism to scale the number of interrupt inputs into the i/o apic without increasing the number of dedicated input pins. when a device that supports this interrupt assertion protocol requires interrupt service, that device will issue a write to this register. bits 4:0 written to this register contain the irq number for this interrupt. the only valid values are 0 ? 23. bits 31:5 are ignored. to provide for future expansion, peripherals should always write a value of 0 for bits 31:5. see section 5.9.3 for more details on how pci devices will use this field. note: writes to this register are only allowed by the processor and by masters on the ich5?s pci bus. writes by devices on pci buses above the ich5 (e.g., a pci segment on a p64h2) are not supported. bit description 7:0 apic data ? r/w. this is a 32-bit register for the data to be read or written to the apic indirect register pointed to by the index register. bit description 31:5 reserved. to provide for future expansion, the processor should always write a value of 0 to bits 31:5. 4:0 irq number ? wo. bits 4:0 written to this register contain the irq number for this interrupt. the only valid values are 0?23. intel ? 82801eb ich5 / 82801er ich5r datasheet 365 lpc interface bridge registers (d31:f0) 9.5.5 eoir?eoi register (lpc i/f?d31:f0) memory address fec0_0040h attribute: wo default value: n/a size: 32 bits the eoi register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. when a write is issued to this register, the i/o apic will check the lower 8 bits written to this register, and compare it with the vector field for each entry in the i/o redirection table. when a match is found, the remote_irr bit for that i/o redirection entry will be cleared. note: if multiple i/o redirection entries, for any reason, assign the same vector for more than one interrupt input, each of those entries will have the remote_irr bit reset to 0. the interrupt which was prematurely reset will not be lost because if its input remained active when the remote_irr bit is cleared, the interrupt will be reissued and serviced at a later time. note: only bits 7:0 are actually used. bits 31:8 are ignored by the ich5. note: to provide for future expansion, the processor should always write a value of 0 to bits 31:8. 9.5.6 id?identification register (lpc i/f?d31:f0) index offset: 00h attribute: r/w default value: 00000000h size: 32 bits the apic id serves as a physical name of the apic. the apic bus arbitration id for the apic is derived from its i/o apic id. this register is reset to 0 on power up reset. bit description 31:8 reserved. to provide for future expansion, the processor should always write a value of 0 to bits 31:8. 7:0 redirection entry clear ? wo. when a write is issued to this register, the i/o apic will check this field, and compare it with the vector field for each entry in the i/o redirection table. when a match is found, the remote_irr bit for that i/o redirection entry will be cleared. bit description 31:28 reserved 27:24 apic id ? r/w. software must program this value before using the apic. 23:16 reserved 15 scratchpad bit. 14:0 reserved 366 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.5.7 ver?version register (lpc i/f?d31:f0) index offset: 01h attribute: ro default value: 00170002h size: 32 bits each i/o apic contains a hardwired version register that identifies different implementation of apic and their versions. the maximum redirection entry information also is in this register, to let software know how many interrupt are supported by this apic. bit description 31:24 reserved 23:16 maximum redirection entries ? ro. this is the entry number (0 being the lowest entry) of the highest entry in the redirection table. it is equal to the number of interrupt input pins minus one and is in the range 0 through 239. in the intel ? ich5 this field is hardwired to 17h to indicate 24 interrupts. 15 prq ? ro. this bit is set to 1 to indicate that this version of the i/o apic implements the irq assertion register and allows pci devices to write to it to cause interrupts. 14:8 reserved 7:0 version ? ro. this is a version number that identifies the implementation version. intel ? 82801eb ich5 / 82801er ich5r datasheet 367 lpc interface bridge registers (d31:f0) 9.5.8 redir_tbl?redirection table (lpc i/f?d31:f0) index offset: 10h ? 11h (vector 0) through attribute: r/w, ro 3e ? 3fh (vector 23) default value: bit 16 = 1, bits[15:12] = 0. size: 64 bits each, (accessed as all other bits undefined two 32 bit quantities) the redirection table has a dedicated entry for each interrupt input pin. the information in the redirection table is used to translate the interrupt manifestation on the corresponding interrupt pin into an apic message. the apic will respond to an edge triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. once the interrupt is detected, a delivery status bit internally to the i/o apic is set. the state machine will step ahead and wait for an acknowledgment from the apic unit that the interrupt message was sent. only then will the i/o apic be able to recognize a new edge on that interrupt pin. that new edge will only result in a new invocation of the handler if its acceptance by the destination apic causes the interrupt request register bit to go from 0 to 1. (in other words, if the interrupt was not already pending at the destination.) bit description 63:56 destination ? r/w. if bit 11 of this entry is 0 (physical), then bits 59:56 specifies an apic id. in this case, bits 63:59 should be programmed by software to 0. if bit 11 of this entry is 1 (logical), then bits 63:56 specify the logical destination address of a set of processors. 55:48 extended destination id (edid) ? ro. these bits are sent to a local apic only when in front side bus mode. they become bits 11:4 of the address. 47:17 reserved 16 mask ? r/w. 0 = not masked: an edge or level on this interrupt pin results in the delivery of the interrupt to the destination. 1 = masked: interrupts are not delivered nor held pending. setting this bit after the interrupt is accepted by a local apic has no effect on that interrupt. this behavior is identical to the device withdrawing the interrupt before it is posted to the processor. it is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been accepted by a local apic unit but before the interrupt is dispensed to the processor. 15 trigger mode ? r/w. this field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = edge triggered. 1 = level triggered. 14 remote irr ? r/w. this bit is used for level triggered interrupts; its meaning is undefined for edge triggered interrupts. 0 = reset when an eoi message is received from a local apic. 1 = set when local apic/s accept the level interrupt sent by the i/o apic. 13 interrupt input pin polarity ? r/w. this bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = active high. 1 = active low. 12 delivery status ? ro. this field contains the current status of the delivery of this interrupt. writes to this bit have no effect. 0 = idle. no activity for this interrupt. 1 = pending. interrupt has been injected, but delivery is not complete. 368 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) note: delivery mode encoding: 000 = fixed. deliver the signal on the intr signal of all processor cores listed in the destination. trigger mode can be edge or level. 001 = lowest priority. deliver the signal on the intr signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. trigger mode can be edge or level. 010 = smi (system management interrupt). requires the interrupt to be programmed as edge triggered. the vector information is ignored but must be programmed to 0s for future compatibility. ? not supported 011 = reserved 100 = nmi. deliver the signal on the nmi signal of all processor cores listed in the destination. vector information is ignored. nmi is treated as an edge triggered interrupt even if it is programmed as level triggered. for proper operation this redirection table entry must be programmed to edge triggered. the nmi delivery mode does not set the rirr bit. if the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. once the count for the nmi pin is reached again, the interrupt will be sent again. ? not supported 101 = init. deliver the signal to all processor cores listed in the destination by asserting the init signal. all addressed local apics will assume their init state. init is always treated as an edge triggered interrupt even if programmed as level triggered. for proper operation this redirection table entry must be programmed to edge triggered. the init delivery mode does not set the rirr bit. if the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. once the count for the init pin is reached again, the interrupt will be sent again. ? not supported 110 = reserved 111 = extint. deliver the signal to the intr signal of all processor cores listed in the destination as an interrupt that originated in an externally connected 8259a compatible interrupt controller. the inta cycle that corresponds to this extint delivery will be routed to the external controller that is expected to supply the vector. requires the interrupt to be programmed as edge triggered. 11 destination mode ? r/w. this field determines the interpretation of the destination field. 0 = physical. destination apic id is identified by bits 59:56. 1 = logical. destinations are identified by matching bit 63:56 with the logical destination in the destination format register and logical destination register in each local apic. 10:8 delivery mode ? r/w. this field specifies how the apics listed in the destination field should act upon reception of this signal. certain delivery modes will only operate as intended when used in conjunction with a specific trigger mode. these encodings are listed in the note below. 7:0 vector ? r/w. this field contains the interrupt vector for this interrupt. values range between 10h and feh. bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 369 lpc interface bridge registers (d31:f0) 9.6 real time clock registers (lpc i/f?d31:f0) 9.6.1 i/o register address map (lpc i/f?d31:f0) the rtc internal registers and ram are organized as two banks of 128 bytes each, called the standard and extended banks. the first 14 bytes of the standard bank contain the rtc time and date information along with four registers, a ? d, that are used for configuration of the rtc. the extended bank contains a full 128 bytes of battery backed sram, and will be accessible even when the rtc module is disabled (via the rtc configuration register). registers a ? d do not physically exist in the ram. all data movement between the host processor and the real-time clock is done through registers mapped to the standard i/o space. the register map appears in table 146 . notes: 1. i/o locations 70h and 71h are the standard isa location for the real-time clock. the map for this bank is shown in table 147 . locations 72h and 73h are for accessing the extended ram. the extended ram bank is also accessed using an indexed scheme. i/o address 72h is used as the address pointer and i/o address 73h is used as the data register. index addresses above 127h are not valid. if the extended ram is not needed, it may be disabled. 2. software must preserve the value of bit 7 at i/o addresses 70h. when writing to this address, software must first read the value, and then write the same value for bit 7 during the sequential address write. note that port 70h is not directly readable. the only way to read this register is through alt access mode. if the nmi# enable is not changed during normal operation, software can alternatively read this bit once and then retain the value for all subsequent writes to port 70h. the rtc contains two sets of indexed registers that are accessed using the two separate index and target registers (70/71h or 72/73h), as shown in table 147 . table 146. rtc i/o registers (lpc i/f?d31:f0) i/o locations if u128e bit = 0 function 70h and 74h also alias to 72h and 76h real-time clock (standard ram) index register 71h and 75h also alias to 73h and 77h real-time clock (standard ram) target register 72h and 76h extended ram index register (if enabled) 73h and 77h extended ram target register (if enabled) table 147. rtc (standard) ram bank (lpc i/f?d31:f0) index name 00h seconds 01h seconds alarm 02h minutes 03h minutes alarm 04h hours 05h hours alarm 06h day of week 07h day of month 08h month 09h year 0ah register a 0bh register b 0ch register c 0dh register d 0eh?7fh 114 bytes of user ram 370 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.6.2 rtc_rega?register a (lpc i/f?d31:f0) rtc index: 0ah attribute: r/w default value: undefined size: 8-bit lockable: no power well: rtc this register is used for general configuration of the rtc functions. none of the bits are affected by rsmrst# or any other ich5 reset signal. bit description 7 update in progress (uip) ? r/w. this bit may be monitored as a status flag. 0 = the update cycle will not start for at least 492 s. the time, calendar, and alarm information in ram is always available when the uip bit is 0. 1 = the update is soon to occur or is in progress. 6:4 division chain select (dv[2:0]) ? r/w. these three bits control the divider chain for the oscillator, and are not affected by rsmrst# or any other reset signal. dv2 corresponds to bit 6. 010 = normal operation 11x = divider reset 101 = bypass 15 stages (test mode only) 100 = bypass 10 stages (test mode only) 011 = bypass 5 stages (test mode only) 001 = invalid 000 = invalid 3:0 rate select (rs[3:0]) ? r/w. selects one of 13 taps of the 15 stage divider chain. the selected tap can generate a periodic interrupt if the pie bit is set in register b. otherwise this tap will set the pf flag of register c. if the periodic interrupt is not to be used, these bits should all be set to 0. rs3 corresponds to bit 3. 0000 = interrupt never toggles 0001 = 3.90625 ms 0010 = 7.8125 ms 0011 = 122.070 s 0100 = 244.141 s 0101 = 488.281 s 0110 = 976.5625 s 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms intel ? 82801eb ich5 / 82801er ich5r datasheet 371 lpc interface bridge registers (d31:f0) 9.6.3 rtc_regb?register b (general configuration) (lpc i/f?d31:f0) rtc index: 0bh attribute: r/w default value: u0u00uuu (u: undefined) size: 8-bit lockable: no power well: rtc bit description 7 update cycle inhibit (set) ? r/w. enables/inhibits the update cycles. this bit is not affected by rsmrst# nor any other reset signal. 0 = update cycle occurs normally once each second. 1 = a current update cycle will abort and subsequent update cycles will not occur until set is returned to 0. when set is 1, the bios may initialize time and calendar bytes safely. note: this bit should be set then cleared early in bios post after each powerup directly after coin-cell battery insertion. 6 periodic interrupt enable (pie) ? r/w. this bit is cleared by rsmrst#, but not on any other reset. 0 = disable 1 = enable. allows an interrupt to occur with a time base set with the rs bits of register a. 5 alarm interrupt enable (aie) ? r/w. this bit is cleared by rsmrst#, but not on any other reset. 0 = disable 1 = enable. allows an interrupt to occur when the af is set by an alarm match from the update cycle. an alarm can occur once a second, one an hour, once a day, or one a month. 4 update-ended interrupt enable (uie) ? r/w. this bit is cleared by rsmrst#, but not on any other reset. 0 = disable 1 = enable. allows an interrupt to occur when the update cycle ends. 3 square wave enable (sqwe) ? r/w. this bit serves no function in the intel ? ich5. it is left in this register bank to provide compatibility with the motorola 146818b. the ich5 has no sqw pin. this bit is cleared by rsmrst#, but not on any other reset. 2 data mode (dm) ? r/w. this bit specifies either binary or bcd data representation. this bit is not affected by rsmrst# nor any other reset signal. 0 = bcd 1 = binary 1 hour format (hourform) ? r/w. this bit indicates the hour byte format. this bit is not affected by rsmrst# nor any other reset signal. 0 = 12-hour mode. in 12-hour mode, the seventh bit represents am as 0 and pm as one. 1 = 24-hour mode. 0 daylight savings enable (dse) ? r/w. this bit triggers two special hour updates per year. the days for the hour adjustment are those specified in united states federal law as of 1987, which is different than previous years. this bit is not affected by rsmrst# nor any other reset signal. 0 = daylight savings time updates do not occur. 1 = a) update on the first sunday in april, where time increments from 1:59:59 am to 3:00:00 am. b) update on the last sunday in october when the time first reaches 1:59:59 am, it is changed to 1:00:00 am. the time must increment normally for at least two update cycles (seconds) previous to these conditions for the time change to occur properly. 372 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.6.4 rtc_regc?register c (flag register) (lpc i/f?d31:f0) rtc index: 0ch attribute: ro default value: 00u00000 (u: undefined) size: 8-bit lockable: no power well: rtc writes to register c have no effect. 9.6.5 rtc_regd?register d (flag register) (lpc i/f?d31:f0) rtc index: 0dh attribute: r/w default value: 10uuuuuu (u: undefined) size: 8-bit lockable: no power well: rtc bit description 7 interrupt request flag (irqf) ? ro. irqf = (pf * pie) + (af * aie) + (uf *ufe). this bit also causes the ch_irq_b signal to be asserted. this bit is cleared upon rsmrst# or a read of register c. 6 periodic interrupt flag (pf) ? ro. this bit is cleared upon rsmrst# or a read of register c. 0 = if no taps are specified via the rs bits in register a, this flag will not be set. 1 = periodic interrupt flag will be 1 when the tap specified by the rs bits of register a is 1. 5 alarm flag (af) ? ro. 0 = this bit is cleared upon rtcrst# or a read of register c. 1 = alarm flag will be set after all alarm values match the current time. 4 update-ended flag (uf) ? ro. 0 = the bit is cleared upon rsmrst# or a read of register c. 1 = set immediately following an update cycle for each second. 3:0 reserved. will always report 0. bit description 7 valid ram and time bit (vrt) ? r/w. 0 = this bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles. 1 = this bit is hardwired to 1 in the rtc power well. 6 reserved. this bit always returns a 0 and should be set to 0 for write cycles. 5:0 date alarm ? r/w. these bits store the date of month alarm value. if set to 000000b, then a don?t care state is assumed. the host must configure the date alarm for these bits to do anything, yet they can be written at any time. if the date alarm is not enabled, these bits will return 0s to mimic the functionality of the motorola 146818b. these bits are not affected by reset. intel ? 82801eb ich5 / 82801er ich5r datasheet 373 lpc interface bridge registers (d31:f0) 9.7 processor interface registers (lpc i/f?d31:f0) table 148 is the register address map for the processor interface registers. 9.7.1 nmi_sc?nmi status and control register (lpc i/f?d31:f0) i/o address: 61h attribute: r/w, ro default value: 00h size: 8-bit lockable: no power well: core table 148. processor interface pci register address map (lpc i/f?d31:f0) offset mnemonic register name default type 61h nmi_sc nmi status and control 00h r/w, ro 70h nmi_en nmi enable 80h r/w (special) 92h port92 fast a20 and init 00h r/w f0h coproc_err coprocessor error 00h wo cf9h rst_cnt reset control 00h r/w bit description 7 serr# nmi source status (serr#_nmi_sts) ? ro. 1 = pci agent detected a system error and pulses the pci serr# line. this interrupt source is enabled by setting bit 2 to 0. to reset the interrupt, set bit 2 to 1 and then set it to 0. when writing to port 61h, this bit must be 0. 6 iochk# nmi source status (iochk_nmi_sts) ? ro. 1 = an isa agent (via serirq) asserted iochk# on the isa bus. this interrupt source is enabled by setting bit 3 to 0. to reset the interrupt, set bit 3 to 0 and then set it to 1. when writing to port 61h, this bit must be a 0. 5 timer counter 2 out status (tmr2_out_sts) ? ro. this bit reflects the current state of the 8254 counter 2 output. counter 2 must be programmed following any pci reset for this bit to have a determinate value. when writing to port 61h, this bit must be a 0. 4 refresh cycle toggle (ref_toggle) ? ro. this signal toggles from either 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles would occur. when writing to port 61h, this bit must be a 0. 3 iochk# nmi enable (iochk_nmi_en) ? r/w. 0 = enabled. 1 = disabled and cleared. 2 pci serr# enable (pci_serr_en) ? r/w. 0 = serr# nmis are enabled. 1 = serr# nmis are disabled and cleared. 1 speaker data enable ( spkr_dat_en) ? r/w. 0 = spkr output is a 0. 1 = spkr output is equivalent to the counter 2 out signal value. 0 timer counter 2 enable (tim_cnt2_en) ? r/w. 0 = disable 1 = enable 374 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.7.2 nmi_en?nmi enable (and real time clock index) register (lpc i/f?d31:f0) i/o address: 70h attribute: r/w (special) default value: 80h size: 8-bit lockable: no power well: core note: the rtc index field is write-only for normal operation. this field can only be read in alt-access mode. note, however, that this register is aliased to port 74h (documented in), and all bits are readable at that address. 9.7.3 port92?fast a20 and init register (lpc i/f?d31:f0) i/o address: 92h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core bits description 7 nmi enable (nmi_en) ? r/w (special). 0 = enable nmi sources. 1 = disable all nmi sources. 6:0 real time clock index address (rtc_indx) ? r/w (special). this data goes to the rtc to select which register or cmos ram address is being accessed. bit description 7:2 reserved 1 alternate a20 gate (alt_a20_gate) ? r/w. this bit is or?d with the a20gate input signal to generate a20m# to the processor. 0 = a20m# signal can potentially go active. 1 = this bit is set when init# goes active. 0 init_now ? r/w. when this bit transitions from a 0 to a 1, the intel ? ich5 will force init# active for 16 pci clocks. intel ? 82801eb ich5 / 82801er ich5r datasheet 375 lpc interface bridge registers (d31:f0) 9.7.4 coproc_err?coprocessor error register (lpc i/f?d31:f0) i/o address: f0h attribute: wo default value: 00h size: 8-bits lockable: no power well: core 9.7.5 rst_cnt?reset control register (lpc i/f?d31:f0) i/o address: cf9h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core bits description 7:0 coprocessor error (coproc_err) ? wo. any value written to this register will cause ignne# to go active, if ferr# had generated an internal irq13. for ferr# to generate an internal irq13, the coproc_err_en bit (device 31:function 0, offset d0, bit 13) must be 1. bit description 7:4 reserved 3 full reset (full_rst) ? r/w. this bit is used to determine the states of slp_s3#, slp_s4#, and slp_s5# after a cf9 hard reset (sys_rst =1 and rst_cpu is set to 1), after pwrok going low (with rsmrst# high), or after two tco timeouts. 0 = intel ? ich5 will keep slp_s3#, slp_s4# and slp_s5# high. 1 = ich5 will drive slp_s3#, slp_s4# and slp_s5# low for 3 ? 5 seconds. note: when this bit is set, it also causes the full power cycle (slp_s3/4/5# assertion) in response to sysreset#, pwrok#, and watchdog timer reset sources. 2 reset cpu (rst_cpu) ? r/w. when this bit transitions from a 0 to a 1, it initiates a hard or soft reset, as determined by the sys_rst bit (bit 1 of this register). 1 system reset (sys_rst) ? r/w. this bit is used to determine a hard or soft reset to the processor. 0 = when rst_cpu bit goes from 0 to 1, the ich5 performs a soft reset by activating init# for 16 pci clocks. 1 = when rst_cpu bit goes from 0 to 1, the ich5 performs a hard reset by activating pcirst# for 1 millisecond. it also resets the resume well bits (except for those noted throughout the datasheet). the slp_s3#, slp_s4#, and slp_s5# signals will not go active. 0 reserved 376 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.8 power management pci configuration registers (pm?d31:f0) the power management registers are distributed within the pci device 31: function 0 space, as well as a separate i/o range. each register is described below. unless otherwise indicate, bits are in the main (core) power well. bits not explicitly defined in each register are assumed to be reserved. when writing to a reserved bit, the value should always be 0. software should not attempt to use the value read from a reserved bit, as it may not be consistently 1 or 0. table 149 shows a small part of the configuration space for pci device 31: function 0. it includes only those registers dedicated for power management. some of the registers are only used for legacy power management schemes. table 149. power management pci register address map (pm?d31:f0) offset mnemonic register name default type 40h?43h acpi_base acpi base address 00000001h r/w 44h acpi_cntl acpi control 00h r/w a0h gen_pmcon_1 general power management configuration 1 0000h r/w, ro, r/wo a2h gen_pmcon_2 general power management configuration 2 0000h r/w, r/wc a4h gen_pmcon_3 general power management configuration 3 00h r/w, r/wc a8h stpclk_del stop clock delay register 0dh r/w adh usb_tdd usb transient disconnect detect 00h r/w aeh sata_rd_cfg sata raid configuration (intel ? 82801er ich5r only) c0h r/w b8?bbh gpi_rout gpi route control 00000000h r/w c0 trp_fwd_en i/o monitor trap forwarding enable 00h r/w (special) c4?cah mon[ n ]_trp_rng i/o monitor[4:7] trap range 0000h r/w cch mon_trp_msk i/o monitor trap range mask 0000h r/w intel ? 82801eb ich5 / 82801er ich5r datasheet 377 lpc interface bridge registers (d31:f0) 9.8.1 gen_pmcon_1?general pm configuration 1 register (pm?d31:f0) offset address: a0h attribute: r/w, ro, r/wo default value: 00h size: 16-bit lockable: no usage: acpi, legacy power well: core bit description 15:11 reserved 10 reserved 9 pwrbtn_lvl ? ro. this bit indicates the current state of the pwrbtn# signal. 0 = low. 1 = high. 8:7 reserved 6 i64_en . software sets this bit to indicate that the processor is an ia_64 processor, not an ia_32 processor. this may be used in various state machines where there are behavioral differences. 5 cpu slp# enable (cpuslp_en) ? r/w. 0 = disable 1 = enables the cpuslp# signal to go active in the s1 state. this reduces the processor power. note: cpuslp# will go active on entry to s3, s4 and s5 even if this bit is not set. 4 smi_lock ? r/wo. when this bit is set, writes to the glb_smi_en bit will have no effect. once the smi_lock bit is set, writes of 0 to smi_lock bit will have no effect (i.e., once set, this bit can only be cleared by pcirst#). 3:2 reserved 1:0 periodic smi# rate select (per_smi_sel) ? r/w. set by software to control the rate at which periodic smi# is generated. 00 = 1 minute 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds 378 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.8.2 gen_pmcon_2?general pm configuration 2 register (pm?d31:f0) offset address: a2h attribute: r/w, r/wc default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: resume note: vrmpwrok is sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by the ich5. bit description 7 dram initialization bit ? r/w. this bit does not effect hardware functionality in any way. bios is expected to set this bit prior to starting the dram initialization sequence and to clear this bit after completing the dram initialization sequence. bios can detect that a dram initialization sequence was interrupted by a reset by reading this bit during the boot sequence. ? if the bit is 1, then the dram initialization was interrupted. ? this bit is reset by the assertion of the rsmrst# pin. 6:5 reserved 4 system reset status (srs) ? r/wc. software clears this bit by writing a 1 to it. 0 = sys_reset# button not pressed. 1 = intel ? ich5 sets this bit when the sys_reset# button is pressed. bios is expected to read this bit and clear it, if it is set. note: this bit is also reset by rsmrst# and cf9h resets. 3 cpu thermal trip status (cts) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when pcirst# is inactive and cputhrmtrip# goes active while the system is in an s0 or s1 state. note: this bit is also reset by rsmrst# and cf9h resets. it is not reset by the shutdown and reboot associated with the cputhrmtrip# event. 2 minimum slp_s4# assertion width violation status ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = hardware sets this bit when the slp_s4# assertion width is less than the time programmed in the slp_s4# minimum assertion width field. when exiting g3, the ich5 begins the timer when the rsmrst# input deasserts. note that this bit is functional regardless of the value in the slp_s4# assertion stretch enable. note: this bit is reset by the assertion of the rsmrst# pin, but can be set in some cases before the default value is readable. 1 cpu power failure (cpupwr_flr) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = indicates that the vrmpwrgd signal from the processor?s vrm went low. 0 pwrok failure (pwrok_flr) ? r/wc. 0 = software clears this bit by writing a 1 to it, or when the system goes into a g3 state. 1 = this bit will be set any time pwrok goes low, when the system was in s0, or s1 state. the bit will be cleared only by software by writing a 1 to this bit or when the system goes to a g3 state. note: see section 5.13.11.3 for more details about the pwrok pin functionality. note: in the case of true pwrok failure, pwrok will go low first before vrmpwrgd. intel ? 82801eb ich5 / 82801er ich5r datasheet 379 lpc interface bridge registers (d31:f0) 9.8.3 gen_pmcon_3?general pm configuration 3 register (pm?d31:f0) offset address: a4h attribute: r/w, r/wc default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: rtc note: rsmrst# is sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by the ich5. bit description 7:6 swsmi_rate_sel ? r/w. this field indicates when the swsmi timer will time out. valid values are: 00 = 1.5 ms 0.6 ms 01 = 16 ms 4 ms 10 = 32 ms 4 ms 11 = 64 ms 4 ms 5:4 slp_s4# minimum assertion width ? r/w. this field indicates the minimum assertion width of the slp_s4# signal to guarantee that the drams have been safely power-cycled. valid values are: 11 = 1 to 2 seconds 10 = 2 to 3 seconds 01 = 3 to 4 seconds 00 = 4 to 5 seconds this value is used in two ways: 1. if the slp_s4# assertion width is ever shorter than this time, a status bit is set for bios to read when s0 is entered. 2. if enabled by bit 3 in this register, the hardware will prevent the slp_s4# signal from deasserting within this minimum time period after asserting. rtcrst# forces this field to the conservative default state (00b). 3 slp_s4# assertion stretch enable ? rw. 1 = the slp_s4# signal minimally assert for the time specified in bits 5:4 of this register. 0 = the slp_s4# minimum assertion time is 1 to 2 rtcclk. this bit is cleared by rtcrst#. 2 rtc_pwr_stsrtc power status (rtc_pwr_sts) ? r/w. this bit is set when rtcrst# indicates a weak or missing battery. the bit is not cleared by any type of reset. when the system boots, bios can detect that the freq_strap register contents are 1111 (the default when rtcrst# has been low). if this bit is also set, then bios knows the rtc battery had been removed. in that case, bios should take steps to reprogram the freq_strap register with the correct value, and then reboot the system. 1 power failure (pwr_flr) ? r/wc. this bit is in the rtc well, and is not cleared by any type of reset except rtcrst#. 0 = indicates that the trickle current has not failed since the last time the bit was cleared. software clears this bit by writing a 1 to it. 1 = indicates that the trickle current (from the main battery or trickle supply) was removed or failed. note: clearing cmos in an ich-based platform can be done by using a jumper on rtcrst# or gpi, or using safemode strap. implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. 0 afterg3_en ? r/w. this bit determines what state to go to when power is re-applied after a power failure (g3 state). this bit is in the rtc well and is not cleared by any type of reset except writes to cf9h or rtcrst#. 0 = system will return to s0 state (boot) after power is re-applied. 1 = system will return to the s5 state (except if it was in s4, in which case it will return to s4). in the s5 state, the only enabled wake event is the power button or any enabled wake event that was preserved through the power failure. 380 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.8.4 stpclk_del?stop clock delay register (pm?d31:f0) offset address: a8h attribute: r/w default value: 0dh size: 8-bit power well: core usage: acpi legacy 9.8.5 usb_tdd?usb transient disconnect detect (pm?d31:f0) offset address: adh attribute: r/w default value: 00h size: 8-bit power well: resume 9.8.6 sata_rd_cfg?sata raid configuration (pm?d31:f0) - (intel ? 82801er ich5r only) offset address: aeh attribute: r/w default value: c0h size: 8-bit power well: resume usage: ich5r only bit description 7:6 reserved 5:0 stpclk_del ? r/w. this field selects the value for t190 (cpuslp# inactive to stpclk# inactive). the default value of 0dh yields a default of approximately 50.045 microseconds. the maximum value of 3fh will result in a time of 245 microseconds. note: software must program the value to a range that can be tolerated by the associated processor and chipset. the intel ? ich5 requires that software does not program a value of 00h or 01h; a minimum programming of 02h yields the minimum possible delay of 3.87 microseconds. bit description 7:2 reserved 1:0 transient disconnect detect (tdd) ? r/w. this field prevents a short single-ended zero (se0) condition on the usb ports from being interrupted by the uhci host controller as a disconnect. bios should set this field to 11b. bit description 7:6 integrated sata raid configuration (raid_cfg) ? r/w. when cleared, intel ? raid technology is disabled. these bits are reset by the assertion of the rsmrst# pin. these bits are not reset when returning from s3. 00 = intel raid technology disabled 11 = intel raid technology enabled (default) 5:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 381 lpc interface bridge registers (d31:f0) 9.8.7 gpi_rout?gpi routing control register (pm?d31:f0) offset address: b8h ? bbh attribute: r/w default value: 0000h size: 32-bit lockable: no power well: resume note: gpios that are not implemented will not have the corresponding bits implemented in this register. bit description 31:30 gpi15 route ? r/w. see bits 1:0 for description. same pattern for gpi14 through gpi3 5:4 gpi2 route ? r/w. see bits 1:0 for description. 3:2 gpi1 route ? r/w. see bits 1:0 for description. 1:0 gpi0 route ? r/w. gpio[15:0] can be routed to cause an smi or sci when the gpi[n]_sts bit is set. if the gpio is not set to an input, this field has no effect. if the system is in an s1?s5 state and if the gpe0_en bit is also set, then the gpi can cause a wake event, even if the gpi is not routed to cause an smi# or sci. 00 = no effect. 01 = smi# (if corresponding alt_gpi_smi_en bit is also set) 10 = sci (if corresponding gpe0_en bit is also set) 11 = reserved 382 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.8.8 trp_fwd_en?io monitor trap forwarding enable register (pm?d31:f0) offset address: c0h attribute: r/w (special) default value: 00h size: 8 bits lockable: no usage: legacy only power well: core the ich5 uses this register to enable the monitors to forward cycles to lpc, independent of the pos_dec_en bit and the bits that enable the monitor to generate an smi#. the only criteria is that the address passes the decoding logic as determined by the mon[ n ]_trp_rng and mon_trp_msk register settings. bit description 7 mon7_fwd_en ? r/w. 0 = disable. cycles trapped by i/o monitor 7 will not be forwarded to lpc. 1 = enable. cycles trapped by i/o monitor 7 will be forwarded to lpc. 6 mon6_fwd_en ? r/w. 0 = disable. cycles trapped by i/o monitor 6 will not be forwarded to lpc. 1 = enable. cycles trapped by i/o monitor 6 will be forwarded to lpc. 5 mon5_fwd_en ? r/w. 0 = disable. cycles trapped by i/o monitor 5 will not be forwarded to lpc. 1 = enable. cycles trapped by i/o monitor 5 will be forwarded to lpc. 4 mon4_fwd_en ? r/w. 0 = disable. cycles trapped by i/o monitor 4 will not be forwarded to lpc. 1 = enable. cycles trapped by i/o monitor 4 will be forwarded to lpc. 3:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 383 lpc interface bridge registers (d31:f0) 9.8.9 mon[ n ]_trp_rng?i/o monitor [4:7] trap range register for devices 4?7 (pm?d31:f0) offset address: c4h, c6h, c8h, cah attribute: r/w default value: 00h size: 16 bits lockable: no usage: legacy only power well: core these registers set the ranges that device monitors 4 ? 7 should trap. offset 4ch corresponds to monitor 4. offset c6h corresponds to monitor 5, etc. if the trap is enabled in the mon_smi register and the address is in the trap range (and passes the mask set in the mon_trp_msk register), the ich5 will generate an smi#. this smi# occurs if the address is positively decoded by another device on pci or by the ich5 (because it would be forwarded to lpc or some other ich5 internal registers). the trap ranges should not point to registers in the ich5?s internal ide, usb, ac ?97 or lan i/o space. if the cycle is to be claimed by the ich5 and targets one of the permitted ich5 internal registers (interrupt controller, rtc, etc.), the cycle will complete to the intended target and an smi# will be generated (this is the same functionality as the ich component). if the cycle is to be claimed by the ich5 and the intended target is on lpc, an smi# will be generated but the cycle will only be forwarded to the intended target if forwarding to lpc is enabled via the trp_fwd_en register settings. 9.8.10 mon_trp_msk?i/o monitor trap range mask register for devices 4?7 (pm?d31:f0) offset address: cch attribute: r/w default value: 00h size: 16 bits lockable: no usage: legacy only power well: core bit description 15:0 mon[ n ]_trap_base ? r/w. base i/o locations that mon[ n ] traps (where n = 4, 5, 6 or 7). the range can be mapped anywhere in the processor i/o space (0?64 kb). any access to the range will generate an smi# if enabled by the associated dev[ n ]_trap_en bit in the mon_smi register (pmbase +40h). bit description 15:12 mon7_mask ? r/w. this field selects low 4?bit mask for the i/o locations that mon7 will trap. similar to mon4_mask. 11:8 mon6_mask ? r/w. this field selects low 4?bit mask for the i/o locations that mon6 will trap. similar to mon4_mask. 7:4 mon5_mask ? r/w. this field selects low 4?bit mask for the i/o locations that mon5 will trap. similar to mon4_mask. 3:0 mon4_mask ? r/w. this field selects low 4?bit mask for the i/o locations that mon7 will trap. when a mask bit is set to a 1, the corresponding bit in the base i/o selection will not be decoded. for example, if mon4_trap_base = 1230h, and mon4_msk = 0011b, the intel ? ich5 will decode 1230h, 1231h, 1232h, and 1233h for monitor 4. 384 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.9 apm i/o decode table 150 shows the i/o registers associated with apm support. this register space is enabled in the pci device 31: function 0 space (apmdec_en), and cannot be moved (fixed i/o location). 9.9.1 apm_cnt?advanced power management control port register i/o address: b2h attribute: r/w default value: 00h size: 8-bit lockable: no usage: legacy only power well: core 9.9.2 apm_sts?advanced power management status port register i/o address: b3h attribute: r/w default value: 00h size: 8-bit lockable: no usage: legacy only power well: core table 150. apm register map address mnemonic register name default type b2h apm_cnt advanced power management control port 00h r/w b3h apm_sts advanced power management status port 00h r/w bit description 7:0 used to pass an apm command between the os and the smi handler. writes to this port not only store data in the apmc register, but also generate an smi# when the apmc_en bit is set. bit description 7:0 used to pass data between the os and the smi handler. basically, this is a scratchpad register and is not affected by any other register or function (other than a pci reset). intel ? 82801eb ich5 / 82801er ich5r datasheet 385 lpc interface bridge registers (d31:f0) 9.10 power management i/o registers table 151 shows the registers associated with acpi and legacy power management support. these registers are enabled in the pci device 31: function 0 space (pm_io_en), and can be moved to any i/o location (128-byte aligned). the registers are defined to be compliant with the advanced configuration and power interface, version 2.0b, and use the same bit names. note: all reserved bits and registers will always return 0 when read, and will have no effect when written. table 151. acpi and legacy i/o register map pmbase + offset mnemonic register name acpi pointer default type 00?01h pm1_sts pm1 status pm1a_evt_blk 0000h r/wc 02?03h pm1_en pm1 enable pm1a_evt_blk+2 0000h r/w 04?07h pm1_cnt pm1 control pm1a_cnt_blk 00000000h r/w, wo 08?0bh pm1_tmr pm1 timer pmtmr_blk 00000000h ro 0c?0fh ? reserved ? ? ? 10h?13h proc_cnt processor control p_blk 00000000h r/w, ro, wo 14h?16h ? reserved ? ? ? 17?1fh ? reserved ? ? ? 20h ? reserved ? ? ? 28?2bh gpe0_sts general purpose event 0 status gpe0_blk 00000000h r/w, r/wc 2c?2fh gpe0_en general purpose event 0 enables gpe0_blk+4 00000000h r/w 30?33h smi_en smi# control and enable 0000h r/w, wo, r/w (special) 34?37h smi_sts smi status 0000h r/wc, ro 38?39h alt_gp_smi_en alternate gpi smi enable 0000h r/w 3a?3bh alt_gp_smi_sts alternate gpi smi status 0000h r/wc 3c?3fh ? reserved ? ? ? 40h mon_smi monitor smi status 0000h r/w, r/wc 42h?43h reserved 44h devact_sts device activity status 0000h r/wc 48h devtrap_en device trap enable 0000h r/w 50h ? reserved ? ? ? 51h?5fh ? reserved ? ? ? 60h?7fh ? reserved for tco ? ? ? 386 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.10.1 pm1_sts?power management 1 status register i/o address: pmbase + 00h ( acpi pm1a_evt_blk ) attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 15: resume, except bit 11 in rtc if bit 10 or 8 in this register is set, and the corresponding _en bit is set in the pm1_en register, then the ich5 will generate a wake event. once back in an s0 state (or if already in an s0 state when the event occurs), the ich5 will also generate an sci if the sci_en bit is set, or an smi# if the sci_en bit is not set. note: bit 5 does not cause an smi# or a wake event. bit 0 does not cause a wake event but can cause an smi# or sci. bit description 15 wake status (wak_sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the system is in one of the sleep states (via the slp_en bit) and an enabled wake event occurs. upon setting this bit, the intel ? ich5 will transition the system to the on state. if the afterg3_en bit is not set and a power failure occurs without the slp_en bit set, the system will return to an s0 state when power returns, and the wak_sts bit will not be set. if the afterg3_en bit is set and a power failure occurs without the slp_en bit having been set, the system will go into an s5 state when power returns, and a subsequent wake event will cause the wak_sts bit to be set. note that any subsequent wake event would have to be caused by either a power button press, or an enabled wake event that was preserved through the power failure (enable bit in the rtc well). 14:12 reserved 11 power button override status (prbtnor_sts) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a power button override occurs (i.e., the power button is pressed for at least 4 consecutive seconds), or due to the corresponding bit in the smbus slave message. the power button override causes an unconditional transition to the s5 state, as well as sets the afterg# bit. the bios or sci handler clears this bit by writing a 1 to it. this bit is not affected by hard resets via cf9h writes, and is not reset by rsmrst#. thus, this bit is preserved through power failures. 10 rtc status (rtc_sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the rtc generates an alarm (assertion of the irq8# signal). additionally if the rtc_en bit is set, the setting of the rtc_sts bit will generate a wake event. 9 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 387 lpc interface bridge registers (d31:f0) 8 power button status ( pwrbtn__sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 write. 0 = if the pwrbtn# signal is held low for more than 4 seconds, the hardware clears the pwrbtn_sts bit, sets the pwrbtnor_sts bit, and the system transitions to the s5 state with only pwrbtn# enabled as a wake event. this bit can be cleared by software by writing a one to the bit position. 1 = this bit is set by hardware when the pwrbtn# signal is asserted low, independent of any other enable bit. in the s0 state, while pwrbtn_en and pwrbtn_sts are both set, an sci (or smi# if sci_en is not set) will be generated. in any sleeping state s1?s5, while pwrbtn_en and pwrbtn_sts are both set, a wake event is generated. 7:6 reserved 5 global status (gbl _sts) ? r/wc. 0 = the sci handler should then clear this bit by writing a 1 to the bit location. 1 = set when an sci is generated due to bios wanting the attention of the sci handler. bios has a corresponding bit, bios_rls, which will cause an sci and set this bit. 4 reserved 3:1 reserved 0 timer overflow status (tmrof_sts) ? r/wc. 0 = the sci or smi# handler clears this bit by writing a 1 to the bit location. 1 = this bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). this will occur every 2.3435 seconds. when the tmrof_en bit is set, then the setting of the tmrof_sts bit will additionally generate an sci or smi# (depending on the sci_en). bit description 388 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.10.2 pm1_en?power management 1 enable register i/o address: pmbase + 02h ( acpi pm1a_evt_blk + 2 ) attribute: r/w default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 9, 11 ? 15: resume, bit 10: rtc bit description 15:11 reserved 10 rtc event enable (rtc_en) ? r/w. this bit is in the rtc well to allow an rtc event to wake after a power failure. this bit is not cleared by any reset other than rtcrst# or a power button override event. 0 = no sci (or smi#) or wake event is generated then rtc_sts goes active. 1 = an sci (or smi#) or wake event will occur when this bit is set and the rtc_sts bit goes active. 9 reserved. 8 power button enable (pwrbtn_en) ? r/w. this bit is used to enable the setting of the pwrbtn_sts bit to generate a power management event (smi#, sci). pwrbtn_en has no effect on the pwrbtn_sts bit being set by the assertion of the power button. the power button is always enabled as a wake event. 0 = disable 1 = enable 7:6 reserved. 5 global enable (gbl_en) ? r/w. when both the gbl_en and the gbl_sts are set, an sci is raised. 0 = disable 1 = enable sci on gbl_sts going active. 4:1 reserved. 0 timer overflow interrupt enable (tmrof_en) ? r/w. works in conjunction with the sci_en bit as described below: tmrof_en sci_en effect when tmrof_sts is set 0 x no smi# or sci 1 0 smi# 1 1 sci intel ? 82801eb ich5 / 82801er ich5r datasheet 389 lpc interface bridge registers (d31:f0) 9.10.3 pm1_cnt?power management 1 control i/o address: pmbase + 04h ( acpi pm1a_cnt_blk ) attribute: r/w, wo default value: 0000h size: 32-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 12: rtc, bits 13 ? 15: resume bit description 15:14 reserved. 13 sleep enable ( slp_en) ? wo. setting this bit causes the system to sequence into the sleep state defined by the slp_typ field. 12:10 sleep type (slp_typ) ? r/w. this 3-bit field defines the type of sleep the system should enter when the slp_en bit is set to 1. these bits are only reset by rtcrst#. 000 = on: typically maps to s0 state. 001 = it asserts stpclk#. puts processor in stop-grant state. optional to assert cpuslp# to put processor in sleep state: typically maps to s1 state. 010 = reserved 011 = reserved 100 = reserved 101 = suspend-to-ram. assert slp_s3#: typically maps to s3 state. 110 = suspend-to-disk. assert slp_s3# and slp_s4#: typically maps to s4 state. 111 = soft off. assert slp_s3#, slp_s4#, and slp_s5#: typically maps to s5 state. 9:3 reserved. 2 global release (gbl_rls) ? wo. 0 = this bit always reads as 0. 1 = acpi software writes a 1 to this bit to raise an event to the bios. bios software has a corresponding enable and status bits to control its ability to receive acpi events. 1 reserved 0 sci enable ( sci_en) ? r/w. selects the sci interrupt or the smi# interrupt for various events including the bits in the pm1_sts register (bit 10, 8, 0), and bits in gpe0_sts. 0 = these events will generate an smi#. 1 = these events will generate an sci. 390 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.10.4 pm1_tmr?power management 1 timer register i/o address: pmbase + 08h ( acpi pmtmr_blk ) attribute: ro default value: xx000000h size: 32-bit lockable: no usage: acpi power well: core 9.10.5 proc_cnt?processor control register i/o address: pmbase + 10h ( acpi p_blk ) attribute: r/w, ro, wo default value: 00000000h size: 32-bit lockable: no (bits 7:5 are write once) usage: acpi or legacy power well: core bit description 31:24 reserved 23:0 timer value (tmr_val) ? ro. returns the running count of the pm timer. this counter runs off a 3.579545 mhz clock (14.31818 mhz divided by 4). it is reset to 0 during a pci reset, and then continues counting as long as the system is in the s0 state. anytime bit 22 of the timer goes high to low (bits referenced from 0 to 23), the tmrof_sts bit is set. the high-to-low transition will occur every 2.3435 seconds. if the tmrof_en bit is set, an sci interrupt is also generated. bit description 31:18 reserved 17 throttle status (thtl_sts) ? ro. 0 = no clock throttling is occurring (maximum processor performance). 1 = indicates that the clock state machine is in some type of low power state (where the processor is not running at its maximum performance): thermal throttling or hardware throttling. 16:9 reserved 8 force thermal throttling (force_thtl) ? r/w. software can set this bit to force the thermal throttling function. this has the same effect as the thrm# signal being active for 2 seconds. 0 = no forced throttling. 1 = throttling at the duty cycle specified in thrm_dty starts immediately (no 2 second delay), and no smi# is generated. intel ? 82801eb ich5 / 82801er ich5r datasheet 391 lpc interface bridge registers (d31:f0) 7:5 thrm_dty ? wo. this write-once field determines the duty cycle of the throttling when the thermal override condition occurs. the duty cycle indicates the approximate percentage of time the stpclk# signal is asserted while in the throttle mode. the stpclk# throttle period is 1024 pciclks. note that the throttling only occurs if the system is in the c0 state. there is no enable bit for thermal throttling, because it should not be disabled. once the thrm_dty field is written, any subsequent writes will have no effect until pcirst# goes active. thrm_dty throttle mode pci clocks 000 50% (default) 512 001 87.5% 896 010 75.0% 768 011 62.5% 640 100 50% 512 101 37.5% 384 110 25% 256 111 12.5% 128 4 thtl_en ? r/w. when set and the system is in a c0 state, it enables a processor-controlled stpclk# throttling. the duty cycle is selected in the thtl_dty field. 0 = disable 1 = enable 3:1 thtl_dty ? r/w. this field determines the duty cycle of the throttling when the thtl_en bit is set. the duty cycle indicates the approximate percentage of time the stpclk# signal is asserted (low) while in the throttle mode. the stpclk# throttle period is 1024 pciclks. thtl_dty throttle mode pci clocks 000 50% (default) 512 001 87.5% 896 010 75.0% 768 011 62.5% 640 100 50% 512 101 37.5% 384 110 25% 256 111 12.5% 128 0 reserved bit description 392 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.10.6 gpe0_sts?general purpose event 0 status register i/o address: pmbase + 28h ( acpi gpe0_blk ) attribute: r/w, r/wc default value: 00000000h size: 32-bit lockable: no usage: acpi power well: resume this register is symmetrical to the general purpose event 0 enable register. if the corresponding _en bit is set, then when the _sts bit get set, the ich5 will generate a wake event. once back in an s0 state (or if already in an s0 state when the event occurs), the ich5 will also generate an sci if the sci_en bit is set, or an smi# if the sci_en bit is not set. there will be no sci/smi# or wake event on thrmor_sts since there is no corresponding _en bit. none of these bits are reset by cf9h write. all are reset by rsmrst#. bit description 31:16 gpin_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = these bits are set any time the corresponding gpio is set up as an input and the corresponding gpio signal is high (or low if the corresponding gp_inv bit is set). if the corresponding enable bit is set in the gpe0_en register, then when the gpi[n]_sts bit is set: ? if the system is in an s1?s5 state, the event will also wake the system. ? if the system is in an s0 state (or upon waking back to an s0 state), a sci will be caused depending on the gpi_rout bits for the corresponding gpi. 15 reserved 14 usb4_sts ? r/w. 0 = disable 1 = set by hardware and can be reset by writing a 1 to this bit position or a resume-well reset. this bit is set when usb uhci controller #4 needs to cause a wake. additionally if the usb4_en bit is set, the setting of the usb4_sts bit will generate a wake event. 13 pme_b0_sts ? r/w. this bit will be set to 1 by the intel ? ich5 when any internal device with pci power management capabilities on bus 0 asserts the equivalent of the pme# signal. additionally, if the pme_b0_en bit is set, and the system is in an s0 state, then the setting of the pme_b0_sts bit will generate an sci (or smi# if sci_en is not set). if the pme_b0_sts bit is set, and the system is in an s1?s4 state (or s5 state due to slp_typ and slp_en), then the setting of the pme_b0_sts bit will generate a wake event, and an sci (or smi# if sci_en is not set) will be generated. if the system is in an s5 state due to power button override, then the pme_b0_sts bit will not cause a wake event or sci. the default for this bit is 0. writing a 1 to this bit position clears this bit. 12 usb3_sts ? r/w. 0 = disable 1 = set by hardware and can be reset by writing a 1 to this bit position or a resume-well reset. this bit is set when usb uhci controller #3 needs to cause a wake. additionally if the usb3_en bit is set, the setting of the usb3_sts bit will generate a wake event. 11 pme_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the pme# signal goes active. additionally, if the pme_en bit is set, and the system is in an s0 state, then the setting of the pme_sts bit will generate an sci or smi# (if sci_en is not set). if the pme_en bit is set, and the system is in an s1?s4 state (or s5 state due to setting slp_typ and slp_en), then the setting of the pme_sts bit will generate a wake event, and an sci will be generated. if the system is in an s5 state due to power button override or a power failure, then pme_sts will not cause a wake event or sci. 10:9 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 393 lpc interface bridge registers (d31:f0) 8 ri_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the ri# input signal goes active. 7 smbus wake status (smb_wak_sts) ? r/wc. the smbus controller can independently cause an smi# or sci, so this bit does not need to do so (unlike the other bits in this register). software clears this bit by writing a 1 to it. 0 = wake event not caused by the ich5?s smbus logic. 1 = set by hardware to indicate that the wake event was caused by the ich5?s smbus logic.this bit will be set by the wake/smi# command type, even if the system is already awake. the smi handler should then clear this bit. notes: 1. this bit is set by the smbus slave command 01h (wake/smi#) even when the system is in the s0 state. therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the wake/smi# command or just prior to entering the sleep state. 2. if smb_wak_sts is set due to smbus slave receiving a message, it will be cleared by internal logic when a thrmtrip# event happens or a power button override event. however, thrmtrip# or power button override event will not clear smb_wak_sts if it is set due to smbalert# signal going active. 3. the smbalert_sts bit (d31:f3:i/o offset 00h:bit 5) should be cleared by software before the smb_wak_sts bit is cleared. 6 tcosci_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = toc logic did not cause sci. 1 = set by hardware when the tco logic causes an sci. 5 ac97_sts ? r/wc. this bit will be set to 1 when the codecs are attempting to wake the system and the pme events for the codecs are armed for wakeup. a pme is armed by programming the appropriate pmee bit in the power management control and status register at bit 8 of offset 54h in each ac?97 function. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the codecs are attempting to wake the system. the ac97_sts bit gets set only from the following two cases: 1.the pmee bit for the function is set, and o the ac-link bit clock has been shut and the routed ac_sdin line is high (for audio, if routing is disabled, no wake events are allowed. 2.for modem, if audio routing is disabled, then the wake event is an or of all ac_sdin lines. if routing is enabled, then the wake event for modem is the remaining non-routed ac_sdin line), or o gpi status change interrupt bit (nabmbar + 30h, bit 0) is 1. note: this bit is not affected by a hard reset caused by a cf9h write. 4 usb2_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = usb uhci controller 2 does not need to cause a wake. 1 = set by hardware when usb uhci controller 2 needs to cause a wake. wake event will be generated if the corresponding usb2_en bit is set. 3 usb1_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = usb uhci controller 1 does not need to cause a wake. 1 = set by hardware when usb uhci controller 1 needs to cause a wake. wake event will be generated if the corresponding usb1_en bit is set. bit description 394 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.10.7 gpe0_en?general purpose event 0 enables register i/o address: pmbase + 2ch ( acpi gpe0_blk + 4 ) attribute: r/w default value: 00000000h size: 32-bit lockable: no usage: acpi power well: bits 0 ? 7, 12, 16 ? 31 resume, bits 8 ? 11, 13 ? 15 rtc this register is symmetrical to the general purpose event 0 status register. all the bits in this register should be cleared to 0 based on a power button override or processor thermal trip event. the resume well bits are all cleared by rsmrst#. the rtc sell bits are cleared by rtcrst#. 2 reserved 1 thermal interrupt override status ( thrmor_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = thermal over-ride condition did not occur and start throttling the processor?s clock at the thrm_dty ratio 1 = this bit is set by hardware anytime a thermal over-ride condition occurs and starts throttling the processor?s clock at the thrm_dty ratio. this will not cause an smi#, sci, or wake event. 0 thermal interrupt status (thrm_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = thrm# signal not driven active as defined by the thrm_pol bit 1 = set by hardware anytime the thrm# signal is driven active as defined by the thrm_pol bit. additionally, if the thrm_en bit is set, then the setting of the thrm_sts bit will also generate a power management event (sci or smi#). bit description bit description 31:16 gpin_en ? r/w. these bits enable the corresponding gpi[n]_sts bits being set to cause a sci, and/or wake event. these bits are cleared by rsmrst#. 15 reserved 14 usb4_en ? r/w. 0 = disable 1 = enable the setting of the usb4_sts bit to generate a wake event. the usb4_sts bit is set anytime usb uhci controller #4 signals a wake event. break events are handled via the usb interrupt. 13 pme_b0_en ? r/w. 0 = disable 1 = enables the setting of the pme_b0_sts bit to generate a wake event and/or an sci or smi#. pme_b0_sts can be a wake event from the s1?s4 states, or from s5 (if entered via slp_typ and slp_en) or power failure, but not power button override. this bit defaults to 0. note: it is only cleared by software or rtcrst#. it is not cleared by cf9h writes. 12 usb3_en ? r/w. 0 = disable 1 = enable the setting of the usb3_sts bit to generate a wake event. the usb3_sts bit is set anytime usb uhci controller #3 signals a wake event. break events are handled via the usb interrupt. intel ? 82801eb ich5 / 82801er ich5r datasheet 395 lpc interface bridge registers (d31:f0) 11 pme_en ? r/w. 0 = disable 1 = enables the setting of the pme_sts to generate a wake event and/or an sci. pme# can be a wake event from the s1 ? s4 state or from s5 (if entered via slp_en, but not power button override). 10 reserved 9 reserved 8 ri_en ? r/w. the value of this bit will be maintained through a g3 state and is not affected by a hard reset caused by a cf9h write. 0 = disable 1 = enables the setting of the ri_sts to generate a wake event. 7 reserved 6 tcosci_en ? r/w. 0 = disable 1 = enables the setting of the tcosci_sts to generate an sci. 5 ac97_en ? r/w. 0 = disable 1 = enables the setting of the ac97_sts to generate a wake event. 4 usb2_en ? r/w. 0 = disable 1 = enables the setting of the usb2_sts to generate a wake event. 3 usb1_en ? r/w. 0 = disable 1 = enables the setting of the usb1_sts to generate a wake event. 2 thrm#_pol ? r/w. this bit controls the polarity of the thrm# pin needed to set the thrm_sts bit. 0 = low value on the thrm# signal will set the thrm_sts bit. 1 = high value on the thrm# signal will set the thrm_sts bit. 1 reserved 0 thrm_en ? r/w. 0 = disable 1 = active assertion of the thrm# signal (as defined by the thrm_pol bit) will set the thrm_sts bit and generate a power management event (sci or smi). bit description 396 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.10.8 smi_en?smi control and enable register i/o address: pmbase + 30h attribute: r/w, r/w (special), wo default value: 0000h size: 32 bit lockable: no usage: acpi or legacy power well: core bit description 31:19 reserved 18 intel_usb2_en ? r/w. 0 = disable 1 = enables intel-specific usb2 smi logic to cause smi#. 17 legacy_usb2_en ? r/w. 0 = disable 1 = enables legacy usb2 logic to cause smi#. 16:15 reserved 14 periodic_en ? r/w. 0 = disable 1 = enables the intel ? ich5 to generate an smi# when the periodic_sts bit is set in the smi_sts register. 13 tco_en ? r/w. 0 = disables tco logic generating an smi#. note that if the nmi2smi_en bit is set, smis that are caused by re-routed nmis will not be gated by the tco_en bit. even if the tco_en bit is 0, nmis will still be routed to cause smis. 1 = enables the tco logic to generate smi#. note: this bit cannot be written once the tco_lock bit is set. 12 reserved 11 mcsmi_enmicrocontroller smi enable (mcsmi_en) ? r/w. 0 = disable 1 = enables ich5 to trap accesses to the microcontroller range (62h or 66h) and generate an smi#. note that ?trapped? cycles will be claimed by the ich5 on pci, but not forwarded to lpc. 10:8 reserved 7 bios release (bios_rls) ? wo. 0 = this bit will always return 0 on reads. writes of 0 to this bit have no effect. 1 = enables the generation of an sci interrupt for acpi software when a 1 is written to this bit position by bios software. 6 software smi# timer enable (swsmi_tmr_en) ? r/w. 0 = disable. clearing the swsmi_tmr_en bit before the timer expires will reset the timer and the smi# will not be generated. 1 = starts software smi# timer. when the swsmi timer expires (the timeout period depends upon the swsmi_rate_sel bit setting), swsmi_tmr_sts is set and an smi# is generated. swsmi_tmr_en stays set until cleared by software. 5 apmc_en ? r/w. 0 = disable. writes to the apm_cnt register will not cause an smi#. 1 = enables writes to the apm_cnt register to cause an smi#. 4 slp_smi_en ? r/w. 0 = disables the generation of smi# on slp_en. note that this bit must be 0 before the software attempts to transition the system into a sleep state by writing a 1 to the slp_en bit. 1 = a write of 1 to the slp_en bit (bit 13 in pm1_cnt register) will generate an smi#, and the system will not transition to the sleep state based on that write to the slp_en bit. intel ? 82801eb ich5 / 82801er ich5r datasheet 397 lpc interface bridge registers (d31:f0) 3 legacy_usb_en ? r/w. 0 = disable 1 = enables legacy usb circuit to cause smi#. 2 bios_en ? r/w. 0 = disable 1 = enables the generation of smi# when acpi software writes a 1 to the gbl_rls bit. 1 end of smi (eos) ? r/w (special). this bit controls the arbitration of the smi signal to the processor. this bit must be set for the intel ? ich5 to assert smi# low to the processor after smi# has been asserted previously. 0 = once the ich5 asserts smi# low, the eos bit is automatically cleared. 1 = when this bit is set to 1, smi# signal will be deasserted for 4 pci clocks before its assertion. in the smi handler, the processor should clear all pending smis (by servicing them and then clearing their respective status bits), set the eos bit, and exit smm. this will allow the smi arbiter to re-assert smi upon detection of an smi event and the setting of a smi status bit. note: ich5 is able to generate 1st smi after reset even though eos bit is not set. subsequent smi require eos bit is set. 0 gbl_smi_en ? r/w. 0 = no smi# will be generated by ich5. this bit is reset by a pci reset event. 1 = enables the generation of smi# in the system upon any enabled smi event. bit description 398 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.10.9 smi_sts?smi status register i/o address: pmbase + 34h attribute: ro, r/wc default value: 0000h size: 32-bit lockable: no usage: acpi or legacy power well: core note: if the corresponding _en bit is set when the _sts bit is set, the ich5 will cause an smi# (except bits 8 ? 10 and 12, which do not need enable bits since they are logic ors of other registers that have enable bits). the ich5 uses the same gpe0_en register (i/o address: pmbase+2ch) to enable/disable both smi and acpi sci general purpose input events. acpi os assumes that it owns the entire gpe0_en register per acpi spec. problems arise when some of the general- purpose inputs are enabled as smi by bios, and some of the general purpose inputs are enabled for sci. in this case acpi os turns off the enabled bit for any gpix input signals that are not indicated as sci general-purpose events at boot, and exit from sleeping states. bios should define a dummy control method which prevents the acpi os from clearing the smi gpe0_en bits. bit description 31:19 reserved 18 intel_usb2_sts ? ro. this non-sticky read-only bit is a logical or of each of the smi status bits in the intel-specific usb2 smi status register anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. writes to this bit will have no effect. 17 legacy_usb2_sts ? ro. this non-sticky read-only bit is a logical or of each of the smi status bits in the usb2 legacy support register anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. writes to this bit will have no effect. 16 smbus smi status (smbus_smi_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = this bit is set from the 64 khz clock domain used by the smbus. software must wait at least 15.63 us after the initial assertion of this bit before clearing it. 1 = indicates that the smi# was caused by: 1. the smbus slave receiving a message, or 2. the smbalert# signal goes active and the smb_smi_en bit is set and the smbalert_dis bit is cleared, or 3. the smbus slave receiving a host notify message and the host_notify_intren and the smb_smi_en bits are set, or 4. the intel ? ich5 detecting the smlink_slave_smi command while in the s0 state. 15 serirq_smi_sts ? ro. 0 = smi# was not caused by the serirq decoder. this is not a sticky bit. 1 = indicates that the smi# was caused by the serirq decoder. 14 periodic_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set at the rate determined by the per_smi_sel bits. if the periodic_en bit is also set, the ich5 generates an smi#. 13 tco_sts ? ro. 0 = smi# not caused by tco logic. 1 = indicates the smi# was caused by the tco logic. note that this is not a wake event. 12 device monitor status (devmon_sts) ? ro. 0 = smi# not caused by device monitor. 1 = set under any of the following conditions: ? any of the dev[7:4]_trap_sts bits are set and the corresponding dev[7:4]_trap_en bits are also set. ? any of the devtrap_sts bits are set and the corresponding devtrap_en bits are also set. intel ? 82801eb ich5 / 82801er ich5r datasheet 399 lpc interface bridge registers (d31:f0) 11 microcontroller smi# status ( mcsmi_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = indicates that there has been no access to the power management microcontroller range (62h or 66h). 1 = set if there has been an access to the power management microcontroller range (62h or 66h). if this bit is set, and the mcsmi_en bit is also set, the ich5 will generate an smi#. 10 gpe0_sts ? ro. this bit is a logical or of the bits in the alt_gp_smi_sts register that are also set up to cause an smi# (as indicated by the gpi_rout registers) and have the corresponding bit set in the alt_gp_smi_en register. bits that are not routed to cause an smi# will have no effect on this bit. 0 = smi# was not generated by a gpi assertion. 1 = smi# was generated by a gpi assertion. 9 gpe0_sts ? ro. this bit is a logical or of the bits in the gpe0_sts register that also have the corresponding bit set in the gpe0_en register. 0 = smi# was not generated by a gpe0 event. 1 = smi# was generated by a gpe0 event. 8 pm1_sts_reg ? ro. this is an ors of the bits in the acpi pm1 status register (offset pmbase+00h) that can cause an smi#. 0 = smi# was not generated by a pm1_sts event. 1 = smi# was generated by a pm1_sts event. 7 reserved 6 swsmi_tmr_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = software smi# timer has not expired. 1 = set by the hardware when the software smi# timer expires. 5 apm_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = no smi# generated by write access to apm control register with apmch_en bit set. 1 = smi# was generated by a write access to the apm control register with the apmc_en bit set. 4 slp_smi_sts ? r/wc. software clears this bit by writing a 1 to the bit location. 0 = no smi# caused by write of 1 to slp_en bit when slp_smi_en bit is also set. 1 = indicates an smi# was caused by a write of 1 to slp_en bit when slp_smi_en bit is also set. 3 legacy_usb_sts ? ro. this bit is a logical or of each of the smi status bits in the usb legacy keyboard/mouse control registers anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. 0 = smi# was not generated by usb legacy event. 1 = smi# was generated by usb legacy event. 2 bios_sts ? r/wc. 0 = no smi# generated due to acpi software requesting attention. 1 = smi# was generated due to acpi software requesting attention (writing a 1 to the gbl_rls bit with the bios_en bit set). 1:0 reserved bit description 400 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.10.10 alt_gp_smi_en?alternate gpi smi enable register i/o address: pmbase +38h attribute: r/w default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: resume 9.10.11 alt_gp_smi_sts?alternate gpi smi status register i/o address: pmbase +3ah attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: resume 9.10.12 mon_smi?device monitor smi status and enable register i/o address: pmbase +40h attribute: r/w, r/wc default value: 0000h size: 16-bit lockable: no usage: legacy only power well: core bit description 15:0 alternate gpi smi enable ? r/w. these bits are used to enable the corresponding gpio to cause an smi#. for these bits to have any effect, the following must be true. ? the corresponding bit in the alt_gp_smi_en register is set. ? the corresponding gpi must be routed in the gpi_rout register to cause an smi. ? the corresponding gpio must be implemented. bit description 15:0 alternate gpi smi status ? r/wc. these bits report the status of the corresponding gpis. 0 = inactive. software clears this bit by writing a 1 to it. 1 = active these bits are sticky. if the following conditions are true, then an smi# will be generated and the gpe0_sts bit set: ? the corresponding bit in the alt_gpi_smi_en register is set ? the corresponding gpi must be routed in the gpi_rout register to cause an smi. ? the corresponding gpio must be implemented. all bits are in the resume well. default for these bits is dependent on the state of the gpi pins. bit description 15:12 dev[7:4]_trap_sts ? r/wc. bit 12 corresponds to monitor 4, bit 13 corresponds to monitor 5 etc. 0 = smi# was not caused by the associated device monitor. software clears this bit by writing a 1 to it. 1 = smi# was caused by an access to the corresponding device monitor?s i/o range. 11:8 dev[7:4]_trap_en ? r/w. bit 8 corresponds to monitor 4, bit 9 corresponds to monitor 5 etc. 0 = disable 1 = enables smi# due to an access to the corresponding device monitor?s i/o range. 7:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 401 lpc interface bridge registers (d31:f0) 9.10.13 devact_sts ? device activity status register i/o address: pmbase +44h attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: legacy only power well: core this register is used in conjunction with the periodic smi# timer to detect any system activity for legacy power management. note: software clears bits that are set in this register by writing a 1 to the bit position. bit description 15:13 reserved 12 kbc_act_sts ? r/wc. kbc (60/64h). 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. 11:10 reserved 9 pirqdh_act_sts ? r/wc. pirq[d or h]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 8 pirqcg_act_sts ? r/wc. pirq[c or g]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 7 pirqbf_act_sts ? r/wc. pirq[b or f]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 6 pirqae_act_sts ? r/wc. pirq[a or e]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active. clear this bit by writing a 1 to the bit location. 5 leg_act_sts ? r/wc. parallel port, serial port 1, serial port 2, floppy disk controller. 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. 4 reserved 3 ides1_act_sts ? r/wc. ide secondary drive 1. 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. 2 ides0_act_sts ? r/wc. ide secondary drive 0. 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. 1 idep1_act_sts ? r/wc. ide primary drive 1. 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. 0 idep0_act_sts ? r/wc. ide primary drive 0. 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. 402 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.10.14 devtrap_en?device trap enable register i/o address: pmbase +48h attribute: r/w default value 0000h size: 16-bit lockable: no usage: legacy only power well: core this register enables the individual trap ranges to generate an smi# when the corresponding status bit in the devact_sts register is set. when a range is enabled, i/o cycles associated with that range will not be forwarded to lpc or ide. bit description 15:13 reserved 12 kbc_trp_en ? r/w. kbc (60/64h). 0 = disable 1 = enable 11:10 reserved 9:6 reserved 5 leg_io_trp_en ? r/w. parallel port, serial port 1, serial port 2, floppy disk controller. 0 = disable 1 = enable 4 reserved 3 ides1_trp_en ? r/w. ide secondary drive 1. 0 = disable 1 = enable 2 ides0_trp_en ? r/w. ide secondary drive 0. 0 = disable 1 = enable 1 idep1_trp_en ? r/w. ide primary drive 1. 0 = disable 1 = enable 0 idep0_trp_en ? r/w. ide primary drive 0. 0 = disable 1 = enable intel ? 82801eb ich5 / 82801er ich5r datasheet 403 lpc interface bridge registers (d31:f0) 9.11 system management tco registers (d31:f0) the tco logic is accessed via registers mapped to the pci configuration space (device 31:function 0) and the system i/o space. for tco pci configuration registers, see lpc device 31:function 0 pci configuration registers. the tco i/o registers reside in a 32-byte range pointed to by a tcobase value, which is, acpibase + 60h in the pci config space. the following table shows the mapping of the registers within that 32-byte range. each register is described in the following sections. 9.11.1 tco_rld?tco timer reload and current value register i/o address: tcobase +00h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core table 152. tco i/o register address map offset mnemonic register name default type 00h tco_rld tco timer reload and current value 00h r/w 01h tco_tmr tco timer initial value 04h r/w 02h tco_dat_in tco data in 00h r/w 03h tco_dat_out tco data out 00h r/w 04h?05h tco1_sts tco1 status 0000h r/wc, ro 06h?07h tco2_sts tco2 status 0000h r/w, r/wc 08h?09h tco1_cnt tco1 control 0000h r/w, r/w (special), r/wc 0ah?0bh tco2_cnt tco2 control 0008h r/w 0ch?0dh tco_message1, tco_message2 tco message 1 and 2 00h r/w 0eh tco_wdsts watchdog status register 00h r/w 0fh ? reserved ? ? 10h sw_irq_gen software irq generation register 11h r/w 11h?1fh ? reserved ? ? bit description 7:0 tco timer value ? r/w. reading this register will return the current count of the tco timer. writing any value to this register will reload the timer to prevent the timeout. bits 7:6 will always be 0. 404 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.11.2 tco_tmr?tco timer initial value register i/o address: tcobase +01h attribute: r/w default value: 04h size: 8-bit lockable: no power well: core 9.11.3 tco_dat_in?tco data in register i/o address: tcobase +02h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core 9.11.4 tco_dat_out?tco data out register i/o address: tcobase +03h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core bit description 7:6 reserved 5:0 tco timer initial value ? r/w. this field provides the value that is loaded into the timer each time the tco_rld register is written. values of 0h?3h are ignored and should not be attempted. the timer is clocked at approximately 0.6 seconds, and this allows timeouts ranging from 2.4 seconds to 38 seconds. bit description 7:0 tco data in value ? r/w. this data register field is used for passing commands from the os to the smi handler. writes to this register will cause an smi and set the sw_tco_smi bit in the tco1_sts register. bit description 7:0 tco data out value ? r/w. this data register field is used for passing commands from the smi handler to the os. writes to this register will set the tco_int_sts bit in the tco_sts register. it will also cause an interrupt, as selected by the tco_int_sel bits. intel ? 82801eb ich5 / 82801er ich5r datasheet 405 lpc interface bridge registers (d31:f0) 9.11.5 tco1_sts?tco1 status register i/o address: tcobase +04h attribute: r/wc, ro default value: 0000h size: 16-bit lockable: no power well: core (except bit 7, in rtc) bit description 15:13 reserved 12 hubserr_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = intel ? ich5 received an serr# message via the hub interface. the software must read the memory controller hub (or its equivalent) to determine the reason for the serr#. note: if this bit is set and the serr_en bit in cmd register (d30:f0, offset 04h, bit 8) is also set, the ich5 will set the sse bit in secsts register (d30:f0, offset 1eh, bit 14) and will also generate a nmi (or smi# if nmi routed to smi#). 11 hubnmi_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = ich5 received an nmi message via the hub interface. the software must read the memory controller hub (or its equivalent) to determine the reason for the nmi. 10 hubsmi_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = ich5 received an smi message via the hub interface. the software must read the memory controller hub (or its equivalent) to determine the reason for the smi#. 9 hubsci_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = ich5 received an sci message via the hub interface. the software must read the memory controller hub (or its equivalent) to determine the reason for the sci. 8 bioswr_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = ich5 sets this bit and generates and smi# to indicate an illegal attempt to write to the bios. this occurs when either: a) the bioswp bit is changed from 0 to 1 and the bld bit is also set, or b) any write is attempted to the bios and the bioswp bit is also set. note: on write cycles attempted to the 4-mb lower alias to the bios space, the bioswr_sts will not be set. 7 newcentury_sts ? r/wc. this bit is in the rtc well. 0 = cleared by writing a 1 to the bit position or by rtcrst# going active. 1 = this bit is set when the year byte (rtc i/o space, index offset 09h) rolls over from 99 to 00. setting this bit will cause an smi# (but not a wake event). note that the newcentury_sts bit is not valid when the rtc battery is first installed (or when rtc power has not been maintained). software can determine if rtc power has not been maintained by checking the rtc_pwr_sts bit, or by other means (such as a checksum on rtc ram). if rtc power is determined to have not been maintained, bios should set the time to a legal value and then clear the newcentury_sts bit. the newcentury_sts bit may take up to 3 rtc clocks for the bit to be cleared after a 1 is written to the bit to clear it. after writing a 1 to this bit, software should not exit the smi handler until verifying that the bit has actually been cleared. this will ensure that the smi is not re-entered. 6:4 reserved 3 timeout ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by ich5 to indicate that the smi was caused by the tco timer reaching 0. 406 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.11.6 tco2_sts?tco2 status register i/o address: tcobase +06h attribute: r/wc default value: 0000h size: 16-bit lockable: no power well: resume (except bit 0, in rtc) 2 tco_int_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = smi handler caused the interrupt by writing to the tco_dat_out register. 1 sw_tco_smi ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = software caused an smi# by writing to the tco_dat_in register. 0 nmi2smi_sts ? ro. 0 = cleared by clearing the associated nmi status bit. 1 = set by the ich5 when an smi# occurs because an event occurred that would otherwise have caused an nmi (because nmi2smi_en is set). bit description bit description 15:5 reserved 4 smlink slave smi status (smlink_slv_smi_sts) ? r/wc. allow the software to go directly into pre-determined sleep state. this avoids race conditions. software clears this bit by writing a 1 to it. 0 = the bit is reset by rsmrst#, but not due to the pci reset associated with exit from s3?s5 states. 1 = intel ? ich5 sets this bit to 1 when it receives the smi message on the smlink's slave interface. 3 reserved 2 boot_sts ? r/wc. 0 = cleared by ich5 based on rsmrst# or by software writing a 1 to this bit. note that software should first clear the second_to_sts bit before writing a 1 to clear the boot_sts bit. 1 = set to 1 when the second_to_sts bit goes from 0 to 1 and the processor has not fetched the first instruction. if rebooting due to a second tco timer timeout, and if the boot_sts bit is set, the ich5 will reboot using the ?safe? multiplier (1111). this allows the system to recover from a processor fr equency multiplier that is too high, and allows the bios to check the boot_sts bit at boot. if the bit is set and the frequency multiplier is 1111, then the bios knows that the processor has been programmed to an illegal multiplier. 1 second_to_sts ? r/wc. 0 = software clears this bit by writing a 1 to it, or by a rsmrst#. 1 = the ich5 sets this bit to a 1 to indicate that the tco timer timed out a second time (probably due to system lock). if this bit is set and the no_reboot configuration bit is 0, then the ich5 will reboot the system after the second timeout. the reboot is done by asserting pcirst#. 0 intruder detect (intrd_det) ? r/wc. 0 = software clears this bit by writing a 1 to it, or by rtcrst# assertion. 1 = set by ich5 to indicate that an intrusion was detected. this bit is set even if the system is in g3 state. intel ? 82801eb ich5 / 82801er ich5r datasheet 407 lpc interface bridge registers (d31:f0) 9.11.7 tco1_cnt?tco1 control register i/o address: tcobase +08h attribute: r/w, r/w (special), r/wc default value: 0000h size: 16-bit lockable: no power well: core bit description 15:13 reserved 12 tco_lock ? r/w (special). when set to 1, this bit prevents writes from changing the tco_en bit (in offset 30h of power management i/o space). once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. a core-well reset is required to change this bit from 1 to 0. this bit defaults to 0. 11 tco timer halt (tco_tmr_hlt) ? r/w. 0 = the tco timer is enabled to count. 1 = the tco timer will halt. it will not count, and thus cannot reach a value that will cause an smi# or set the second_to_sts bit. when set, this bit will prevent rebooting and prevent alert on lan event messages from being transmitted on the smlink (but not alert on lan* heartbeat messages). 10 send_now ? r/w (special). 0 = the intel ? ich5 will clear this bit when it has completed sending the message. software must not set this bit to 1 again until the ich5 has set it back to 0. 1 = writing a 1 to this bit will cause the ich5 to send an alert on lan event message over the smlink interface, with the software event bit set. setting the send_now bit causes the ich5 integrated lan controller to reset, which can have unpredictable side-effects. unless software protects against these side effects, software should not attempt to set this bit. 9 nmi2smi_en ? r/w. 0 = normal nmi functionality. 1 = forces all nmis to instead cause smis. the functionality of this bit is dependent upon the settings of the nmi_en bit and the gbl_smi_en bit as detailed in the following table: nmi_en gbl_smi_en description 0 0 no smi# at all because gbl_smi_en = 0 0 1 smi# will be caused due to nmi events 1 0 no smi# at all because gbl_smi_en = 0 1 1 no smi# due to nmi because nmi_en = 1 8 nmi_now ? r/wc. 0 = software clears this bit by writing a 1 to it. the nmi handler is expected to clear this bit. another nmi will not be generated until the bit is cleared. 1 = writing a 1 to this bit causes an nmi. this allows the bios or smi handler to force an entry to the nmi handler. 7:0 reserved 408 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.11.8 tco2_cnt?tco2 control register i/o address: tcobase +0ah attribute: r/w default value: 0008h size: 16-bit lockable: no power well: resume 9.11.9 tco_message1 and tco_message2 registers i/o address: tcobase +0ch (message 1) attribute: r/w tcobase +0dh (message 2) default value: 00h size: 8-bit lockable: no power well: resume 9.11.10 tco_wdsts?tco watchdog status register offset address: tcobase + 0eh attribute: r/w default value: 00h size: 8 bits power well: resume bit description 15:4 reserved 3 gpio11_alert_disable ? r/w. at reset (via rsmrst# asserted) this bit is set and gpio11 alerts are disabled. 0 = enable 1 = disable gpio11/smbalert# as an alert source for the heartbeats and the smbus slave. 2:1 intrd_sel ? r/w. this field selects the action to take if the intruder# signal goes active. 00 = no interrupt or smi# 01 = interrupt (as selected by tco_int_sel). 10 = smi 11 = reserved 0 reserved bit description 7:0 tco_message[ n ] ? r/w. the value written into this register will be sent out via the smlink interface in the message field of the alert on lan message. bios can write to this register to indicate its boot progress which can be monitored externally. bit description 7:0 watchdog status (wdstatus) ? r/w. the value written to this register will be sent in the alert on lan message on the smlink interface. it can be used by the bios or system management software to indicate more details on the boot progress. this register will be reset to the default of 00h based on rsmrst# (but not pci reset). intel ? 82801eb ich5 / 82801er ich5r datasheet 409 lpc interface bridge registers (d31:f0) 9.11.11 sw_irq_gen?software irq generation register offset address: tcobase + 10h attribute: r/w default value: 11h size: 8 bits power well: core 9.12 general purpose i/o registers (d31:f0) the control for the general purpose i/o signals is handled through a separate 64-byte i/o space. the base offset for this space is selected by the gpio_bar register. bit description 7:2 reserved 1 irq12_cause ? r/w. the state of this bit is logically anded with the irq12 signal as received by the intel ? ich5?s serirq logic. this bit must be a 1 (default) if the ich5 is expected to receive irq12 assertions from a serirq device. 0 irq1_cause ? r/w. the state of this bit is logically anded with the irq1 signal as received by the ich5?s serirq logic. this bit must be a 1 (default) if the ich5 is expected to receive irq1 assertions from a serirq device. table 153. registers to control gpio address map offset mnemonic register name default access general registers 00?03h gpio_use_sel gpio use select 1a003180h r/w 04?07h gp_io_sel gpio input/output select 0000 ffffh r/w 08?0bh ? reserved ? ? 0c?0fh gp_lvl gpio level for input or output 1f1f 0000h r/w 10?13h reserved 00h ro output control registers 14?17h gpo_ttl gpio ttl select 06630000h ro 18?1bh gpo_blink gpio blink enable 00000000h r/w 1c?1fh ? reserved ? ? input control registers 20?2bh ? reserved ? ? 2c?2fh gpi_inv gpio signal invert 00000000h r/w 30?33h gpio_use_sel2 gpio use select 2 00000007h r/w 34?37h gp_io_sel2 gpio input/output select 2 00000300h r/w 38?3bh gp_lvl2 gpio level for input or output 2 00030207h r/w 410 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.12.1 gpio_use_sel?gpio use select register offset address: gpiobase + 00h attribute: r/w default value: 1a003180h size: 32-bit lockable: no power well: core for 0:7 and 16:23 resume for 8:15 and 24:31 9.12.2 gp_io_sel?gpio input/output select register offset address: gpiobase +04h attribute: r/w default value: 0000ffffh size: 32-bit lockable: no power well: resume bit description 23:21, 14:15, 11:9, 5:0 gpio_use_sel[23:21, 15:14, 11:9, 5:0] ? r/w. each bit in this register enables the corresponding gpio (if it exists) to be used as a gpio, rather than for the native function. 0 = signal used as native function. 1 = signal used as a gpio. note: bits 31:29, 26 are not implemented because there is no corresponding gpio. note: bits 28:27, 25, 13:12, and 8:7 are not implemented because the corresponding gpios are not multiplexed. note: bits 16:17 are not implemented because the gpio selection is controlled by bits 0:1. the req/gnt# pairs are enabled/disabled together. for example, if bit 0 is set to 1 then the req/gnta# pair will function as gpio0 and gpio16. after a full reset (rsmrst#) all multiplexed signals in the resume and core wells are configured as their native function rather than as a gpio. after just a pcirst#, the gpio in the core well are configured as their native function. bit description 31:29, 26 reserved 28:27 25:24 gpio[n]_sel ? r/w. 0 = output. the corresponding gpio signal is an output. 1 = input. the corresponding gpio signal is an input. 23:16 always 0. the gpios are fixed as outputs. 15:0 always 1. these gpios are fixed as inputs. intel ? 82801eb ich5 / 82801er ich5r datasheet 411 lpc interface bridge registers (d31:f0) 9.12.3 gp_lvl?gpio level for input or output register offset address: gpiobase +0ch attribute: r/w default value: 1b3f 0000h size: 32-bit lockable: no power well: see bit descriptions 9.12.4 gpo_blink?gpo blink enable register offset address: gpiobase +18h attribute: r/w default value: 0004 0000h size: 32-bit lockable: no power well: see bit description note: gpio18 will blink by default immediately after reset. this signal could be connected to an led to indicate a failed boot (by programming bios to clear gp_blink18 after successful post). bit description 31:29, 26 reserved 28:27, 25:24 gp_lvl[n] ? r/w. if gpion is programmed to be an output (via the corresponding bit in the gp_io_sel register) then the bit can be updated by software to drive a high or low value on the output pin. if gpion is programmed as an input, then software can read the bit to determine the level on the corresponding input pin. these bits correspond to gpio that are in the resume well, and will be reset to their default values by rsmrst# and also by a write to the cf9h register. 0 = low 1 = high 23:16 gp_lvl[n] ? r/w. these bits can be updated by software to drive a high or low value on the output pin. these bits correspond to gpio that are in the core well, and will be reset to their default values by pcirst#. 0 = low 1 = high 15:0 reserved. for gpi[13:11] and [8:0], the active status of a gpi is read from the corresponding bit in gpe0_sts register. bit description 31:29, 26, 24:20, 17:0 reserved 28:27, 25 gp_blink[n] ? r/w. the setting of these bits will have no effect if the corresponding gpio is programmed as an input. these bits correspond to gpio that are in the resume well, and will be reset to their default values by rsmrst# or by a write to the cf9h register. 0 = the corresponding gpio will function normally. 1 = if the corresponding gpio is programmed as an output, the output signal will blink at a rate of approximately once per second. the high and low times have approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. 19:18 gp_blink[n] ? r/w. the setting of these bits will have no effect if the corresponding gpio is programmed as an input. these bits correspond to gpio that are in the core well, and will be reset to their default values by pcirst#. 0 = the corresponding gpio will function normally. 1 = if the corresponding gpio is programmed as an output, the output signal will blink at a rate of approximately once per second. the high and low times are approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. 412 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.12.5 gpi_inv?gpio signal invert register offset address: gpiobase +2ch attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: see bit description 9.12.6 gpio_use_sel2?gpio use select 2 register offset address: gpiobase +30h attribute: r/w default value: 00000007h size: 32-bit lockable: no power well: core bit description 31:16 reserved 15:8 gp_inv[n] ? r/w. these bits are used to allow both active-low and active-high inputs to cause smi# or sci. note that in the s0 or s1 state, the input signal must be active for at least 2 pci clocks to ensure detection by the intel ? ich5. in the s3, s4 or s5 states the input signal must be active for at least 2 rtc clocks to ensure detection. the setting of these bits has no effect if the corresponding gpio is programmed as an output. these bits correspond to gpio that are in the resume well, and will be reset to their default values by rsmrst# or by a write to the cf9h register. 0 = the corresponding gpi_sts bit is set when the ich5 detects the state of the input pin to be high. 1 = the corresponding gpi_sts bit is set when the ich5 detects the state of the input pin to be low. 7:0 gp_inv[n] ? r/w. these bits are used to allow both active-low and active-high inputs to cause smi# or sci. note that in the s0 or s1 state, the input signal must be active for at least 2 pci clocks to ensure detection by the ich5. the setting of these bits will have no effect if the corresponding gpio is programmed as an output. these bits correspond to gpio that are in the core well, and will be reset to their default values by pcirst#. 0 = the corresponding gpi_sts bit is set when the ich5 detects the state of the input pin to be high. 1 = the corresponding gpi_sts bit is set when the ich5 detects the state of the input pin to be low. bit description 31:0 gpio_use_sel2[49:48, 41:40]? r/w. each bit in this register enables the corresponding gpio (if it exists) to be used as a gpio, rather than for the native function. 0 = signal used as native function. 1 = signal used as a gpio. notes: 1. the following bits are not implemented because there is no corresponding gpio: 31:18, 16:10, 7:3. 2. the following bits are always 1 because they are unmuxed: 2:0. 3. if gpion does not exist, then the bit in this register will always read as 0 and writes will have no effect. after a full reset (rsmrst#) all multiplexed signals in the resume and core wells are configured as their native function rather than as a gpio. after just a pcirst#, the gpio in the core well are configured as their native function. intel ? 82801eb ich5 / 82801er ich5r datasheet 413 lpc interface bridge registers (d31:f0) 9.12.7 gp_io_sel2?gpio input/output select 2 register offset address: gpiobase +34h attribute: r/w default value: 00000300h size: 32-bit lockable: no power well: core bit description 31:18 always 0. no corresponding gpio. 17:16 always 0. outputs. 15:10 always 0. no corresponding gpio. 9:8 always 0. inputs. 7:3 always 0. no corresponding gpio. 2 gp_io_sel2 [34] ? r/w. 0 = gpio signal is programmed as an output. 1 = corresponding gpio signal (if enabled in the gpio_use_sel2 register) is programmed as an input. 1 no corresponding gpio 0 gp_io_sel2 [32] ? r/w. 0 = gpio signal is programmed as an output. 1 = corresponding gpio signal (if enabled in the gpio_use_sel2 register) is programmed as an input. 414 intel ? 82801eb ich5 / 82801er ich5r datasheet lpc interface bridge registers (d31:f0) 9.12.8 gp_lvl2?gpio level for input or output 2 register offset address: gpiobase +38h attribute: r/w default value: 00030207h size: 32-bit lockable: no power well: see below bit description 31:18 reserved. read-only 0 17:16 gp_lvl[49:48] ? r/w. the corresponding gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. since these bits correspond to gpio that are in the processor i/ o and core well, respectively, these bits will be reset by pcirst#. 0 = low 1 = high 15:10 reserved. read-only 0 9:8 gp_lvl[41:40] ? r/w. the corresponding gp_lvl[n] bit reflects the state of the input signal. writes will have no effect. since these bits correspond to gpio that are in the core well, these bits will be reset by pcirst#. 0 = low 1 = high 7:3 reserved. read-only 0 2 gp_lvl [34] ? r/w. if gpion is programmed to be an output (via the corresponding bit in the gp_io_sel register), then the corresponding gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. if gpion is programmed as an input, then the corresponding gp_lvl bit reflects the state of the input signal (1 = high, 0 = low). writes will have no effect. 0 = low 1 = high since these bits correspond to gpio that are in the core well, these bits will be reset by pcirst#. 1 reserved 0 gp_lvl [32] ? r/w. if gpion is programmed to be an output (via the corresponding bit in the gp_io_sel register), then the corresponding gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. if gpion is programmed as an input, then the corresponding gp_lvl bit reflects the state of the input signal (1 = high, 0 = low). writes will have no effect. 0 = low 1 = high since these bits correspond to gpio that are in the core well, these bits will be reset by pcirst#. intel ? 82801eb ich5 / 82801er ich5r datasheet 415 ide controller registers (d31:f1) ide controller registers (d31:f1) 10 10.1 pci configuration registers (ide?d31:f1) note: address locations that are not shown in table 154 should be treated as reserved (see section 6.2 for details). all of the ide registers are in the core well. none of the registers can be locked. notes: 1. refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. 2. the ich5 ide controller is not arbitrated as a pci device; therefore, it does not need a master latency timer. table 154. ide controller pci register address map (ide-d31:f1) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 24dbh ro 04?05h pcicmd pci command 00h r/w, ro 06?07h pcists pci status 0280h r/w, ro 08h rid revision identification see register description. ro 09h pi programming interface 8ah r/w, ro 0ah scc sub class code 01h ro 0bh bcc base class code 01h ro 0dh pmlt primary master latency timer 00h ro 10?13h pcmd_bar primary command block base address 00000001h r/w, ro 14?17h pcnl_bar primary control block base address 00000001h r/w, ro 18?1bh scmd_bar secondary command block base address 00000001h r/w, ro 1c?1fh scnl_bar secondary control block base address 00000001h r/w, ro 20?23h bm_base bus master base address 00000001h r/w, ro 2c?2dh ide_svid subsystem vendor id 00h r/wo 2e?2fh ide_sid subsystem id 00h r/wo 3c intr_ln interrupt line 00h r/w 3d intr_pn interrupt pin 01h ro 40?41h ide_timp primary ide timing 0000h r/w 42?43h ide_tims secondary ide timing 0000h r/w 44h slv_idetim slave ide timing 00h r/w 48h sdma_cnt synchronous dma control 00h r/w 4a?4bh sdma_tim synchronous dma timing 0000h r/w 54h ide_config ide i/o configuration 00h r/w 416 intel ? 82801eb ich5 / 82801er ich5r datasheet ide controller registers (d31:f1) 10.1.1 vid?vendor identification register (ide?d31:f0) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16-bit lockable: no power well: core 10.1.2 did?device identification register (ide?d31:f0) offset address: 02 ? 03h attribute: ro default value: 24dbh size: 16-bit lockable: no power well: core bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich5 ide controller. intel ? 82801eb ich5 / 82801er ich5r datasheet 417 ide controller registers (d31:f1) 10.1.3 pcicmd?pci command register (ide?d31:f1) address offset: 04h ? 05h attribute: ro, r/w default value: 00h size: 16 bits bit description 15:11 reserved 10 interrupt disable (id) ? r/w. 0 = enables the ide controller to assert inta# (native mode) or irq14/15 (legacy mode). 1 = disable. the interrupt will be deasserted. 9 fast back to back enable (fbe) ? ro. reserved as 0. 8 serr# enable (serr_en) ? ro. reserved as 0. 7 wait cycle control (wcc) ? ro. reserved as 0. 6 parity error response (per) ? ro. reserved as 0. 5 vga palette snoop (vps) ? ro. reserved as 0. 4 postable memory write enable (pmwe) ? ro. reserved as 0. 3 special cycle enable (sce) ? ro. reserved as 0. 2 bus master enable (bme) ? r/w. controls the intel ? ich5?s ability to act as a pci master for ide bus master transfers. 1 memory space enable (mse) ? r/w. 0 = disables access. 1 = enables access to the ide expansion memory range. the exbar register (offset 24h) must be programmed before this bit is set. note: bios should set this bit to a 1. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disables access to the legacy or native ide ports (both primary and secondary) as well as the bus master io registers. 1 = enable. note that the base address register for the bus master registers should be programmed before this bit is set. notes: 1. separate bits are provided (ide decode enable, in the ide timing register) to independently disable the primary or secondary i/o spaces. 2. when this bit is 0 and the ide controller is in native mode, the interrupt pin register (see section 10.1.18 ) will be masked (the interrupt will not be asserted). if an interrupt occurs while the masking is in place and the interrupt is still active when the masking ends, the interrupt will be allowed to be asserted. 418 intel ? 82801eb ich5 / 82801er ich5r datasheet ide controller registers (d31:f1) 10.1.4 pcists ? pci status register (ide?d31:f1) address offset: 06 ? 07h attribute: r/wc, ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? ro. reserved as 0. 14 signaled system error (sse) ? ro. reserved as 0. 13 received master abort (rma) ? r/wc. 0 = master abort not generated by bus master ide interface function. 1 = bus master ide interface function, as a master, generated a master abort. 12 reserved as 0 ? ro. 11 signaled target abort (sta) ? r/wc. 0 = intel ? ich5 did not target abort a transaction targeting the ide interface function. 1 = ide interface function is targeted with a transaction that the ich5 terminates with a target abort. 10:9 devsel# timing status (dev_sts) ? ro. 01 = hardwired; however, the ich5 does not have a real devsel# signal associated with the ide unit, so these bits have no effect. 8 data parity error detected (dped) ? ro. reserved as 0. 7 fast back to back capable (fb2bc) ? ro. reserved as 1. 6 user definable features (udf) ? ro. reserved as 0. 5 66 mhz capable (66mhz_cap) ? ro. reserved as 0. 4 reserved 3 interrupt status (ints) ? ro. this bit is independent of the state of the interrupt disable bit in the command register. 0 = interrupt is cleared. 1 = interrupt/msi is asserted. 2:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 419 ide controller registers (d31:f1) 10.1.5 rid?revision identification register (ide?d31:f1) offset address: 08h attribute: ro default value: see bit description size: 8 bits 10.1.6 pi?programming interface register (ide?d31:f1) address offset: 09h attribute: r/w, ro default value: 8ah size: 8 bits 10.1.7 scc?sub class code register (ide?d31:f1) address offset: 0ah attribute: ro default value: 01h size: 8 bits bit description 7:0 revision id ? ro. this 8-bit value indicates the revision number for ide controller. note: refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. bit description 7 this read-only bit is a 1 to indicate that the intel ? ich5 supports bus master operation. 6:4 reserved. hardwired to 000b. 3 sop_mode_cap ? ro. this read-only bit is a 1 to indicate that the secondary controller supports both legacy and native modes. 2 sop_mode_sel ? r/w. this read/write bit determines the mode that the secondary ide channel is operating in. 0 = legacy-pci mode (default) 1 = native-pci mode 1 pop_mode_cap ? ro. this read-only bit is a 1 to indicate that the primary controller supports both legacy and native modes. 0 pop_mode_sel ? r/w. this read/write bits determines the mode that the primary ide channel is operating in. 0 = legacy-pci mode (default) 1 = native-pci mode bit description 7:0 sub class code (scc) ? ro. 01h = ide device, in the context of a mass storage device. 420 intel ? 82801eb ich5 / 82801er ich5r datasheet ide controller registers (d31:f1) 10.1.8 bcc?base class code register (ide?d31:f1) address offset: 0bh attribute: ro default value: 01h size: 8 bits 10.1.9 pmlt?primary master latency timer register (ide?d31:f1) address offset: 0dh attribute: ro default value: 00h size: 8 bits 10.1.10 pcmd_bar?primary command block base address register (ide?d31:f1) address offset: 10h ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 8-byte i/o space is used in native mode for the primary controller?s command block. bit description 7:0 base class code (bcc) ? ro. 01 = mass storage device bit description 7:0 master latency timer count (mltc) ? ro. 00h =hardwired. the ide controller is implemented internally, and is not arbitrated as a pci device, so it does not need a master latency timer. bit description 31:16 reserved 15:3 base address ? r/w. base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. intel ? 82801eb ich5 / 82801er ich5r datasheet 421 ide controller registers (d31:f1) 10.1.11 pcnl_bar?primary control block base address register (ide?d31:f1) address offset: 14h ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 4-byte i/o space is used in native mode for the primary controller?s command block. 10.1.12 scmd_bar?secondary command block base address register (ide d31:f1) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. 10.1.13 scnl_bar?secondary control block base address register (ide d31:f1) address offset: 1ch ? 1fh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. bit description 31:16 reserved 15:2 base address ? r/w. base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. bit description 31:16 reserved 15:3 base address ? r/w. base address of the i/o space (eight, consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. base address of the i/o space (four, consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. 422 intel ? 82801eb ich5 / 82801er ich5r datasheet ide controller registers (d31:f1) 10.1.14 bm_base ? bus master base address register (ide?d31:f1) address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits the bus master ide interface function uses base address register 5 to request a 16-byte i/o space to provide a software interface to the bus master functions. only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). only bits [15:4] are used to decode the address. 10.1.15 ide_svid ? subsystem vendor identification (ide?d31:f1) address offset: 2ch ? 2dh attribute: r/wo default value: 00h size: 16 bits lockable: no power well: core 10.1.16 ide_sid ? subsystem identification register (ide?d31:f1) address offset: 2eh ? 2fh attribute: r/wo default value: 00h size: 16 bits lockable: no power well: core bit description 31:16 reserved 15:4 base address ? r/w. this field provides the base address of the i/o space (16 consecutive i/o locations). 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. bit description 15:0 subsystem vendor id (svid) ? r/wo. the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. software (bios) sets the value in this register. after that, the value can be read, but subsequent writes to this register have no effect. the value written to this register will also be readable via the corresponding svid registers for the usb#1, usb#2, and smbus functions. bit description 15:0 subsystem id (sid) ? r/wo. the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. software (bios) sets the value in this register. after that, the value can be read, but subsequent writes to this register have no effect. the value written to this register will also be readable via the corresponding sid registers for the usb#1, usb#2, and smbus functions. intel ? 82801eb ich5 / 82801er ich5r datasheet 423 ide controller registers (d31:f1) 10.1.17 intr_ln?interrupt line register (ide?d31:f1) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 10.1.18 intr_pn?interrupt pin register (ide?d31:f1) address offset: 3dh attribute: ro default value: 01h size: 8 bits bit description 7:0 interrupt line (int_ln) ? r/w. this field is used to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:3 reserved 2:0 interrupt pin (int_pin) ? ro. hardwired to 01h to indicate to ?software? that the intel ? ich5 will drive inta#. note that this is only used in native mode. also note that the routing to the internal interrupt controller doesn?t necessarily relate to the value in this register. the ide interrupt is in fact routed to pirqc# (irq18 in apic mode). 424 intel ? 82801eb ich5 / 82801er ich5r datasheet ide controller registers (d31:f1) 10.1.19 ide_tim ? ide timing register (ide?d31:f1) address offset: primary: 40 ? 41h attribute: r/w secondary: 42 ? 43h default value: 0000h size: 16 bits this register controls the timings driven on the ide cable for pio and 8237 style dma transfers. it also controls operation of the buffer for pio transfers. bit description 15 ide decode enable (ide) ? r/w. this bit enables/disables the primary or secondary decode. the ide i/o space enable bit in the command register must be set in order for this bit to have any effect. additionally, separate configuration bits are provided (in the ide i/o configuration register) to individually disable the primary or secondary ide interface signals, even if the ide decode enable bit is set. 0 = disable 1 = enables the intel ? ich5 to decode the associated command blocks (1f0?1f7h for primary, 170?177h for secondary) and control block (3f6h for primary and 376h for secondary). this bit effects the ide decode ranges for both legacy and native-mode decoding. it also effects the corresponding primary or secondary memory decode range for ide expansion. 14 drive 1 timing register enable (sitre) ? r/w. 0 = use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = use bits 13:12, 9:8 for drive 0, and use the slave ide timing register for drive 1. 13:12 iordy sample point (isp) ? r/w. the setting of these bits determine the number of pci clocks between ide ior#/iow# assertion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 11:10 reserved 9:8 recovery time (rct) ? r/w. the setting of these bits determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock 7 drive 1 dma timing enable (dte1) ? r/w. 0 = disable 1 = enable the fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 6 drive 1 prefetch/posting enable (ppe1) ? r/w. 0 = disable 1 = enable prefetch and posting to the ide data port for this drive. 5 drive 1 iordy sample point enable (ie1) ? r/w. 0 = disable iordy sampling for this drive. 1 = enable iordy sampling for this drive. intel ? 82801eb ich5 / 82801er ich5r datasheet 425 ide controller registers (d31:f1) 10.1.20 slv_idetim?slave (drive 1) ide timing register (ide?d31:f1) address offset: 44h attribute: r/w default value: 00h size: 8 bits 4 drive 1 fast timing bank (time1) ? r/w. 0 = accesses to the data port will use compatible timings for this drive. 1 = when this bit = 1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time. when this bit = 1 and bit 14 = 1, accesses to the data port will use the iordy sample point and recover time specified in the slave ide timing register. 3 drive 0 dma timing enable (dte0) ? r/w. 0 = disable 1 = enable fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 2 drive 0 prefetch/posting enable (ppe0) ? r/w. 0 = disable prefetch and posting to the ide data port for this drive. 1 = enable prefetch and posting to the ide data port for this drive. 1 drive 0 iordy sample point enable (ie0) ? r/w. 0 = disable iordy sampling is disabled for this drive. 1 = enable iordy sampling for this drive. 0 drive 0 fast timing bank (time0) ? r/w. 0 = accesses to the data port will use compatible timings for this drive. 1 = accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time bit description bit description 7:6 secondary drive 1 iordy sample point (sisp1) ? r/w. this field determines the number of pci clocks between ide ior#/iow# assertion and the first iordy sample point, if the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 426 intel ? 82801eb ich5 / 82801er ich5r datasheet ide controller registers (d31:f1) 5:4 secondary drive 1 recovery time (srct1) ? r/w. this field determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks 3:2 primary drive 1 iordy sample point (pisp1) ? r/w. this field determines the number of pci clocks between ior#/iow# assertion and the first iordy sample point, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 1:0 primary drive 1 recovery time (prct1) ? r/w. this field determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 427 ide controller registers (d31:f1) 10.1.21 sdma_cnt?synchronous dma control register (ide?d31:f1) address offset: 48h attribute: r/w default value: 00h size: 8 bits bit description 7:4 reserved 3 secondary drive 1 synchronous dma mode enable (ssde1) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for secondary channel drive 1. 2 secondary drive 0 synchronous dma mode enable (ssde0) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for secondary drive 0. 1 primary drive 1 synchronous dma mode enable (psde1) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 1. 0 primary drive 0 synchronous dma mode enable (psde0) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 0. 428 intel ? 82801eb ich5 / 82801er ich5r datasheet ide controller registers (d31:f1) 10.1.22 sdma_tim?synchronous dma timing register (ide?d31:f1) address offset: 4a ? 4bh attribute: r/w default value: 0000h size: 16 bits note: for fast_scb1 = 1 (133 mhz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to section 5.16.6 for details. bit description 15:14 reserved 13:12 secondary drive 1 cycle time (sct1) ? r/w. for ultra ata mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. scb1 = 0 (33 mhz clk) scb1 = 1 (66 mhz clk) fast_scb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clks, rp 16 clks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved 11:10 reserved 9:8 secondary drive 0 cycle time (sct0) ? r/w. for ultra ata mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. scb1 = 0 (33 mhz clk) scb1 = 1 (66 mhz clk) fast_scb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clks, rp 16 clks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved 7:6 reserved 5:4 primary drive 1 cycle time (pct1) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. pcb1 = 0 (33 mhz clk) pcb1 = 1 (66 mhz clk) fast_pcb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clks, rp 16 clks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved 3:2 reserved 1:0 primary drive 0 cycle time (pct0) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. pcb1 = 0 (33 mhz clk) pcb1 = 1 (66 mhz clk) fast_pcb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clks, rp 16 clks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 429 ide controller registers (d31:f1) 10.1.23 ide_config?ide i/o configuration register (ide?d31:f1) address offset: 54h attribute: r/w default value: 00h size: 32 bits bit description 31:20 reserved 19:18 sec_sig_mode ? r/w. these bits are used to control mode of the secondary ide signal pins for swap bay support. if the srs bit (bit 15, offset d0h of d31:f0) is 1, the reset states of bits 19:18 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved 17:16 prim_sig_mode ? r/w. these bits are used to control mode of the primary ide signal pins for swap bay support. if the prs bit (bit 14, offset d0h of d31:f0) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved 15 fast secondary drive 1 base clock (fast_scb1) ? r/w. this bit is used in conjunction with the sct1 bits to enable/disable ultra ata/100 timings for the secondary slave drive. 0 = disable ultra ata/100 timing for the secondary slave drive. 1 = enable ultra ata/100 timing for the secondary slave drive (overrides bit 3 in this register). 14 fast secondary drive 0 base clock (fast_scb0) ? r/w. this bit is used in conjunction with the sct0 bits to enable/disable ultra ata/100 timings for the secondary master drive. 0 = disable ultra ata/100 timing for the secondary master drive. 1 = enable ultra ata/100 timing for the secondary master drive (overrides bit 2 in this register). 13 fast primary drive 1 base clock (fast_pcb1) ? r/w. this bit is used in conjunction with the pct1 bits to enable/disable ultra ata/100 timings for the primary slave drive. 0 = disable ultra ata/100 timing for the primary slave drive. 1 = enable ultra ata/100 timing for the primary slave drive (overrides bit 1 in this register). 12 fast primary drive 0 base clock (fast_pcb0) ? r/w. this bit is used in conjunction with the pct0 bits to enable/disable ultra ata/100 timings for the primary master drive. 0 = disable ultra ata/100 timing for the primary master drive. 1 = enable ultra ata/100 timing for the primary master drive (overrides bit 0 in this register). 11:8 reserved 7 secondary slave channel cable reporting ? r/w. bios should program this bit to tell the ide driver which cable is plugged into the channel. 0 = 40 conductor cable is present. 1 = 80 conductor cable is present. 6 secondary master channel cable reporting ? r/w. same description as bit 7. 5 primary slave channel cable reporting ? r/w. same description as bit 7. 4 primary master channel cable reporting ? r/w. same description as bit 7. 3 secondary drive 1 base clock (scb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings. 430 intel ? 82801eb ich5 / 82801er ich5r datasheet ide controller registers (d31:f1) 10.2 bus master ide i/o registers (ide?d31:f1) the bus master ide function uses 16 bytes of i/o space, allocated via the bmiba register, located in device 31:function 1 configuration space, offset 20h. all bus master ide i/o space registers can be accessed as byte, word, or dword quantities. reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). the description of the i/o registers is shown in table 155 . 2 secondary drive 0 base clock (scbo) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings. 1 primary drive 1 base clock (pcb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings. 0 primary drive 0 base clock (pcb0) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings. bit description table 155. bus master ide i/o registers offset mnemonic register name default type 00 bmicp bus master ide command primary 00h r/w 01 ? reserved 00h ro 02 bmisp bus master ide status primary 00h r/wc 03 ? reserved 00h ro 04?07 bmidp bus master ide descriptor table pointer primary xxxxxxxxh r/w 08 bmics bus master ide command secondary 00h r/w 09 ? reserved 00h ro 0a bmiss bus master ide status secondary 00h r/wc 0b ? reserved 00h ro 0c?0f bmids bus master ide descriptor table pointer secondary xxxxxxxxh r/w intel ? 82801eb ich5 / 82801er ich5r datasheet 431 ide controller registers (d31:f1) 10.2.1 bmic[p,s]?bus master ide command register (ide?d31:f1) address offset: primary: 00h attribute: r/w secondary: 08h default value: 00h size: 8 bits bit description 7:4 reserved. returns 0. 3 read / write control (rwc) ? r/w. this bit sets the direction of the bus master transfer: this bit must not be changed when the bus master function is active. 0 = memory reads 1 = memory writes 2:1 reserved. returns 0. 0 start/stop bus master (start) ? r/w. 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. if this bit is reset while bus master operation is still active (i.e., the bus master ide active bit of the bus master ide status register for that ide channel is set) and the drive has not yet finished its data transfer (the interrupt bit in the bus master ide status register for that ide channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the controller. bus master operation does not actually start unless the bus master enable bit (d31:f1: offset 04h, bit 2) in pci configuration space is also set. bus master operation begins when this bit is detected changing from 0 to 1. the controller will transfer data between the ide device and memory only when this bit is set. master operation can be halted by writing a 0 to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bus master ide active bit being cleared or the interrupt bit of the bus master ide status register for that ide channel being set, or both. hardware does not clear this bit automatically. 432 intel ? 82801eb ich5 / 82801er ich5r datasheet ide controller registers (d31:f1) 10.2.2 bmis[p,s]?bus master ide status register (ide?d31:f1) address offset: primary: 02h attribute: r/wc secondary: 0ah default value: 00h size: 8 bits 10.2.3 bmid[p,s]?bus master ide descriptor table pointer register (ide?d31:f1) address offset: primary: 04h attribute: r/w secondary: 0ch default value: all bits undefined size: 32 bits bit description 7 reserved. returns 0. 6 drive 1 dma capable ? r/w. 0 = not capable. 1 = capable. set by device dependent code (bios or device driver) to indicate that drive 1 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the intel ? ich5 does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 5 drive 0 dma capable ? r/w. 0 = not capable 1 = capable. set by device dependent code (bios or device driver) to indicate that drive 0 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the ich5 does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 4:3 reserved. returns 0. 2 interrupt ? r/wc. software can use this bit to determine if an ide device has asserted its interrupt line (irq 14 for the primary channel, and irq 15 for secondary). 0 = software clears this bit by writing a 1 to it. if this bit is cleared while the interrupt is still active, this bit will remain clear until another assertion edge is detected on the interrupt line. 1 = set by the rising edge of the ide interrupt line, regardless of whether or not the interrupt is masked in the 8259 or the internal i/o apic. when this bit is read as 1, all data transferred from the drive is visible in system memory. 1 error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the controller encounters a target abort or master abort when transferring data on pci. 0 bus master ide active (act) ? ro. 0 = this bit is cleared by the ich5 when the last transfer for a region is performed, where eot for that region is set in the region descriptor. it is also cleared by the ich5 when the start bit is cleared in the command register. when this bit is read as 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = set by the ich5 when the start bit is written to the command register. bit description 31:2 address of descriptor table (addr) ? r/w. corresponds to a[31:2]. the descriptor table must be dword-aligned. the descriptor table must not cross a 64-k boundary in memory. 1:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 433 sata controller registers (d31:f2) sata controller registers (d31:f2) 11 11.1 pci configuration registers (sata?d31:f2) note: address locations that are not shown in table 156 should be treated as reserved (see section 6.2 for details). all of the sata registers are in the core well. none of the registers can be locked. table 156. sata controller pci register address map (sata?d31:f2) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 24d1h (intel ? 82801eb ich5) 24dfh (82801er ich5r) ro 04?05h pcicmd pci command 00h r/w, ro 06?07h pcists pci status 02b0h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 8ah r/w, ro 0ah scc sub class code 01h (82801eb ich5) 04h (82801er ich5r) ro 0bh bcc base class code 01h ro 0dh pmlt primary master latency timer 00h ro 10?13h pcmd_bar primary command block base address 00000001h r/w, ro 14?17h pcnl_bar primary control block base address 00000001h r/w, ro 18?1bh scmd_bar secondary command block base address 00000001h r/w, ro 1c?1fh scnl_bar secondary control block base address 00000001h r/w, ro 20?23h bar legacy bus master base address 00000001h r/w, ro 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 34h cap capabilities pointer 80h ro 3c int_ln interrupt line 00h r/w 3d int_pn interrupt pin 01h ro 40?41h ide_timp primary ide timing 0000h r/w 42?43h ide_tims secondary ide timing 0000h r/w 44h sidetim slave ide timing 00h r/w 48h sdma_cnt synchronous dma control 00h r/w 4a?4bh sdma_tim synchronous dma timing 0000h r/w 54?57h ide_config ide i/o configuration 00000000h r/w 434 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) notes: 1. refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. 2. the ich5 sata controller is not arbitrated as a pci device, therefore it does not need a master latency timer. 11.1.1 vid?vendor identification register (sata?d31:f2) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16 bit lockable: no power well: core 11.1.2 did?device identification register (sata?d31:f2) offset address: 02 ? 03h attribute: ro default value: 24d1h (82801eb ich5 only) size: 16 bit 24dfh (82801er ich5r only) lockable: no power well: core 70?71h pid pci power management capability id 0001h ro 72?73h pc pci power management capabilities 0002h ro 74?75h pmcs pci power management control and status 0000h r/w, ro 80?81h mid message signaled interrupt id 7005h ro 82?83h mc message signaled interrupt message control 0000h r/w, ro 84?87h ma message signaled interrupt message address 00000000h r/w 88?89h md message signaled interrupt message data 0000h r/w 90h map address map 00h r/w 92h?93h pcs port control and status 0000h r/w, ro a0h sri sata registers index 00h r/w a4h srd sata registers data xxh r/w e0h?e3h bfcs bist fis control/status 00000000h r/w, r/wc e4h?e7h bftd1 bist fis transmit data, dw1 00000000h r/w e8h?ebh bftd2 bist fis transmit data, dw2 00000000h r/w table 156. sata controller pci register address map (sata?d31:f2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich5 sata controller. intel ? 82801eb ich5 / 82801er ich5r datasheet 435 sata controller registers (d31:f2) 11.1.3 pcicmd?pci command register (sata?d31:f2) address offset: 04h ? 05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = enables the sata host controller to assert inta# (native mode), irq14/15 (legacy mode), and msi (if msi is enabled). 1 = the interrupt will be deasserted and it may not generate msis. 9 fast back to back enable (fbe) ? ro. reserved as 0. 8 serr# enable (serr_en) ? ro. reserved as 0. 7 wait cycle control (wcc) ? ro. reserved as 0. 6 parity error response (per) ? r/w. 0 = disabled. sata controller will not generate perr# when a data parity error is detected. 1 = enabled. sata controller will generate perr# when a data parity error is detected. 5 vga palette snoop (vps) ? ro. reserved as 0. 4 postable memory write enable (pmwe) ? ro. reserved as 0. 3 special cycle enable (sce) ? ro. reserved as 0. 2 bus master enable (bme) ? r/w. this bit controls the intel ? ich5?s ability to act as a pci master for ide bus master transfers. this bit does not impact the generation of completions for split transaction commands. 1 memory space enable (mse) ? ro. the sata controller does not contain memory space. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disables access to the legacy or native ide ports (both primary and secondary) as well as the bus master i/o registers. 1 = enable. note that the base address register for the bus master registers should be programmed before this bit is set. 436 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.1.4 pcists ? pci status register (sata?d31:f2) address offset: 06 ? 07h attribute: r/wc, ro default value: 02a0h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected by sata controller. 1 = sata controller detects a parity error on its interface. 14 signaled system error (sse) ? ro. reserved as 0. 13 received master abort (rma) ? r/wc. 0 = master abort not generated. 1 = bus master ide interface function, as a master, generated a master abort. 12 reserved as 0 ? ro. 11 signaled target abort (sta) ? ro. reserved as 0. 10:9 devsel# timing status (dev_sts) ? ro. 01 = hardwired; controls the device select time for the sata controller?s pci interface. 8 data parity error detected (dped) ? ro. for intel ? ich5, this bit can only be set on read completions received from sibus where there is a parity error. 1 = sata controller, as a master, either detects a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. 7 fast back to back capable (fb2bc) ? ro. reserved as 1. 6 user definable features (udf) ? ro. reserved as 0. 5 66 mhz capable (66mhz_cap) ? ro. reserved as 1. 4 capabilities list (cap_list) ? ro. this bit indicates the presence of a capabilities list. the minimum requirement for the capabilities list must be pci power management for the sata controller. 0 = a capabilities list is not present 1 = a capabilities list is present note: this bit is hardwired to 0. 3 interrupt status (ints)? ro. this bit is independent of the state of the interrupt disable bit in the command register. 0 = interrupt is cleared. 1 = interrupt/msi is asserted. 2:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 437 sata controller registers (d31:f2) 11.1.5 rid?revision identification register (sata?d31:f2) offset address: 08h attribute: ro default value: see bit description size: 8 bits 11.1.6 pi?programming interface register (sata?d31:f2) address offset: 09h attribute: r/w, ro default value: 8ah size: 8 bits 11.1.7 scc?sub class code register (sata?d31:f2) address offset: 0ah attribute: ro default value: 01h (82801eb ich5 only) size: 8 bits 04h (82801er ich5r only) bit description 7:0 revision id (rid) ? ro. 8-bit value that indicates the revision number for sata. note: refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. bit description 7 this read-only bit is a 1 to indicate that the intel ? ich5 supports bus master operation 6:4 reserved. will always return 0. 3 sop_mode_cap ? ro. hardwired to 1 to indicate that the secondary controller supports both legacy and native modes. 2 sop_mode_sel ? r/w. this bit determines the operating mode of the secondary ide channel. 0 = legacy-pci mode (default) 1 = native-pci mode 1 pop_mode_cap ? ro. hardwired to 1 indicate that the primary controller supports both legacy and native modes. 0 pop_mode_sel ? r/w. this bit determines the operating mode of the primary ide channel. 0 = legacy-pci mode (default) 1 = native-pci mode bit description 7:0 sub class code (scc) ? ro. 01h = ide device, in the context of a mass storage device. (intel ? 82801eb ich5 only) 04h = intel ? raid technology device, in the context of a mass storage device. (intel ? 82801er ich5r only) 438 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.1.8 bcc?base class code register (sata?d31:f2) address offset: 0bh attribute: ro default value: 01h size: 8 bits 11.1.9 pmlt?primary master latency timer register (sata?d31:f2) address offset: 0dh attribute: ro default value: 00h size: 8 bits 11.1.10 pcmd_bar?primary command block base address register (sata?d31:f2) address offset: 10h ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 8-byte i/o space is used in native mode for the primary controller?s command block. bit description 7:0 base class code (bcc) ? ro. 01h = mass storage device bit description 7:0 master latency timer count (mltc) ? ro. 00h = hardwired. the ide controller is implemented internally, and is not arbitrated as a pci device, so it does not need a master latency timer. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the base address of the i/o space (eight, consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. intel ? 82801eb ich5 / 82801er ich5r datasheet 439 sata controller registers (d31:f2) 11.1.11 pcnl_bar?primary control block base address register (sata?d31:f2) address offset: 14h ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 4-byte i/o space is used in native mode for the primary controller?s command block. 11.1.12 scmd_bar?secondary command block base address register (ide d31:f1) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. 11.1.13 scnl_bar?secondary control block base address register (ide d31:f1) address offset: 1ch ? 1fh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base address of the i/o space (four, consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the base address of the i/o space (eight, consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base address of the i/o space (four, consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. 440 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.1.14 bar ? legacy bus master base address register (sata?d31:f2) address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits the bus master ide interface function uses base address register 5 to request a 16-byte io space to provide a software interface to the bus master functions. only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). only bits [15:4] are used to decode the address. 11.1.15 svid?subsystem vendor identification register (sata?d31:f2) address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 11.1.16 sid?subsystem identification register (sata?d31:f2) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core bit description 31:16 reserved 15:4 base address ? r/w. this field provides the base address of the i/o space (16 consecutive i/o locations). 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 15:0 subsystem vendor id (svid) ? r/wo. the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. software (bios) sets the value in this register. after that, the value can be read, but subsequent writes to this register have no effect. bit description 15:0 subsystem id (sid) ? r/wo . the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. software (bios) sets the value in this register. after that, the value can be read, but subsequent writes to this register have no effect. intel ? 82801eb ich5 / 82801er ich5r datasheet 441 sata controller registers (d31:f2) 11.1.17 cap?capabilities pointer register (sata?d31:f2) address offset: 34h attribute: ro default value: 00h size: 8 bits 11.1.18 int_ln?interrupt line register (sata?d31:f2) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 11.1.19 int_pn?interrupt pin register (sata?d31:f2) address offset: 3dh attribute: ro default value: 01h size: 8 bits bit description 7:0 capabilities pointer (cap_ptr) ? ro. this bit indicates that the first capability pointer is set to 00h and therefore is not pointing to anything (i.e., disabled). bit description 7:0 interrupt line ? r/w. this field is used to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:3 reserved 2:0 interrupt pin ? ro. hardwired to 01h indicating to ?software? that the intel ? ich5 will drive inta#. note that this is only used in native mode. also note that the routing to the internal interrupt controller doesn?t necessarily relate to the value in this register. 442 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.1.20 ide_tim ? ide timing register (sata?d31:f2) address offset: primary: 40 ? 41h attribute: r/w secondary: 42 ? 43h default value: 0000h size: 16 bits this register controls the timings driven on the ide cable for pio and 8237 style dma transfers. it also controls operation of the buffer for pio transfers. note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are combined. these bits have no effect on sata operation unless otherwise noted. bit description 15 ide decode enable (ide) ? r/w. individually enable/disable the primary or secondary decode. 0 = disable 1 = enables the intel ? ich5 to decode the associated command blocks (1f0?1f7h for primary, 170?177h for secondary) and control block (3f6h for primary and 376h for secondary). this bit effects the ide decode ranges for both legacy and native-mode decoding. note: this bit affects sata operation in both combined and non-combined ata modes. see section 6.16 for more on ata modes of operation. 14 drive 1 timing register enable (sitre) ? r/w. 0 = use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = use bits 13:12, 9:8 for drive 0, and use the slave ide timing register for drive 1 13:12 iordy sample point (isp) ? r/w. the setting of these bits determines the number of pci clocks between ide ior#/iow# assertion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 11:10 reserved 9:8 recovery time (rct) ? r/w. the setting of these bits determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock 7 drive 1 dma timing enable (dte1) ? r/w. 0 = disable 1 = enable the fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 6 drive 1 prefetch/posting enable (ppe1) ? r/w. 0 = disable 1 = enable prefetch and posting to the ide data port for this drive. 5 drive 1 iordy sample point enable (ie1) ? r/w. 0 = disable iordy sampling for this drive. 1 = enable iordy sampling for this drive. intel ? 82801eb ich5 / 82801er ich5r datasheet 443 sata controller registers (d31:f2) 4 drive 1 fast timing bank (time1) ? r/w. 0 = accesses to the data port will use compatible timings for this drive. 1 = when this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time. when this bit = 1 and bit 14 = 1, accesses to the data port will use the iordy sample point and recover time specified in the slave ide timing register. 3 drive 0 dma timing enable (dte0) ? r/w. 0 = disable 1 = enable fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 2 drive 0 prefetch/posting enable (ppe0) ? r/w. 0 = disable prefetch and posting to the ide data port for this drive. 1 = enable prefetch and posting to the ide data port for this drive. 1 drive 0 iordy sample point enable (ie0) ? r/w. 0 = disable iordy sampling is disabled for this drive. 1 = enable iordy sampling for this drive. 0 drive 0 fast timing bank (time0) ? r/w. 0 = accesses to the data port will use compatible timings for this drive. 1 = accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time bit description 444 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.1.21 sidetim?slave ide timing register (sata?d31:f2) address offset: 44h attribute: r/w default value: 00h size: 8 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are combined. these bits have no effect on sata operation unless otherwise noted. bit description 7:6 secondary drive 1 iordy sample point (sisp1) ? r/w. this field determines the number of pci clocks between ide ior#/iow# assertion and the first iordy sample point, if the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 5:4 secondary drive 1 recovery time (srct1) ? r/w. this field determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks 3:2 primary drive 1 iordy sample point (pisp1) ? r/w. this field determines the number of pci clocks between ior#/iow# assertion and the first iordy sample point, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 1:0 primary drive 1 recovery time (prct1) ? r/w. this field determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks intel ? 82801eb ich5 / 82801er ich5r datasheet 445 sata controller registers (d31:f2) 11.1.22 sdma_cnt?synchronous dma control register (sata?d31:f2) address offset: 48h attribute: r/w default value: 00h size: 8 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are combined. these bits have no effect on sata operation unless otherwise noted. bit description 7:4 reserved 3 secondary drive 1 synchronous dma mode enable (ssde1) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for secondary channel drive 1 2 secondary drive 0 synchronous dma mode enable (ssde0) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for secondary drive 0. 1 primary drive 1 synchronous dma mode enable (psde1) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 1 0 primary drive 0 synchronous dma mode enable (psde0) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 0 446 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.1.23 sdma_tim?synchronous dma timing register (sata?d31:f2) address offset: 4a ? 4bh attribute: r/w default value: 0000h size: 16 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are combined. these bits have no effect on sata operation, unless otherwise noted. bit description 15:14 reserved 13:12 secondary drive 1 cycle time (sct1) ? r/w. for ultra ata mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. scb1 = 0 (33 mhz clk) scb1 = 1 (66 mhz clk) fast_scb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clks, rp 16 clks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved 11:10 reserved 9:8 secondary drive 0 cycle time (sct0) ? r/w. for ultra ata mode. the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. scb1 = 0 (33 mhz clk) scb1 = 1 (66 mhz clk) fast_scb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clks, rp 16 clks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved 7:6 reserved 5:4 primary drive 1 cycle time (pct1) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. pcb1 = 0 (33 mhz clk) pcb1 = 1 (66 mhz clk) fast_pcb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clks, rp 16 clks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved 3:2 reserved 1:0 primary drive 0 cycle time (pct0) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write strobe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. pcb1 = 0 (33 mhz clk) pcb1 = 1 (66 mhz clk) fast_pcb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks, rp 8 clocks 01 = ct 3 clks, rp 16 clks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 447 sata controller registers (d31:f2) 11.1.24 ide_config?ide i/o configuration register (sata?d31:f2) address offset: 54h ? 57h attribute: r/w default value: 00000000h size: 32 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are combined. these bits have no effect on sata operation, unless otherwise noted. bit description 31:24 reserved 23:20 scratchpad (sp2). intel ? ich5 does not perform any actions on these bits. 19:18 sec_sig_mode ? r/w. these bits are used to control mode of the secondary ide signal pins for swap bay support. if the srs bit (bit 15, offset d0h of d31:f0) is 1, the reset states of bits 19:18 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved 17:16 prim_sig_mode ? r/w. these bits are used to control mode of the primary ide signal pins for mobile swap bay support. if the prs bit (bit 14, offset d0h of d31:f0) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved 15 fast secondary drive 1 base clock (fast_scb1) ? r/w. this bit is used in conjunction with the sct1 bits to enable/disable ultra ata/100 timings for the secondary slave drive. 0 = disable ultra ata/100 timing for the secondary slave drive. 1 = enable ultra ata/100 timing for the secondary slave drive (overrides bit 3 in this register). 14 fast secondary drive 0 base clock (fast_scb0) ? r/w. this bit is used in conjunction with the sct0 bits to enable/disable ultra ata/100 timings for the secondary master drive. 0 = disable ultra ata/100 timing for the secondary master drive. 1 = enable ultra ata/100 timing for the secondary master drive (overrides bit 2 in this register). 13 fast primary drive 1 base clock (fast_pcb1) ? r/w. this bit is used in conjunction with the pct1 bits to enable/disable ultra ata/100 timings for the primary slave drive. 0 = disable ultra ata/100 timing for the primary slave drive. 1 = enable ultra ata/100 timing for the primary slave drive (overrides bit 1 in this register). 12 fast primary drive 0 base clock (fast_pcb0) ? r/w. this bit is used in conjunction with the pct0 bits to enable/disable ultra ata/100 timings for the primary master drive. 0 = disable ultra ata/100 timing for the primary master drive. 1 = enable ultra ata/100 timing for the primary master drive (overrides bit 0 in this register). 11:8 reserved 7:4 scratchpad (sp1). ich5 does not perform any action on these bits. 3 secondary drive 1 base clock (scb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings. 448 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.1.25 pid?pci power management capability identification register (sata?d31:f2) address offset: 70 ? 71h attribute: ro default value: 0001h size: 16 bits 11.1.26 pc?pci power management capabilities register (sata?d31:f2) address offset: 72 ? 73h attribute: ro default value: 0002h size: 16 bits f 2 secondary drive 0 base clock (scbo) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings. 1 primary drive 1 base clock (pcb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings. 0 primary drive 0 base clock (pcb0) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings. bit description bits description 15:8 next capability (next) ? ro. indicates that this is the last item in the list. 7:0 capability id (cid) ? ro. indicates that this pointer is a pci power management. bits description 15:11 pme support (pme_sup) ? ro. hardwired to 0s to indicate pme# cannot be generated form the sata host controller. when in low power state, resume events are not allowed. 10 d2 support (d2_sup) ? ro. hardwired to 0. the d2 state is not supported 9 d1 support (d1_sup) ? ro. hardwired to 0. the d1 state is not supported 8:6 auxiliary current (aux_cur) ? ro. hardwired to 000 to indicate 375 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi) ? ro. hardwired to 0 to indicate that no device-specific initialization is required. 4 reserved 3 pme clock (pme_clk) ? ro. hardwired to 0 to indicate that pci clock is not required to generate pme#. 2:0 version (ver) ? ro. hardwired to 010 to indicates support for the pci power management specification, revision 1.1 . intel ? 82801eb ich5 / 82801er ich5r datasheet 449 sata controller registers (d31:f2) 11.1.27 pmcs?pci power management control and status register (sata?d31:f2) address offset: 74 ? 75h attribute: ro, r/w default value: 0000h size: 16 bits 11.1.28 mid?message signaled interrupt identifiers register (sata?d31:f2) address offset: 80 ? 81h attribute: ro default value: 7005h size: 16 bits bits description 15 pme status (pmes) ? ro. reserved as 0. 14:9 reserved 8 pme enable (pmee) ? ro. reserved as 0. 7:2 reserved 1:0 power state (ps) ? r/w. these bits are used both to determine the current power state of the sata controller and to set a new power state. 00 = d0 state 01 = d1 state 10 = d2 state 11 = d3hot state when in the d3hot state, the controller?s configuration space is available, but the i/o and memory spaces are not. additionally, interrupts are blocked. bits description 15:8 next pointer (next) ? ro. this field indicates that the next item in the list the pci power management pointer. 7:0 capability id (cid) ? ro. the capabilities id indicates msi. 450 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.1.29 mc?message signaled interrupt message control register (sata?d31:f2) address offset: 82 ? 83h attribute: ro, r/w default value: 0000h size: 16 bits 11.1.30 ma?message signaled interrupt message address register (sata?d31:f2) address offset: 84 ? 87h attribute: r/w default value: 00000000h size: 32 bits 11.1.31 md?message signaled interrupt message data register (sata?d31:f2) address offset: 88 ? 89h attribute: r/w default value: 0000h size: 16 bits bits description 15:8 reserved 7 64 bit address capable (c64) ? ro. hardwired to 0 to indicate capability of generating 32-bit message only. 6:4 multiple message enable (mme) ? r/w. these bits are r/w for software compatibility, but only one message is ever sent by intel ? ich5. 3:1 multiple message capable (mmc) ? ro. only one message is required. 0 msi enable (msie) ? r/w. 0 = disabled. 1 = msi is enabled and traditional interrupt pins are not used to generate interrupts. bits description 31:2 address (addr) ? r/w. lower 32 bits of the system specified message address, always dword aligned. 1:0 reserved bits description 15:0 data (data) ? r/w. this field is programmed by system software if msi is enabled. its content is driven onto the lower word (pci ad[15:0]) during the data phase of the msi memory write transaction. intel ? 82801eb ich5 / 82801er ich5r datasheet 451 sata controller registers (d31:f2) 11.1.32 map?address map register (sata?d31:f2) address offset: 90h attribute: r/w default value: 00h size: 8 bits 11.1.33 pcs?port control and status register (sata?d31:f2) address offset: 92h ? 93h attribute: r/w, ro default value: 0000h size: 16 bits bits description 7:3 reserved. 2:0 map value ? r/w. the value of these bits indicate the address range the sata port responds to, and whether or not the sata and ide functions are combined. 000 = non-combined. p0 is primary master. p1 is secondary master. 001 = non-combined. p0 is secondary master. p1 is primary master. 100 = combined. p0 is primary master. p1 is primary slave. ide is secondary; primary ide channel disabled. 101 = combined. p0 is primary slave. p1 is primary master. ide is secondary. 110 = combined. ide is primary. p0 is secondary master. p1 is secondary slave; secondary ide channel disabled. 111 = combined. ide is primary. p0 is secondary slave. p1 is secondary master. bits description 15:6 reserved. 5 port 1 present (p1p) ? ro. 0 = device not detected. this bit is cleared when the port is disabled via the p1e bit (bit 1 of this register). 1 = device present. the sata host has detected the presence of a device on port 1. it may change at any time. note: sata device presence detection is dependant on the amount of time a device needs to prepare to be detected. device preparation time is device-specific, and is not specified. 4 port 0 present (p0p) ? ro. 0 = device not detected.this bit is cleared when the port is disabled via the p0e bit (bit 0 of this register). 1 = device present. the sata host has detected the presence of a device on port 1. it may change at any time. note: sata device presence detection is dependant on the amount of time a device needs to prepare to be detected. device preparation time is device-specific, and is not specified. 3:2 reserved. 1 port 1 enabled (p1e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. 0 port 0 enabled (p0e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices 452 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.1.34 sri?sata registers index (sata?d31:f2) address offset: a0h attribute: r/w default value: 00h size: 8 bits 11.1.35 srd?sata registers data (sata?d31:f2) address offset: a4h?a7h attribute: r/w default value: xxh size: 8 bits 11.1.36 sira?sata initialization register a (sata?d31:f2) index address: index 18h?1bh attribute: r/w default value: 0000025bh size: 32 bits bits description 7 reserved. 6:0 index (idx) ? r/w. this field is a 7-bit index pointer into the sata registers space. data is written into the srd register (d31:f2:a4h) and read from the srd register. table 157. sata indexed registers index name 00h?17h reserved 18h?1bh sata initialization register a (sira) 1ch?3fh reserved 40h?43h sata initialization register b (sirb) 44h?57h reserved 58h?5bh power management register port 0 (pmr0) 5ch?67h reserved 68h?6bh power management register port 1 (pmr1) 6ch?ffh reserved bits description 31:0 data (dta) ? r/w. this field is a 32-bit data value that is written to the register pointed to by sri (d31:f2:a0h) or read from the register pointed to by sri. bit description 31:8 reserved 7:0 sata setup data a (ssda) ? r/w. this field is written by bios during sata initialization. contact your intel field representative for additional bios information. intel ? 82801eb ich5 / 82801er ich5r datasheet 453 sata controller registers (d31:f2) 11.1.37 sirb ? sata initialization register b (sata?d31:f2) index address: index 40h?43h attribute: r/w default value: 0011017dh size: 32 bits 11.1.38 pmr0 ? power management register port 0 (sata?d31:f2) index offset: index 58h?5bh attribute: r/w default value: xxxxxxxxh size: 32 bits 11.1.39 pmr1 ? power management register port 1 (sata?d31:f2) index offset: index 68h?6bh attribute: r/w default value: xxxxxxxxh size: 32 bits bit description 31:24 reserved 23:16 sata setup data b (ssdb) ? r/w. this field is written by bios during sata initialization. contact your intel field representative for additional bios information. 15:0 reserved bits description 31:16 reserved 15:8 device partial/slumber request port 0 ? r/w. the intel ? ich5 port 0 configuration to respond to device-initiated requests to transition to partial/slumber power management states. note: bios must program this field to 03h. 7:0 reserved bits description 31:16 reserved 15:8 device partial/slumber request port 1 ? r/w. the intel ? ich5 port 1 configuration to respond to device-initiated requests to transition to partial/slumber power management states. note: bios must program this field to 03h. 7:0 reserved 454 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.1.40 bfcs?bist fis control/status register (sata?d31:f2) address offset: e0h ? e3h attribute: r/w, r/wc default value: 00000000h size: 32 bits bits description 31:12 reserved 11 bist fis successful (bfs) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a bist fis transmitted by intel ? ich5 receives an r_ok completion status from the device. note: this bit must be cleared by software prior to initiating a bist fis. 10 bist fis failed (bff) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a bist fis transmitted by ich5 receives an r_err completion status from the device. note: this bit must be cleared by software prior to initiating a bist fis. 9 port 1 bist fis initiate (p1bfi) ? r/w. when a rising edge is detected on this bit field, the ich5 initiates a bist fis to the device on port 1, using the parameters specified in this register and the data specified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 1 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re-enable the port using the pxe bits at offset 92h prior to attempting additional bist fises or to return the ich5 to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p1bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully. 8 port 0 bist fis initiate (p0bfi) ? r/w. when a rising edge is detected on this bit field, the ich5 initiates a bist fis to the device on port 0, using the parameters specified in this register and the data specified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 0 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re-enable the port using the pxe bits at offset 92h prior to attempting additional bist fises or to return the ich5 to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p0bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully. 7:2 bist fis parameters. these 6 bits form the contents of the upper 6 bits of the bist fis pattern definition in any bist fis transmitted by the ich5. this field is not port specific ? its contents will be used for any bist fis initiated on port 0 on port 1. the specific bit definitions are: bit 7: t ? far end transmit mode bit 6: a ? align bypass mode bit 5: s ? bypass scrambling bit 4: l ? far end retimed loopback bit 3: f ? far end analog loopback bit 2: p ? primitive bit for use with transmit mode 1:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 455 sata controller registers (d31:f2) 11.1.41 bftd1?bist fis transmit data1 register (sata?d31:f2) address offset: e4h ? e7h attribute: r/w default value: 00000000h size: 32 bits 11.1.42 bftd2?bist fis transmit data2 register (sata?d31:f2) address offset: e8h ? ebh attribute: r/w default value: 00000000h size: 32 bits bits description 31:0 bist fis transmit data 1 ? r/w. the data programmed into this register will form the contents of the second dword of any bist fis initiated by the intel ? ich5. this register is not port specific ? its contents will be used for bist fis initiated on port 0 or port 1. although the 2nd and 3rd dws of the bist fis are only meaningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 2nd dw regardless of whether or not the ?t? bit is indicated in the bfcs register. bits description 31:0 bist fis transmit data 2 ? r/w. the data programmed into this register will form the contents of the third dword of any bist fis initiated by the intel ? ich5. this register is not port specific ? its contents will be used for bist fis initiated on port 0 or port 1. although the 2nd and 3rd dws of the bist fis are only meaningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 3rd dw regardless of whether or not the ?t? bit is indicated in the bfcs register. 456 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.2 bus master ide i/o registers (d31:f2) the bus master ide function uses 16 bytes of i/o space, allocated via the bmiba register, located in device 31:function 1 configuration space, offset 20h. all bus master ide i/o space registers can be accessed as byte, word, or dword quantities. reading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). the description of the i/o registers is shown in table 158 . table 158. bus master ide i/o register address map offset mnemonic register name default type 00 bmicp command register primary 01h r/w 01 ? reserved ? ro 02 bmisp bus master ide status register primary 00h r/w, r/wc, ro 03 ? reserved ? ro 04?07 bmidp bus master ide descriptor table pointer primary xx r/w 08 bmics command register secondary 01h r/w 09 ? reserved ? ro 0a bmiss bus master ide status register secondary 00h r/w, r/wc, ro 0b ? reserved ? ro 0c?0f bmids bus master ide descriptor table pointer secondary xx r/w intel ? 82801eb ich5 / 82801er ich5r datasheet 457 sata controller registers (d31:f2) 11.2.1 bmic[p,s]?bus master ide command register (d31:f2) address offset: primary: 00h attribute: r/w secondary: 08h default value: 01h size: 8 bits bit description 7:4 reserved. returns 0. 3 read / write control (rwc) ? r/w. this bit sets the direction of the bus master transfer: this bit must not be changed when the bus master function is active. 0 = memory reads 1 = memory writes 2:1 reserved. returns 0. 0 start/stop bus master (start) ? r/w. 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. if this bit is reset while bus master operation is still active (i.e., the bus master ide active bit of the bus master ide status register for that ide channel is set) and the drive has not yet finished its data transfer (the interrupt bit in the bus master ide status register for that ide channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the controller. bus master operation does not actually start unless the bus master enable bit (d31:f1: offset 04h, bit 2) in pci configuration space is also set. bus master operation begins when this bit is detected changing from 0 to 1. the controller will transfer data between the ide device and memory only when this bit is set. master operation can be halted by writing a 0 to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bus master ide active bit being cleared or the interrupt bit of the bus master ide status register for that ide channel being set, or both. hardware does not clear this bit automatically. 458 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) 11.2.2 bmis[p,s]?bus master ide status register (d31:f2) address offset: primary: 02h attribute: r/w, r/wc, ro secondary: 0ah default value: 00h size: 8 bits bit description 7 prd interrupt status (prdis) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the host controller execution of a prd that has its prd_int bit set. 6 drive 1 dma capable ? r/w. 0 = not capable. 1 = capable. set by device dependent code (bios or device driver) to indicate that drive 1 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the intel ? ich5 does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 5 drive 0 dma capable ? r/w. 0 = not capable. 1 = capable. set by device dependent code (bios or device driver) to indicate that drive 0 for this channel is capable of dma transfers, and that the controller has been initialized for optimum performance. the ich5 does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 4:3 reserved. returns 0. 2 interrupt ? r/wc. software can use this bit to determine if an ide device has asserted its interrupt line (irq 14 for the primary channel, and irq 15 for secondary). 0 = software clears this bit by writing a 1 to it. if this bit is cleared while the interrupt is still active, this bit will remain clear until another assertion edge is detected on the interrupt line. 1 = set by the rising edge of the ide interrupt line, regardless of whether or not the interrupt is masked in the 8259 or the internal i/o apic. when this bit is read as a 1, all data transferred from the drive is visible in system memory. 1 error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the controller encounters a target abort or master abort when transferring data on pci. 0 bus master ide active (act) ? ro. 0 = this bit is cleared by the ich5 when the last transfer for a region is performed, where eot for that region is set in the region descriptor. it is also cleared by the ich5 when the start bit is cleared in the command register. when this bit is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = set by the ich5 when the start bit is written to the command register. intel ? 82801eb ich5 / 82801er ich5r datasheet 459 sata controller registers (d31:f2) 11.2.3 bmid[p,s]?bus master ide descriptor table pointer register (d31:f2) address offset: primary: 04h ? 07h attribute: r/w secondary: 0ch ? 0fh default value: all bits undefined size: 32 bits bit description 31:2 address of descriptor table (addr) ? r/w. the bits in this field correspond to a[31:2]. the descriptor table must be dword-aligned. the descriptor table must not cross a 64-k boundary in memory. 1:0 reserved 460 intel ? 82801eb ich5 / 82801er ich5r datasheet sata controller registers (d31:f2) this page is intentionally left blank. intel ? 82801eb ich5 / 82801er ich5r datasheet 461 uhci controllers registers uhci controllers registers 12 12.1 pci configuration registers (usb?d29:f0/f1/f2/f3) note: register address locations that are not shown in table 159 and should be treated as reserved (see section 6.2 for details). note: refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. table 159. uhci controller pci register address map (usb?d29:f0/f1/f2/f3) offset mnemonic register name function 0 default function 1 default function 2 default function 3 default type 00?01h vid vendor identification 8086h 8086h 8086h 8086h ro 02?03h did device identification 24d2h 24d4h 24d7h 24deh ro 04?05h pcicmd pci command 0400h 0400h 0400h 0400h r/w, ro 06?07h pcists pci status 0280h 0280h 0280h 0280h r/wc, ro 08h rid revision identification see register description see register description see register description see register description ro 09h pi programming interface 00h 00h 00h 00h ro 0ah scc sub class code 03h 03h 03h 03h ro 0bh bcc base class code 0ch 0ch 0ch 0ch ro 0eh headtyp header type 80h 00h 00h 00h ro 20?23h base base address 00000001h 00000001h 00000001h 00000001h r/w, ro 2c?2dh svid subsystem vendor identification 0000h 0000h 0000h 0000h ro 2e?2fh sid subsystem identification 0000h 0000h 0000h 0000h ro 3ch int_ln interrupt line 00h 00h 00h 00h r/w 3dh int_pn interrupt pin 01h 02h 03h 01h ro 60h usb_relnum serial bus release number 10h 10h 10h 10h ro c0?c1h usb_legkey usb legacy keyboard/ mouse control 2000h 2000h 2000h 2000h r/w, ro r/wc c4h usb_res usb resume enable 00h 00h 00h 00h r/w 462 intel ? 82801eb ich5 / 82801er ich5r datasheet uhci controllers registers 12.1.1 vid?vendor identification register (usb?d29:f0/f1/f2/f3) address offset: 00 ? 01h attribute: ro default value: 8086h size: 16 bits 12.1.2 did?device identification register (usb?d29:f0/f1/f2/f3) address offset: 02 ? 03h attribute: ro default value: uhci #1 = 24d2h size: 16 bits uhci #2 = 24d4h uhci #3 = 24d7h uhci #4 = 24deh 12.1.3 pcicmd?pci command register (usb?d29:f0/f1/f2/f3) address offset: 04 ? 05h attribute: r/w, ro default value: 0400h size: 16 bits bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich5 usb host controllers bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = enable. the function is able to generate its interrupt to the interrupt controller. 1 = disable. the function is not capable of generating interrupts. note: the corresponding interrupt status bit is not affected by the interrupt enable. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable ? ro. reserved as 0. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? ro. hardwired to 0. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. 0 = disable 1 = enable. intel ? ich5 can act as a master on the pci bus for usb transfers. 1 memory space enable (mse) ? ro. hardwired to 0. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disable 1 = enable accesses to the usb i/o registers. the base address register for usb should be programmed before this bit is set. intel ? 82801eb ich5 / 82801er ich5r datasheet 463 uhci controllers registers 12.1.4 pcists?pci status register (usb?d29:f0/f1/f2/f3) address offset: 06 ? 07h attribute: r/wc, ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 12.1.5 rid?revision identification register (usb?d29:f0/f1/f2/f3) address offset: 08h attribute: ro default value: see bit description size: 8 bits bit description 15:14 reserved as 00b. read only. 13 received master abort (rma) ? r/wc. 0 = no master abort generated by usb. 1 = usb, as a master, generated a master abort. 12 reserved. always read as 0. 11 signaled target abort (sta) ? r/wc. 0 = intel ? ich5 did not terminate transaction for usb function with a target abort. 1 = usb function is targeted with a transaction that the ich5 terminates with a target abort. 10:9 devsel# timing status (dev_sts) ? ro. this 2-bit field defines the timing for devsel# assertion. these read only bits indicate the ich5's devsel# timing when performing a positive decode. ich5 generates devsel# with medium timing for usb. 8 data parity error detected (dped) ? ro. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (udf) ? ro. hardwired to 0. 5 66 mhz capable ? ro. hardwired to 0. 4 capabilities list ? ro. hardwired to 0. 3 interrupt status ? ro. this bit reflects the state of this function?s interrupt at the input of the enable/disable logic. 0 = interrupt is deasserted. 1 = interrupt is asserted. the value reported in this bit is independent of the value in the interrupt enable bit. 2:0 reserved bit description 7:0 revision id ? ro.these bits contain device stepping information and are hardwired to the default value. note: refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. 464 intel ? 82801eb ich5 / 82801er ich5r datasheet uhci controllers registers 12.1.6 pi?programming interface register (usb?d29:f0/f1/f2/f3) address offset: 09h attribute: ro default value: 00h size: 8 bits 12.1.7 scc?sub class code register (usb?d29:f0/f1/f2/f3) address offset: 0ah attribute: ro default value: 03h size: 8 bits 12.1.8 bcc?base class code register (usb?d29:f0/f1/f2/f3) address offset: 0bh attribute: ro default value: 0ch size: 8 bits bit description 7:0 programming interface ? ro. 00h = no specific register level programming interface defined. bit description 7:0 sub class code (scc) ? ro. 03h = usb host controller. bit description 7:0 base class code (bcc) ? ro. 0ch = serial bus controller. intel ? 82801eb ich5 / 82801er ich5r datasheet 465 uhci controllers registers 12.1.9 headtyp?header type register (usb?d29:f0/f1/f2/f3) address offset: 0eh attribute: ro default value: fn 0: 80h size: 8 bits fn 1: 00h fn 2: 00h fn 3: 00h for functions 1, 2, and 3, this register is hardwired to 00h. for function 0, bit 7 is determined by the values in bits 15, 10, and 9 of the function disable register (d31:f0:f2h). 12.1.10 base?base address register (usb?d29:f0/f1/f2/f3) address offset: 20 ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits bit description 7 multi-function device ? ro. 0 = single-function device. 1 = multi-function device. since the upper functions in this device can be individually hidden, this bit is based on the function- disable bits in device 31, function 0, offset f2h as follows: d29:f7_disable d29:f3_disable d29:f2_disable d29:f1_disable multi-function bit (bit 15) (bit 11) (bit 10) (bit 9) 0 x x x 1 x 0 x x 1 x x 0 x 1 x x x 0 1 1 1 1 1 0 6:0 configuration layout. hardwired to 00h, which indicates the standard pci configuration layout. bit description 31:16 reserved 15:5 base address ? r/w. bits [15:5] correspond to i/o address signals ad [15:5], respectively. this gives 32 bytes of relocatable i/o space. 4:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate that the base address field in this register maps to i/o space. 466 intel ? 82801eb ich5 / 82801er ich5r datasheet uhci controllers registers 12.1.11 svid ? subsystem vendor identification register (usb?d29:f0/f1/f2/f3) address offset: 2ch ? 2dh attribute: ro default value: 0000h size: 16 bits lockable: no power well: core 12.1.12 sid ? subsystem identification register (usb?d29:f0/f1/f2/f3) address offset: 2eh ? 2fh attribute: ro default value: 0000h size: 16 bits lockable: no power well: core 12.1.13 int_ln?interrupt line register (usb?d29:f0/f1/f2/f3) address offset: 3ch attribute: r/w default value: 00h size: 8 bits bit description 15:0 subsystem vendor id (svid) ? ro. the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide svid register. bit description 15:0 subsystem id (sid) ? ro. the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide sid register. bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich5. it is to communicate to software the interrupt line that the interrupt pin is connected to. intel ? 82801eb ich5 / 82801er ich5r datasheet 467 uhci controllers registers 12.1.14 int_pn?interrupt pin register (usb?d29:f0/f1/f2/f3) address offset: 3dh attribute: ro default value: function 0: 01h size: 8 bits function 1: 02h function 2: 03h function 3: 01h 12.1.15 usb_relnum?serial bus release number register (usb?d29:f0/f1/f2/f3) address offset: 60h attribute: ro default value: 10h size: 8 bits bit description 7:3 reserved 2:0 interrupt pin (int_pn) ? ro. the values of 01h, 02h, 03h, and 01h in function 0, 1, 2, and 3 respectively, indicate to software that the corresponding intel ? ich5 classic usb controllers drive the inta#, intb#, intc#, and inta# pci signals. note that this does not determine the mapping to the ich5 pirq inputs. function 0 drives pirqa; function 1 drives pirqd; function 2 drives pirqc; function 3 drives pirqa. bit description 7:0 serial bus release number ? ro. 10h = usb controller is compliant with the universal serial bus revision 2.0 specification . 468 intel ? 82801eb ich5 / 82801er ich5r datasheet uhci controllers registers 12.1.16 usb_legkey?usb legacy keyboard/mouse control register (usb?d29:f0/f1/f2/f3) address offset: c0 ? c1h attribute: r/w, r/wc, ro default value: 2000h size: 16 bits this register is implemented separately in each of the usb uhci functions. however, the enable and status bits for the trapping logic are or?d and shared, respectively, since their functionality is not specific to any one host controller. bit description 15 smi caused by end of pass-through (smibyendps) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in bit 7, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred 14 reserved 13 pci interrupt enable (usbpirqen) ? r/w. this bit is used to prevent the usb controller from generating an interrupt due to transactions on its ports. note that, when disabled, it will probably be configured to generate an smi using bit 4 of this register. default to 1 for compatibility with older usb software. 0 = disable 1 = enable 12 smi caused by usb interrupt (smibyusb) ? ro. this bit indicates if an interrupt event occurred from this controller. the interrupt from the controller is taken before the enable in bit 13 has any effect to create this read-only bit. note that even if the corresponding enable bit is not set in bit 4, this bit may still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software should clear the interrupts via the usb controllers. writing a 1 to this bit will have no effect. 1 = event occurred. 11 smi caused by port 64 write (trapby64w) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in bit 3, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. note that the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 10 smi caused by port 64 read (trapby64r) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in bit 2, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 9 smi caused by port 60 write (trapby60w) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in bit 1, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. note that the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 8 smi caused by port 60 read (trapby60r) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. intel ? 82801eb ich5 / 82801er ich5r datasheet 469 uhci controllers registers 7 smi at end of pass-through enable (smiatendps) ? r/w. this bit enables smi at the end of a pass-through. this can occur if an smi is generated in the middle of a pass-through, and needs to be serviced later. 0 = disable 1 = enable 6 pass through state (pstate) ? ro. 0 = if software needs to reset this bit, it should set bit 5 in all of the host controllers to 0. 1 = indicates that the state machine is in the middle of an a20gate pass-through sequence. 5 a20gate pass-through enable (a20passen) ? r/w. 0 = disable 1 = enable. allows a20gate sequence pass-through function. a specific cycle sequence involving writes to port 60h and 64h does not result in the setting of the smi status bits. 4 smi on usb irq enable (usbsmien) ? r/w. 0 = disable 1 = enable. usb interrupt will cause an smi event. 3 smi on port 64 writes enable (64wen) ? r/w. 0 = disable 1 = enable. a 1 in bit 11 will cause an smi event. 2 smi on port 64 reads enable (64ren) ? r/w. 0 = disable 1 = enable. a 1 in bit 10 will cause an smi event. 1 smi on port 60 writes enable (60wen) ? r/w. 0 = disable 1 = enable. a 1 in bit 9 will cause an smi event. 0 smi on port 60 reads enable (60ren) ? r/w. 0 = disable 1 = enable. a 1 in bit 8 will cause an smi event. bit description 470 intel ? 82801eb ich5 / 82801er ich5r datasheet uhci controllers registers 12.1.17 usb_res?usb resume enable register (usb?d29:f0/f1/f2/f3) address offset: c4h attribute: r/w default value: 00h size: 8 bits 12.2 usb i/o registers some of the read/write register bits that deal with changing the state of the usb hub ports function such that on read back they reflect the current state of the port, and not necessarily the state of the last write to the register. this allows the software to poll the state of the port and wait until it is in the proper state before proceeding. a host controller reset, global reset, or port reset will immediately terminate a transfer on the affected ports and disable the port. this affects the usbcmd register, bit 4 and the portsc registers, bits [12,6,2]. see individual bit descriptions for more detail. notes: 1. these registers are word writable only. byte writes to these registers have unpredictable effects. bit description 7:2 reserved 1 port1en ? r/w. enable port 1 of the usb controller to respond to wakeup events. 0 = the usb controller will not look at this port for a wakeup event. 1 = the usb controller will monitor this port for remote wakeup and connect/disconnect events. 0 port0en ? r/w. enable port 0 of the usb controller to respond to wakeup events. 0 = the usb controller will not look at this port for a wakeup event. 1 = the usb controller will monitor this port for remote wakeup and connect/disconnect events. table 160. usb i/o registers offset mnemonic register name default type 00?01 usbcmd usb command 0000h r/w 02?03 usbsts usb status 0020h r/wc 04?05 usbintr usb interrupt enable 0000h r/w 06?07 frnum frame number 0000h r/w (see note 1) 08?0b frbaseadd frame list base address undefined r/w 0c sofmod start of frame modify 40h r/w 0d?0f ? reserved ? ? 10?11 portsc0 port 0 status/control 0080h r/wc, ro, r/w (see note 1) 12?13 portsc1 port 1 status/control 0080h r/wc, ro, r/w (see note 1) 14?17 ? reserved ? ? 18h loopdata loop back test data 00h ro intel ? 82801eb ich5 / 82801er ich5r datasheet 471 uhci controllers registers 12.2.1 usbcmd?usb command register i/o offset: base + (00 ? 01h) attribute: r/w default value: 0000h size: 16 bits the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. the table following the bit description provides additional information on the operation of the run/stop and debug bits. bit description 15:7 reserved 8 loop back test mode ? r/w. 0 = disable loop back test mode. 1 = intel ? ich5 is in loop back test mode. when both ports are connected together, a write to one port will be seen on the other port and the data will be stored in i/o offset 18h. 7 max packet (maxp) ? r/w. this bit selects the maximum packet size that can be used for full speed bandwidth reclamation at the end of a frame. this value is used by the host controller to determine whether it should initiate another transaction based on the time remaining in the sof counter. use of reclamation packets larger than the programmed size will cause a babble error if executed during the critical window at frame end. the babble error results in the offending endpoint being stalled. software is responsible for ensuring that any packet which could be executed under bandwidth reclamation be within this size limit. 0 = 32 bytes 1 = 64 bytes 6 configure flag (cf) ? r/w. this bit has no effect on the hardware. it is provided only as a semaphore service for software. 0 = indicates that software has not completed host controller configuration. 1 = hcd software sets this bit as the last action in its process of configuring the host controller. 5 software debug (swdbg) ? r/w. the swdbg bit must only be manipulated when the controller is in the stopped state. this can be determined by checking the hchalted bit in the usbsts register. 0 = normal mode. 1 = debug mode. in sw debug mode, the host controller clears the run/stop bit after the completion of each usb transaction. the next transaction is executed when software sets the run/stop bit back to 1. 4 force global resume (fgr) ? r/w. 0 = software resets this bit to 0 after 20 ms has elapsed to stop sending the global resume signal. at that time all usb devices should be ready for bus activity. the 1 to 0 transition causes the port to send a low speed eop signal. this bit will remain a 1 until the eop has completed. 1 = host controller sends the global resume signal on the usb, and sets this bit to 1 when a resume event (connect, disconnect, or k-state) is detected while in global suspend mode. 3 enter global suspend mode (egsm) ? r/w. 0 = software resets this bit to 0 to come out of global suspend mode. software writes this bit to 0 at the same time that force global resume (bit 4) is written to 0 or after writing bit 4 to 0. 1 = host controller enters the global suspend mode. no usb transactions occur during this time. the host controller is able to receive resume signals from usb and interrupt the system. software must ensure that the run/stop bit (bit 0) is cleared prior to setting this bit. 472 intel ? 82801eb ich5 / 82801er ich5r datasheet uhci controllers registers 2 global reset (greset) ? r/w. 0 = this bit is reset by the software after a minimum of 10 ms has elapsed as specified in chapter 7 of the universal serial bus revision 2.0 specification . 1 = global reset. the host controller sends the global reset signal on the usb and then resets all its logic, including the internal hub registers. the hub registers are reset to their power on state. chip hardware reset has the same effect as global reset (bit 2), except that the host controller does not send the global reset on usb. 1 host controller reset (hcreset) ? r/w. the effects of hcreset on hub registers are slightly different from chip hardware reset and global usb reset. the hcreset affects bits [8,3:0] of the port status and control register (portsc) of each port. hcreset resets the state machines of the host controller including the connect/disconnect state machine (one for each port). when the connect/disconnect state machine is reset, the output that signals connect/disconnect are negated to 0, effectively signaling a disconnect, even if a device is attached to the port. this virtual disconnect causes the port to be disabled. this disconnect and disabling of the port causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the portsc to get set. the disconnect also causes bit 8 of portsc to reset. about 64 bit times after hcreset goes to 0, the connect and low-speed detect will take place, and bits 0 and 8 of the portsc will change accordingly. 0 = reset by the host controller when the reset process is complete. 1 = reset. when this bit is set, the host controller module resets its internal timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediately terminated. 0 run/stop (rs) ? r/w. when set to 1, the ich5 proceeds with execution of the schedule. the ich5 continues execution as long as this bit is set. when this bit is cleared, the ich5 completes the current transaction on the usb and then halts. the hc halted bit in the status register indicates when the host controller has finished the transaction and has entered the stopped state. the host controller clears this bit when the following fatal errors occur: consistency check failure, pci bus errors. 0 = stop 1 = run note: this bit should only be cleared if there are no active transaction descriptors in the executable schedule or software will reset the host controller prior to setting this bit again. bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 473 uhci controllers registers when the usb host controller is in software debug mode (usbcmd register bit 5=1), the single stepping software debug operation is as follows: to enter software debug mode: 1. hcd puts host controller in stop state by setting the run/stop bit to 0. 2. hcd puts host controller in debug mode by setting the swdbg bit to 1. 3. hcd sets up the correct command list and start of frame value for starting point in the frame list single step loop. 4. hcd sets run/stop bit to 1. 5. host controller executes next active td, sets run/stop bit to 0, and stops. 6. hcd reads the usbcmd register to check if the single step execution is completed (hchalted=1). 7. hcd checks results of td execution. go to step 4 to execute next td or step 8 to end software debug mode. 8. hcd ends software debug mode by setting swdbg bit to 0. 9. hcd sets up normal command list and frame list table. 10. hcd sets run/stop bit to 1 to resume normal schedule execution. in software debug mode, when the run/stop bit is set, the host controller starts. when a valid td is found, the run/stop bit is reset. when the td is finished, the hchalted bit in the usbsts register (bit 5) is set. the sw debug mode skips over inactive tds and only halts after an active td has been executed. when the last active td in a frame has been executed, the host controller waits until the next sof is sent and then fetches the first td of the next frame before halting. this hchalted bit can also be used outside of software debug mode to indicate when the host controller has detected the run/stop bit and has completed the current transaction. outside of the software debug mode, setting the run/stop bit to 0 always resets the sof counter so that when the run/stop bit is set the host controller starts over again from the frame list location pointed to by the frame list index (see frnum register description) rather than continuing where it stopped. table 161. run/stop, debug bit interaction swdbg (bit 5), run/stop (bit 0) operation swdbg (bit 5) run/stop (bit 0) description 00 if executing a command, the host controller completes the command and then stops. the 1.0 ms frame counter is reset and command list execution resumes from start of frame using the frame list pointer selected by the current value in the frnum register. (while run/stop=0, the frnum register can be reprogrammed). 01 execution of the command list resumes from start of frame using the frame list pointer selected by the current value in the frnum register. the host controller remains running until the run/stop bit is cleared (by software or hardware). 10 if executing a command, the host controller completes the command and then stops and the 1.0 ms frame counter is frozen at its current value. all status are preserved. the host controller begins execution of the command list from where it left off when the run/stop bit is set. 11 execution of the command list resumes from where the previous execution stopped. the run/stop bit is set to 0 by the host controller when a td is being fetched. this causes the host controller to stop again after the execution of the td (single step). when the host controller has completed execution, the hc halted bit in the status register is set. 474 intel ? 82801eb ich5 / 82801er ich5r datasheet uhci controllers registers 12.2.2 usbsts?usb status register i/o offset: base + (02 ? 03h) attribute: r/wc default value: 0020h size: 16 bits this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. bit description 15:6 reserved 5 hchalted ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the host controller has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (debug mode or an internal error). default. 4 host controller process error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the host controller has detected a fatal error. this indicates that the host controller suffered a consistency check failure while processing a transfer descriptor. an example of a consistency check failure would be finding an illegal pid field while processing the packet header portion of the td. when this error occurs, the host controller clears the run/stop bit in the command register to prevent further schedule execution. a hardware interrupt is generated to the system. 3 host system error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = a serious error occurred during a host system access involving the host controller module. in a pci system, conditions that set this bit to 1 include pci parity error, pci master abort, and pci target abort. when this error occurs, the host controller clears the run/stop bit in the command register to prevent further execution of the scheduled tds. a hardware interrupt is generated to the system. 2 resume detect (rsm_det) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the host controller received a ?resume? signal from a usb device. this is only valid if the host controller is in a global suspend state (bit 3 of command register = 1). 1 usb error interrupt ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = completion of a usb transaction resulted in an error condition (e.g., error counter underflow). if the td on which the error interrupt occurred also had its ioc bit set, both this bit and bit 0 are set. 0 usb interrupt (usbint) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the host controller sets this bit when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. also set when a short packet is detected (actual length field in td is less than maximum length field in td), and short packet detection is enabled in that td. intel ? 82801eb ich5 / 82801er ich5r datasheet 475 uhci controllers registers 12.2.3 usbintr?usb interrupt enable register i/o offset: base + (04 ? 05h) attribute: r/w default value: 0000h size: 16 bits this register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. fatal errors (host controller processor error-bit 4, usbsts register) cannot be disabled by the host controller. interrupt sources that are disabled in this register still appear in the status register to allow the software to poll for events. 12.2.4 frnum?frame number register i/o offset: base + (06 ? 07h) attribute: r/w (writes must be word writes) default value: 0000h size: 16 bits bits [10:0] of this register contain the current frame number that is included in the frame sof packet. this register reflects the count value of the internal frame number counter. bits [9:0] are used to select a particular entry in the frame list during scheduled execution. this register is updated at the end of each frame time. this register must be written as a word. byte writes are not supported. this register cannot be written unless the host controller is in the stopped state as indicated by the hchalted bit (usbsts register). a write to this register while the run/stop bit is set (usbcmd register) is ignored. bit description 15:4 reserved 3 short packet interrupt enable ? r/w. 0 = disabled. 1 = enabled. 2 interrupt on complete enable (ioc) ? r/w. 0 = disabled. 1 = enabled. 1 resume interrupt enable ? r/w. 0 = disabled. 1 = enabled. 0 timeout/crc interrupt enable ? r/w. 0 = disabled. 1 = enabled. bit description 15:11 reserved 10:0 frame list current index/frame number ? r/w. this field provides the frame number in the sof frame. the value in this register increments at the end of each time frame (approximately every 1 ms). in addition, bits [9:0] are used for the frame list current index and correspond to memory address signals [11:2]. 476 intel ? 82801eb ich5 / 82801er ich5r datasheet uhci controllers registers 12.2.5 frbaseadd?frame list base address register i/o offset: base + (08 ? 0bh) attribute: r/w default value: undefined size: 32 bits this 32-bit register contains the beginning address of the frame list in the system memory. hcd loads this register prior to starting the schedule execution by the host controller. when written, only the upper 20 bits are used. the lower 12 bits are written as 0s (4-kb alignment). the contents of this register are combined with the frame number counter to enable the host controller to step through the frame list in sequence. the two least significant bits are always 00. this requires dword alignment for all list entries. this configuration supports 1024 frame list entries. 12.2.6 sofmod?start of frame modify register i/o offset: base + (0ch) attribute: r/w default value: 40h size: 8 bits this 1-byte register is used to modify the value used in the generation of sof timing on the usb. only the seven, least significant bits are used. when a new value is written into these seven bits, the sof timing of the next frame will be adjusted. this feature can be used to adjust out any offset from the clock source that generates the clock that drives the sof counter. this register can also be used to maintain real time synchronization with the rest of the system so that all devices have the same sense of real time. using this register, the frame length can be adjusted across the full range required by the universal serial bus revision 2.0 specification . its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. it may be reprogrammed by usb system software at any time. its value will take effect from the beginning of the next frame. this register is reset upon a host controller reset or global reset. software must maintain a copy of its value for reprogramming if necessary. bit description 31:12 base address ? r/w. these bits correspond to memory address signals [31:12], respectively. 11:0 reserved bit description 7 reserved 6:0 sof timing value ? r/w. guidelines for the modification of frame time are contained in chapter 7 of the universal serial bus revision 2.0 specification . the sof cycle time (number of sof counter clock periods to generate a sof frame length) is equal to 11936 + value in this field. the default value is decimal 64 which gives a sof cycle time of 12000. for a 12 mhz sof counter clock input, this produces a 1 ms frame period. the following table indicates what sof timing value to program into this field for a certain frame period. frame length (# 12 mhz clocks) sof reg. value (decimal) (decimal) 11936 0 11937 1 .. .. 11999 63 12000 64 12001 65 .. .. 12062 126 12063 127 intel ? 82801eb ich5 / 82801er ich5r datasheet 477 uhci controllers registers 12.2.7 portsc[0,1]?port status and control register i/o offset: port 0/2/4/6: base + (10 ? 11h) attribute: r/wc, ro, port 1/3/5/7: base + (12 ? 13h) r/w (word writes only) default value: 0080h size: 16 bits note: for function 0, this applies to ich5 usb ports 0 and 1; for function 1, this applies to ich5 usb ports 2 and 3; for function 2, this applies to ich5 usb ports 4 and 5; and for function 3, this applies to ich5 usb ports 6 and 7. after a power-up reset, global reset, or host controller reset, the initial conditions of a port are: no device connected, port disabled, and the bus line status is 00 (se0). bit description 15:13 reserved ? ro. 12 suspend ? r/w . this bit should not be written to a 1 if global suspend is active (bit 3=1 in the usbcmd register). bit 2 and bit 12 of this register define the hub states as follows: bits [12,2] hub state x0 disable 01 enable 11 suspend when in suspend state, downstream propagation of data is blocked on this port, except for single-ended 0 resets (global reset and port reset). the blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. in the suspend state, the port is sensitive to resume detection. note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the usb. 1 = port in suspend state. 0 = port not in suspend state. note: normally, if a transaction is in progress when this bit is set, the port will be suspended when the current transaction completes. however, in the case of a specific error condition (out transaction with babble), the intel ? ich5 may issue a start-of-frame, and then suspend the port. 11 overcurrent indicator ? r/wc. set by hardware. 0 = software clears this bit by writing a 1 to it. 1 = overcurrent pin has gone from inactive to active on this port. 10 overcurrent active ? ro. this bit is set and cleared by hardware. 0 = indicates that the overcurrent pin is inactive (high). 1 = indicates that the overcurrent pin is active (low). 9 port reset ? r/w . 0 = port is not in reset. 1 = port is in reset. when set, the port is disabled and sends the usb reset signaling. 8 low speed device attached (ls) ? ro . 0 = full speed device is attached. 1 = low speed device is attached to this port. 7 reserved ? ro. always read as 1. 6 resume detect (rsm_det) ? r/w. software sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected for at least 32 microseconds while the port is in the suspend state. the ich5 will then reflect the k-state back onto the bus as long as the bit remains a 1, and the port is still in the suspend state (bit 12,2 are ?11?). writing a 0 (from 1) causes the port to send a low speed eop. this bit will remain a 1 until the eop has completed. 0 = no resume (k-state) detected/driven on port. 1 = resume detected/driven on port. 478 intel ? 82801eb ich5 / 82801er ich5r datasheet uhci controllers registers 5:4 line status ? ro . these bits reflect the d+ (bit 4) and d? (bit 5) signals lines? logical levels. these bits are used for fault detect and recovery as well as for usb diagnostics. this field is updated at eof2 time (see chapter 11 of the universal serial bus revision 2.0 specification ). 3 port enable/disable change ? r/wc . for the root hub, this bit gets set only when a port is disabled due to disconnect on that port or due to the appropriate conditions existing at the eof2 point (see chapter 11 of the universal serial bus revision 2.0 specification ). 0 = no change. software clears this bit by writing a 1 to the bit location. 1 = port enabled/disabled status has changed. 2 port enabled/disabled (port_en) ? r/w . ports can be enabled by host software only. ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. note that the bit status does not change until the port state actually changes and that there may be a delay in disabling or enabling a port if there is a transaction currently in progress on the usb. 0 = disable 1 = enable 1 connect status change ? r/wc . this bit indicates that a change has occurred in the port?s current connect status (see bit 0). the hub device sets this bit for any changes to the port device connect status, even if system software has not cleared a connect status change. if, for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting? an already-set bit (i.e., the bit will remain set). however, the hub transfers the change bit only once when the host controller requests a data transfer to the status change endpoint. system software is responsible for determining state change history in such a case. 0 = no change. software clears this bit by writing a 1 to it. 1 = change in current connect status. 0 current connect status ? ro . this value reflects the current state of the port, and may not correspond directly to the event that caused the connect status change bit (bit 1) to be set. 0 = no device is present. 1 = device is present on port. bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 479 ehci controller registers (d29:f7) ehci controller registers (d29:f7) 13 13.1 usb ehci configuration registers (usb ehci?d29:f7) note: register address locations that are not shown in table 162 should be treated as reserved (see section 6.2 for details). table 162. usb ehci pci register address map (usb ehci?d29:f7) offset mnemonic register name default value type 00?01h vid vendor identification 8086h ro 02?03h did device identification 24ddh ro 04?05h pcicmd pci command 0400h r/w, ro 06?07h pcists pci status 0290h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 20h ro 0ah scc sub class code 03h ro 0bh bcc base class code 0ch ro 0dh pmlt primary master latency timer 00h ro 10?13h mem_base memory base address 00000000h r/w, ro 2c?2dh svid usb ehci subsystem vendor identification xxxxh r/w (special) 2e?2fh sid usb ehci subsystem identification xxxxh r/w (special) 34h cap_ptr capabilities pointer 50h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin 04h ro 50h pwr_capid pci power management capability id 01h ro 51h nxt_ptr1 next item pointer 58h r/w (special) 52?53h pwr_cap power management capabilities c9c2h r/w (special) 54?55h pwr_cntl_sts power management control/status 0000h r/w, r/wc, ro 58h debug_capid debug port capability id 0ah ro 59h nxt_ptr2 next item pointer #2 00h ro 5a?5bh debug_base debug port base offset 20a0h ro 60h usb_relnum usb release number 20h ro 61h fl_adj frame length adjustment 20h r/w 62?63h pwake_cap port wake capabilities 01ffh r/w 66?67h ? reserved ? ? 480 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.1.1 vid?vendor identification register (usb ehci?d29:f7) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16 bits 13.1.2 did?device identification register (usb ehci?d29:f7) offset address: 02 ? 03h attribute: ro default value: 24ddh size: 16 bits 68?6bh leg_ext_cap usb ehci legacy support extended capability 00000001h r/w, ro 6c?6fh leg_ext_cs usb ehci legacy extended support control/status 00000000h r/w, r/wc, ro 70?73h special_smi intel specific usb 2.0 smi 00000000h r/w, r/wc 74?7fh ? reserved ? ? 80h access_cntl access control 00h r/w table 162. usb ehci pci register address map (usb ehci?d29:f7) offset mnemonic register name default value type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich5 usb ehci controller. intel ? 82801eb ich5 / 82801er ich5r datasheet 481 ehci controller registers (d29:f7) 13.1.3 pcicmd?pci command register (usb ehci?d29:f7) address offset: 04 ? 05h attribute: r/w, ro default value: 0400h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = the function is capable of generating interrupts. 1 = the function can not generate its interrupt to the interrupt controller. note that the corresponding interrupt status bit is not affected by the interrupt enable. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. 0 = disables ehc?s capability to generate an serr#. 1 = the enhanced host controller ( ehc) is capable of generating (internally) serr# when it receive a completion status other than ?successful? for one of its dma-initiated memory reads on the hub interface (and subsequently on its internal interface). 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? ro. hardwired to 0. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. 0 = disables this functionality. 1 = enables the intel ? ich5 to act as a master on the pci bus for usb transfers. 1 memory space enable (mse) ? r/w. this bit controls access to the usb 2.0 memory space registers. 0 = disables this functionality. 1 = enables accesses to the usb 2.0 registers. the base address register for usb 2.0 should be programmed before this bit is set. 0 i/o space enable (iose) ? ro. hardwired to 0. 482 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.1.4 pcists?pci status register (usb ehci?d29:f7) address offset: 06 ? 07h attribute: r/wc, ro default value: 0290h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? ro. hardwired to 0. 14 signaled system error (sse) ? r/wc. 0 = no serr# signaled by intel ? ich5. 1 = this bit is set by the ich5 when it signals serr# (internally). the ser_en bit (bit 8 of the command register) must be 1 for this bit to be set. 13 received master abort (rma) ? r/wc. 0 = no master abort received by ehc on a memory access. 1 = this bit is set when ehc, as a master, receives a master abort status on a memory access. this is treated as a host error and halts the dma engines. this event can optionally generate an serr# by setting the serr# enable bit . 12 received target abort (rta) ? r/wc. 0 = no target abort received by ehc on memory access. 1 = this bit is set when ehc, as a master, receives a target abort status on a memory access. this is treated as a host error and halts the dma engines. this event can optionally generate an serr# by setting the serr# enable bit . 11 signaled target abort (sta) ? ro. this bit is used to indicate when the ehci function responds to a cycle with a target abort. there is no reason for this to happen, so this bit will be hardwired to 0. 10:9 devsel# timing status (devt_sts) ? ro. this 2-bit field defines the timing for devsel# assertion. 8 master data parity error detected (dped) ? r/wc. 0 = no data parity error detected on usb2.0 read completion packet. 1 = this bit is set by the ich5 when a data parity error is detected on a usb 2.0 read completion packet on the internal interface to the ehci host controller (due to an equivalent data parity error on hub interface) and bit 6 of the command register is set to 1. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (udf) ? ro. hardwired to 0. 5 66 mhz capable (66 mhz _cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. hardwired to 1 indicating that offset 34h contains a valid capabilities pointer. 3 interrupt status ? ro. this bit reflects the state of this function?s interrupt at the input of the enable/disable logic. 0 = this bit will be 0 when the interrupt is deasserted. 1 = this bit is a 1 when the interrupt is asserted. the value reported in this bit is independent of the value in the interrupt enable bit. 2:0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 483 ehci controller registers (d29:f7) 13.1.5 rid?revision identification register (usb ehci?d29:f7) offset address: 08h attribute: ro default value: see table below size: 8 bits 13.1.6 pi?programming interface register (usb ehci?d29:f7) address offset: 09h attribute: ro default value: 20h size: 8 bits 13.1.7 scc?sub class code register (usb ehci?d29:f7) address offset: 0ah attribute: ro default value: 03h size: 8 bits 13.1.8 bcc?base class code register (usb ehci?d29:f7) address offset: 0bh attribute: ro default value: 0ch size: 8 bits bit description 7:0 revision id ? ro. these bits contain device stepping information and are hardwired to the default value. note: refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. bit description 7:0 programming interface ? ro. a value of 20h indicates that this usb 2.0 host controller conforms to the enhanced host controller interface specification for universal serial bus, revision 1.0 . bit description 7:0 sub class code (scc) ? ro. 03h = universal serial bus host controller. bit description 7:0 base class code (bcc) ? ro. 0ch = serial bus controller. 484 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.1.9 pmlt?primary master latency timer register (usb ehci?d29:f7) address offset: 0dh attribute: ro default value: 00h size: 8 bits 13.1.10 mem_base?memory base address register (usb ehci?d29:f7) address offset: 10 ? 13h attribute: r/w, ro default value: 00000000h size: 32 bits 13.1.11 svid?usb ehci subsystem vendor id register (usb ehci?d29:f7) address offset: 2c ? 2dh attribute: r/w (special) default value: xxxxh size: 16 bits reset: none bit description 7:0 master latency timer count (mltc) ? ro. hardwired to 00h. because the ehci controller is internally implemented with arbitration via hub interface (and not pci), it does not need a master latency timer. bit description 31:10 base address ? r/w. bits [31:10] correspond to memory address signals [31:10], respectively. this gives 1-kb of locatable memory space aligned to 1-kb boundaries. 9:4 reserved 3 prefetchable ? ro. hardwired to 0 indicating that this range should not be prefetched. 2:1 type ? ro. hardwired to 00b indicating that this range can be mapped anywhere within 32-bit address space. 0 resource type indicator (rte) ? ro. hardwired to 0 indicating that the base address field in this register maps to memory space. bit description 15:0 subsystem vendor id (svid) ? r/w (special). this register, in combination with the usb 2.0 subsystem id register, enables the operating system to distinguish each subsystem from the others. note: writes to this register are enabled when the wrt_rdonly bit (offset 80h, bit 0) is set to 1. intel ? 82801eb ich5 / 82801er ich5r datasheet 485 ehci controller registers (d29:f7) 13.1.12 sid?usb ehci subsystem id register (usb ehci?d29:f7) address offset: 2e ? 2fh attribute: r/w (special) default value: xxxxh size: 16 bits reset: none 13.1.13 cap_ptr?capabilities pointer register (usb ehci?d29:f7) address offset: 34h attribute: ro default value: 50h size: 8 bits 13.1.14 int_ln?interrupt line register (usb ehci?d29:f7) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 13.1.15 int_pn?interrupt pin register (usb ehci?d29:f7) address offset: 3dh attribute: ro default value: 04h size: 8 bits bit description 15:0 subsystem id (sid) ? r/w (special). bios sets the value in this register to identify the subsystem id. this register, in combination with the subsystem vendor id register, enables the operating system to distinguish each subsystem from other(s). note: writes to this register are enabled when the wrt_rdonly bit (offset 80h, bit 0) is set to 1. bit description 7:0 capabilities pointer (cap_ptr) ? ro. this register points to the starting offset of the usb 2.0 capabilities ranges. bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich5. it is used as a scratchpad register to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:0 interrupt pin ? ro. the value of 04h indicates that the ehci function within the intel ? ich5?s multi-function usb device will drive the fourth interrupt pin from the device- intd# in pci terms. the value of 04h in function 7 is required because the pci local bus specification, revision 2.3 doesn?t recognize more than 4 interrupts and older apm-based oss require that each function within a multi-function device has a different interrupt pin register value. note: internally the ehci controller uses pirqh#. 486 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.1.16 pwr_capid?pci power management capability id register (usb ehci?d29:f7) address offset: 50h attribute: ro default value: 01h size: 8 bits 13.1.17 nxt_ptr1?next item pointer #1 register (usb ehci?d29:f7) address offset: 51h attribute: r/w (special) default value: 58h size: 8 bits bit description 7:0 power management capability id ? ro. a value of 01h indicates that this is a pci power management capabilities field. bit description 7:0 next item pointer 1 value ? r/w (special). this register defaults to 58h, which indicates that the next capability registers begin at configuration offset 58h. this register is writable when the wrt_rdonly bit is set. this allows bios to effectively hide the debug port capability registers, if necessary. this register should only be written during system initialization before the plug-and-play software has enabled any master-initiated traffic. only values of 58h (debug port visible) and 00h (debug port invisible) are expected to be programmed in this register. intel ? 82801eb ich5 / 82801er ich5r datasheet 487 ehci controller registers (d29:f7) 13.1.18 pwr_cap?power management capabilities register (usb ehci?d29:f7) address offset: 52 ? 53h attribute: r/w (special) default value: c9c2h size: 16 bits notes: 1. normally, this register is read-only to report capabilities to the power management software. to report different power management capabilities, depending on the system in which the ich5 is used, bits 15:11 and 8:6 in this register are writable when the wrt_rdonly bit is set. the value written to this register does not affect the hardware other than changing the value returned during a read. 2. reset: core well, but not d3-to-d0 warm reset. bit description 15:11 pme support (pme_sup) ? r/w (special). this 5-bit field indicates the power states in which the function may assert pme#. the intel ? ich5 ehc does not support the d1 or d2 states. for all other states, the ich5 ehc is capable of generating pme#. software should never need to modify this field. 10 d2 support (d2_sup) ? r/w (special). 0 = d2 state is not supported 1 = d2 state is supported 9 d1 support (d1_sup) ? r/w (special). 0 = d1 state is not supported 1 = d1 state is supported 8:6 auxiliary current (aux_cur) ? r/w (special). the ich5 ehc reports 375 ma maximum suspend well current required when in the d3 cold state. this value can be written by bios when a more accurate value is known. 5 device specific initialization (dsi )? r/w (special). the ich5 reports 0, indicating that no device-specific initialization is required. 4 reserved 3 pme clock (pme_clk) ? r/w (special). the ich5 reports 0, indicating that no pci clock is required to generate pme#. 2:0 version (ver) ? r/w (special). the ich5 reports 010b, indicating that it complies with the pci power management specification, revision 1.1 488 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.1.19 pwr_cntl_sts?power management control/status register (usb ehci?d29:f7) address offset: 54 ? 55h attribute: r/w, r/wc, ro default value: 0000h size: 16 bits note: reset (bits 15, 8): suspend well, and not d3-to-d0 warm reset nor core well reset. 13.1.20 debug_capid?debug port capability id register (usb ehci?d29:f7) address offset: 58h attribute: ro default value: 0ah size: 8 bits bit description 15 pme status ? r/wc. 0 = writing a 1 to this bit will clear it and cause the internal pme to deassert (if enabled). 1 = this bit is set when the intel ? ich5 ehc would normally assert the pme# signal independent of the state of the pme_en bit. note: this bit must be explicitly cleared by the operating system each time the operating system is loaded. 14:13 data scale ? ro. hardwired to 00b indicating it does not support the associated data register. 12:9 data select ? ro. hardwired to 0000b indicating it does not support the associated data register. 8 pme enable ? r/w. 0 = disable 1 = enable. enables ich5 ehc to generate an internal pme signal when pme_status is 1. note: this bit must be explicitly cleared by the operating system each time it is initially loaded. 7:2 reserved 1:0 power state ? r/w. this 2-bit field is used both to determine the current power state of ehc function and to set a new power state. the definition of the field values are: 00 = d0 state 11 = d3 hot state if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. when in the d3 hot state, the ich5 must not accept accesses to the ehc memory range; but the configuration space must still be accessible. when not in the d0 state, the generation of the interrupt output is blocked. specifically, the pirqh is not asserted by the ich5 when not in the d0 state. when software changes this value from the d3hot state to the d0 state, an internal warm (soft) reset is generated, and software must re-initialize the function. bit description 7:0 debug port capability id ? ro. hardwired to 0ah indicating that this is the start of a debug port capability structure. intel ? 82801eb ich5 / 82801er ich5r datasheet 489 ehci controller registers (d29:f7) 13.1.21 nxt_ptr2?next item pointer #2 register (usb ehci?d29:f7) address offset: 59h attribute: ro default value: 00h size: 8 bits 13.1.22 debug_base?debug port base offset register (usb ehci?d29:f7) address offset: 5ah ? 5bh attribute: ro default value: 20a0h size: 16 bits 13.1.23 usb_relnum?usb release number register (usb ehci?d29:f7) address offset: 60h attribute: ro default value: 20h size: 8 bits bit description 7:0 next item pointer 2 capability ? ro. hardwired to 00h to indicate there are no more capability structures in this function. bit description 15:13 bar number ? ro. hardwired to 001b to indicate the memory bar begins at offset 10h in the ehci configuration space. 12:0 debug port offset ? ro. hardwired to 0a0h to indicate that the debug port registers begin at offset a0h in the ehci memory range. bit description 7:0 usb release number ? ro. a value of 20h indicates that this controller follows universal serial bus (usb) specification, revision 2.0 . 490 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.1.24 fl_adj?frame length adjustment register (usb ehci?d29:f7) address offset: 61h attribute: r/w default value: 20h size: 8 bits this feature is used to adjust any offset from the clock source that generates the clock that drives the sof counter. when a new value is written into these six bits, the length of the frame is adjusted. its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. this register should only be modified when the hchalted bit in the usb2.0_sts register is a 1. changing value of this register while the host controller is operating yields undefined results. it should not be reprogrammed by usb system software unless the default or bios programmed values are incorrect, or the system is restoring the register while returning from a suspended state. bit description 7:6 reserved ? ro. these bits are reserved for future use and should read as 00b. 5:0 frame length timing value ? r/w. each decimal value change to this register corresponds to 16 high-speed bit times. the sof cycle time (number of sof counter clock periods to generate a sof micro-frame length) is equal to 59488 + value in this field. the default value is decimal 32 (20h), which gives a sof cycle time of 60000. frame length fladj value (# 480 mhz clocks) decimal (hex) 59488 0 (00h) 59504 1 (01h) 59520 2 (02h) ? 59984 31 (1fh) 60000 32 (20h) ? 60480 62 (3eh) 60496 63 (3fh) intel ? 82801eb ich5 / 82801er ich5r datasheet 491 ehci controller registers (d29:f7) 13.1.25 pwake_cap?port wake capability register (usb ehci?d29:f7) address offset: 62 ? 63h attribute: r/w default value: 01ffh size: 16 bits this register is in the suspend power well. the intended use of this register is to establish a policy about which ports are to be used for wake events. bit positions 1?8 in the mask correspond to a physical port implemented on the current ehci controller. a 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect/connect or overcurrent events as wake-up events. this is an information-only mask register. the bits in this register do not affect the actual operation of the ehci host controller. the system-specific policy can be established by bios initializing this register to a system-specific value. system software uses the information in this register when enabling devices and ports for remote wake-up. 13.1.26 leg_ext_cap?usb ehci legacy support extended capability register (usb ehci?d29:f7) address offset: 68 ? 6bh attribute: r/w, ro default value: 00000001h size: 32 bits power well: suspend bit description 15:9 reserved ? ro. 8:1 port wake up capability mask ? r/w. bit positions 1 through 8 correspond to a physical port implemented on this host controller. for example, bit position 1 corresponds to port 1, bit position 2 corresponds to port 2, etc. 0 port wake implemented ? r/w. a 1 in this bit indicates that this register is implemented to software. bit description 31:25 reserved ? ro. hardwired to 00h 24 hc os owned semaphore ? r/w. system software sets this bit to request ownership of the ehci controller. ownership is obtained when this bit reads as 1 and the hc bios owned semaphore bit reads as clear. 23:17 reserved ? ro. hardwired to 00h 16 hc bios owned semaphore ? r/w. the bios sets this bit to establish ownership of the ehci controller. system bios will clear this bit in response to a request for ownership of the ehci controller by system software. 15:8 next ehci capability pointer ? ro. hardwired to 00h to indicate that there are no ehci extended capability structures in this device. 7:0 capability id ? ro. hardwired to 01h to indicate that this ehci extended capability is the legacy support capability. 492 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.1.27 leg_ext_cs?usb ehci legacy support extended control / status register (usb ehci?d29:f7) address offset: 6c ? 6fh attribute: r/w, r/wc, ro default value: 00000000h size: 32 bits power well: suspend bit description 31 smi on bar ?r/wc. software clears this bit by writing a 1 to it. 0 = base address register (bar) not written. 1 = this bit is set to 1 when the base address register (bar) is written. 30 smi on pci command ? r/wc. software clears this bit by writing a 1 to it. 0 = pci command (pcicmd) register not written. 1 = this bit is set to 1 when the pci command (pcicmd) register is written. 29 smi on os ownership change ? r/wc. software clears this bit by writing a 1 to it. 0 = no hc os owned semaphore bit change. 1 = this bit is set to 1 when the hc os owned semaphore bit in the leg_ext_cap register transitions from 1 to 0 or 0 to 1. 28:22 reserved ? ro. hardwired to 00h 21 smi on async advance ? ro. this bit is a shadow bit of the interrupt on async advance bit in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the interrupt on async advance bit in the usb2.0_sts register. 20 smi on host system error ? ro. this bit is a shadow bit of host system error bit in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the host system error bit in the usb2.0_sts register. 19 smi on frame list rollover ? ro. this bit is a shadow bit of frame list rollover bit in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the frame list rollover bit in the usb2.0_sts register. 18 smi on port change detect ? ro. this bit is a shadow bit of port change detect bit in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the port change detect bit in the usb2.0_sts register. 17 smi on usb error ? ro. this bit is a shadow bit of usb error interrupt (usberrint) bit in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the usb error interrupt bit in the usb2.0_sts register. 16 smi on usb complete ? ro. this bit is a shadow bit of usb interrupt (usbint) bit in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the usb interrupt bit in the usb2.0_sts register. 15 smi on bar enable ? r/w. 0 = disable 1 = enable. when this bit is 1 and smi on bar is 1, then the host controller will issue an smi. 14 smi on pci command enable ? r/w. 0 = disable 1 = enable. when this bit is 1 and smi on pci command is 1, then the host controller will issue an smi. intel ? 82801eb ich5 / 82801er ich5r datasheet 493 ehci controller registers (d29:f7) 13.1.28 special_smi?intel specific usb 2.0 smi register (usb ehci?d29:f7) address offset: 70 ? 73h attribute: r/w, r/wc default value: 00000000h size: 32 bits power well: suspend 13 smi on os ownership enable ? r/w. 0 = disable 1 = enable. when this bit is a 1 and the os ownership change bit is 1, the host controller will issue an smi. 12:6 reserved ? ro. hardwired to 00h 5 smi on async advance enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the smi on async advance bit is a 1, the host controller will issue an smi immediately. 4 smi on host system error enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the smi on host system error is a 1, the host controller will issue an smi. 3 smi on frame list rollover enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the smi on frame list rollover bit is a 1, the host controller will issue an smi. 2 smi on port change enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the smi on port change detect bit is a 1, the host controller will issue an smi. 1 smi on usb error enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the smi on usb error bit is a 1, the host controller will issue an smi immediately. 0 smi on usb complete enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the smi on usb complete bit is a 1, the host controller will issue an smi immediately. bit description bit description 31:30 reserved ? ro. hardwired to 00h 29:22 smi on portowner ? r/wc. software clears these bits by writing a 1 to it. 0 = no port owner bit change. 1 = bits 29:22 correspond to the port owner bits for ports 1 (22) through 8 (29). these bits are set to 1 when the associated port owner bits transition from 0 to 1 or 1 to 0. 21 smi on pmcsr ? r/wc. software clears these bits by writing a 1 to it. 0 = power state bits not modified. 1 = software modified the power state bits in the power management control/status (pmcsr) register. 20 smi on async ? r/wc. software clears these bits by writing a 1 to it. 0 = no async schedule enable bit change 1 = async schedule enable bit transitioned from 1 to 0 or 0 to 1. 494 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 19 smi on periodic ? r/wc. software clears this bit by writing a 1 it. 0 = no periodic schedule enable bit change. 1 = periodic schedule enable bit transitions from 1 to 0 or 0 to 1. 18 smi on cf ? r/wc. software clears this bit by writing a 1 it. 0 = no configure flag (cf) change. 1 = configure flag (cf) transitions from 1 to 0 or 0 to 1. 17 smi on hchalted ? r/wc. software clears this bit by writing a 1 it. 0 = hchalted did not transition to 1 (as a result of the run/stop bit being cleared). 1 = hchalted transitions to 1 (as a result of the run/stop bit being cleared). 16 smi on hcreset ? r/wc. software clears this bit by writing a 1 it. 0 = hcreset did not transitioned to 1. 1 = hcreset transitioned to 1. 15:14 reserved ? ro. hardwired to 00h 13:6 smi on portowner enable ? r/w. 0 = disable 1 = enable. when any of these bits are 1 and the corresponding smi on portowner bits are 1, then the host controller will issue an smi. unused ports should have their corresponding bits cleared. 5 smi on pmscr enable ? r/w. 0 = disable 1 = enable. when this bit is 1 and smi on pmscr is 1, then the host controller will issue an smi. 4 smi on async enable ? r/w. 0 = disable 1 = enable. when this bit is 1 and smi on async is 1, then the host controller will issue an smi 3 smi on periodic enable ? r/w. 0 = disable 1 = enable. when this bit is 1 and smi on periodic is 1, then the host controller will issue an smi. 2 smi on cf enable ? r/w. 0 = disable 1 = enable. when this bit is 1 and smi on cf is 1, then the host controller will issue an smi. 1 smi on hchalted enable ? r/w. 0 = disable 1 = enable. when this bit is a 1 and smi on hchalted is 1, then the host controller will issue an smi. 0 smi on hcreset enable ? r/w. 0 = disable 1 = enable. when this bit is a 1 and smi on hcreset is 1, then host controller will issue an smi? r/w. bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 495 ehci controller registers (d29:f7) 13.1.29 access_cntl?access control register (usb ehci?d29:f7) address offset: 80h attribute: r/w default value: 00h size: 8 bits bit description 7:1 reserved 0 wrt_rdonly ? r/w. when set to 1, this bit enables a select group of normally read-only registers in the ehc function to be written by software. registers that may only be written when this mode is entered are noted in the summary tables and detailed description as ?read/write-special?. the registers fall into two categories: 1. system-configured parameters, and 2. status bits 496 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.2 memory-mapped i/o registers the ehci memory-mapped i/o space is composed of two sets of registers: capability registers and operational registers. note: the ich5 ehci controller will not accept memory transactions (neither reads nor writes) as a target that are locked transactions. the locked transactions should not be forwarded to pci as the address space is known to be allocated to usb. note: when the ehci function is in the d3 pci power state, accesses to the usb 2.0 memory range are ignored and result a master abort. similarly, if the memory space enable (mse) bit is not set in the command register in configuration space, the memory range will not be decoded by the ich5 enhanced host controller (ehc). if the mse bit is not set, then the ich5 must default to allowing any memory accesses for the range specified in the bar to go to pci. this is because the range may not be valid and, therefore, the cycle must be made available to any other targets that may be currently using that range. host controller capability registers these registers specify the limits, restrictions and capabilities of the host controller implementation. within the host controller capability registers, only the structural parameters register is writable. this register is implemented in the suspend well and is only reset by the standard suspend-well hardware reset, not by hcreset or the d3-to-d0 reset. note: ?read/write special? means that the register is normally read-only, but may be written when the wrt_rdonly bit is set. because these registers are expected to be programmed by bios during initialization, their contents must not get modified by hcreset or d3-to-d0 internal reset. 13.2.1 caplength?capability registers length register offset: 00h attribute: ro default value: 20h size: 8 bits table 163. enhanced host controller capability registers offset mnemonic register default type 00h caplength capabilities registers length 20h ro 02?03h hciversion host controller interface version number 0100h ro 04?07h hcsparams host controller structural parameters 00104208h r/w (special), ro 08?0bh hccparams host controller capability parameters 00006871h ro bit description 7:0 capability register length value ? ro. this register is used as an offset to add to the memory base register to find the beginning of the operational register space. this field is hardwired to 20h indicating that the operation registers begin at offset 20h. intel ? 82801eb ich5 / 82801er ich5r datasheet 497 ehci controller registers (d29:f7) 13.2.2 hciversion?host controller interface version number register offset: 02 ? 03h attribute: ro default value: 0100h size: 16 bits 13.2.3 hcsparams?host controller structural parameters offset: 04 ? 07h attribute: r/w (special), ro default value: 00104208h size: 32 bits note: this register is reset by a suspend well reset and not a d3-to-d0 reset or hcreset. note: this register is writable when the wrt_rdonly bit is set. bit description 15:0 host controller interface version number ? ro. this is a two-byte register containing a bcd encoding of the version number of interface that this host controller interface conforms. bit description 31:24 reserved ? ro. default=0h. 23:20 debug port number (dp_n) ? r/w (special). hardwired to 1h indicating that the debug port is on the lowest numbered port on the intel ? ich5. 19:16 reserved 15:12 number of companion controllers (n_cc) ? r/w (special). this field indicates the number of companion controllers associated with this usb ehci host controller. a 0 in this field indicates there are no companion host controllers. port-ownership hand-off is not supported. only high-speed devices are supported on the host controller root ports. a value larger than 1 in this field indicates there are companion usb uhci host controller(s). port- ownership hand-offs are supported. high, full- and low-speed devices are supported on the host controller root ports. the ich5 allows the default value of 4h to be over-written by bios. when removing classic controllers, they should be disabled in the following order: function 3, function 2, function 1, and function 0, which correspond to ports 7:6, 5:4, 3:2, and 1:0, respectively. 11:8 number of ports per companion controller (n_pcc) ? ro. hardwired to 2h. this field indicates the number of ports supported per companion host controller. it is used to indicate the port routing configuration to system software. 7:4 reserved. these bits are reserved and default to 0. 3:0 n_ports ? r/w (special). this field specifies the number of physical downstream ports implemented on this host controller. the value of this field determines how many port registers are addressable in the operational register space. valid values are in the range of 1h to fh. the ich5 reports 8h by default. however, software may write a value less than 8 for some platform configurations. a 0 in this field is undefined. 498 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.2.4 hccparams?host controller capability parameters register offset: 08 ? 0bh attribute: ro default value: 00006871h size: 32 bits bit description 31:16 reserved 15:8 ehci extended capabilities pointer (eecp) ? ro. this field is hardwired to 68h, indicating that the ehci capabilities list exists and begins at offset 68h in the pci configuration space. 7:4 isochronous scheduling threshold ? ro. this field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. when bit 7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller hold a set of isochronous data structures (one or more) before flushing the state. when bit 7 is a 1, then host software assumes the host controller may cache an isochronous data structure for an entire frame. refer to the enhanced host controller interface specification for universal serial bus, revision 1.0 for details on how software uses this information for scheduling isochronous transfers. this field is hardwired to 7h. 3 reserved. these bits are reserved and should be set to 0. 2 asynchronous schedule park capability ? ro. this bit is hardwired to 0 indicating that the host controller does not support this optional feature 1 programmable frame list flag ? ro. 0 = system software must use a frame list length of 1024 elements with this host controller. the usb2.0_cmd register frame list size field is a read-only register and must be set to 0. 1 = system software can specify and use a smaller frame list and configure the host controller via the usb2.0_cmd register frame list size field. the frame list must always be aligned on a 4k page boundary. this requirement ensures that the frame list is always physically contiguous. 0 64-bit addressing capability ? ro. this field documents the addressing range capability of this implementation. the value of this field determines whether software should use the 32-bit or 64-bit data structures. values for this field have the following interpretation: 0 = data structures using 32-bit address memory pointers 1 = data structures using 64-bit address memory pointers this bit is hardwired to 1. note: intel ? ich5 only implements 44 bits of addressing. bits 63:44 will always be 0. intel ? 82801eb ich5 / 82801er ich5r datasheet 499 ehci controller registers (d29:f7) host controller operational registers this section defines the enhanced host controller operational registers. these registers are located after the capabilities registers. the operational register base must be dword-aligned and is calculated by adding the value in the first capabilities register (caplength) to the base address of the enhanced host controller register address space. all registers are 32 bits in length. note: software must read and write these registers using only dword accesses.these registers are divided into two sets. the first set at offsets 00:3fh are implemented in the core power well. unless otherwise noted, the core-well registers are reset by the assertion of any of the following: ? core well hardware reset ? hcreset ? d3-to-d0 reset table 164. enhanced host controller operational register address map offset (caplen gth+) mnemonic register name default special notes type 00?03h usb2.0_cmd usb 2.0 command 00080000h r/w, ro 04?07h usb2.0_sts usb 2.0 status 00001000h r/wc, ro 08?0bh usb2.0_intr usb 2.0 interrupt enable 00000000h r/w 0c?0fh frindex usb 2.0 frame index 00000000h r/w, 10?13h ctrlds- segment control data structure segment 00000000h r/w, ro 14?17h perodi- clistbase period frame list base address 00000000h r/w 18?1bh asynclis- taddr current asynchronous list address 00000000h r/w 1c?3fh ? reserved 0h ro 40?43h configglag configure flag 00000000h suspend r/w 44?47h port0sc port 0 status and control 00003000h suspend r/w, r/wc, ro 48?4bh port1sc port 1 status and control 00003000h suspend r/w, r/wc, ro 4c?4fh port2sc port 2 status and control 00003000h suspend r/w, r/wc, ro 50?53h port3sc port 3 status and control 00003000h suspend r/w, r/wc, ro 54?57h port4sc port 4 status and control 00003000h suspend r/w, r/wc, ro 58?5bh port5sc port 5 status and control 00003000h suspend r/w, r/wc, ro 5c?5fh port6sc port 6 status and control 00003000h suspend r/w, r/wc, ro 60?63h port7sc port 7 status and control 00003000h suspend r/w, r/wc, ro 64?7fh ? reserved undefined ro 80?93h ? debug port registers undefined see register description 94?3ffh ? reserved undefined ro 500 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) the second set at offsets 40h to the end of the implemented register space are implemented in the suspend power well. unless otherwise noted, the suspend-well registers are reset by the assertion of either of the following: ? suspend well hardware reset ? hcreset 13.2.5 usb2.0_cmd?usb 2.0 command register offset: caplength + 00 ? 03h attribute: rw, ro default value: 00080000h size: 32 bits bit description 31:24 reserved. these bits are reserved and should be set to 0 when writing this register. 23:16 interrupt threshold control ? r/w. system software uses this field to select the maximum rate at which the host controller will issue interrupts. the only valid values are defined below. if software writes an invalid value to this register, the results are undefined. value maximum interrupt interval 00h reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames (default) 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms) 15:8 reserved. these bits are reserved and should be set to 0 when writing this register. 11:8 unimplemented asynchronous park mode bits. hardwired to 000b indicating the host controller does not support this optional feature. 7 light host controller reset ? ro. hardwired to 0. the intel ? ich5 does not implement this optional reset. 6 interrupt on async advance doorbell ? r/w. this bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. 0 = the host controller sets this bit to a 0 after it has set the interrupt on async advance status bit in the usb2.0_sts register to a 1. 1 = software must write a 1 to this bit to ring the doorbell. when the host controller has evicted all appropriate cached schedule state, it sets the interrupt on async advance status bit in the usb2.0_sts register. if the interrupt on async advance enable bit in the usb2.0_intr register is a 1 then the host controller will assert an interrupt at the next interrupt threshold. see the enhanced host controller interface specification for universal serial bus, revision 1.0 for operational details. note: software should not write a 1 to this bit when the asynchronous schedule is inactive. doing so will yield undefined results. 5 asynchronous schedule enable ? r/w. default 0b. this bit controls whether the host controller skips processing the asynchronous schedule. 0 = do not process the asynchronous schedule 1 = use the asynclistaddr register to access the asynchronous schedule. 4 periodic schedule enable ? r/w. default 0b. this bit controls whether the host controller skips processing the periodic schedule. 0 = do not process the periodic schedule 1 = use the periodiclistbase register to access the periodic schedule. intel ? 82801eb ich5 / 82801er ich5r datasheet 501 ehci controller registers (d29:f7) note: the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. 3:2 frame list size ? ro. the ich5 hardwires this field to 00b because it only supports the 1024-element frame list size. 1 host controller reset (hcreset) ? r/w. this control bit used by software to reset the host controller. the effects of this on root hub registers are similar to a chip hardware reset (i.e., rsmrst# assertion and pwrok deassertion on the ich5). when software writes a 1 to this bit, the host controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediately terminated. a usb reset is not driven on downstream ports. note: pci configuration registers and host controller capability registers are not effected by this reset. all operational registers, including port registers and port state machines are set to their initial values. port ownership reverts to the companion host controller(s), with the side effects described in the enhanced host controller interface specification for universal serial bus, revision 1.0. software must re-initialize the host controller in order to return the host controller to an operational state. this bit is set to 0 by the host controller when the reset process is complete. software cannot terminate the reset process early by writing a 0 to this register. software should not set this bit to a 1 when the hchalted bit in the usb2.0_sts register is a 0. attempting to reset an actively running host controller will result in undefined behavior. this reset me be used to leave ehci port test modes. 0 run/stop (rs) ? r/w. 0 = stop (default) 1 = run. when set to a 1, the host controller proceeds with execution of the schedule. the host controller continues execution as long as this bit is set. when this bit is set to 0, the host controller completes the current transaction on the usb and then halts. the hchalted bit in the usb2.0_sts register indicates when the host controller has finished the transaction and has entered the stopped state. software should not write a 1 to this field unless the host controller is in the halted state (i.e., hchalted in the usbsts register is a 1). the halted bit is cleared immediately when the run bit is set. the following table explains how the different combinations of run and halted should be interpreted: run/stop halted interpretation 0 0 valid- in the process of halting 0 1 valid- halted 1 0 valid- running 1 1 invalid- the hchalted bit clears immediately. memory read cycles initiated by the ehc that receive any status other than successful will result in this bit being cleared. bit description 502 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.2.6 usb2.0_sts?usb 2.0 status register offset: caplength + 04 ? 07h attribute: r/wc, ro default value: 00001000h size: 32 bits this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. see the interrupts description in section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 for additional information concerning usb 2.0 interrupt conditions. note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 has no effect. bit description 31:16 reserved. these bits are reserved and should be set to 0 when writing this register. 15 asynchronous schedule status ? ro. this bit reports the current real status of the asynchronous schedule. 0 = status of the asynchronous schedule is disabled. (default) 1 = status of the asynchronous schedule is enabled. note: the host controller is not required to immediately disable or enable the asynchronous schedule when software transitions the asynchronous schedule enable bit in the usb2.0_cmd register. when this bit and the asynchronous schedule enable bit are the same value, the asynchronous schedule is either enabled (1) or disabled (0). 14 periodic schedule status ? ro. this bit reports the current real status of the periodic schedule. 0 = status of the periodic schedule is disabled. (default) 1 = status of the periodic schedule is enabled. note: the host controller is not required to immediately disable or enable the periodic schedule when software transitions the periodic schedule enable bit in the usb2.0_cmd register. when this bit and the periodic schedule enable bit are the same value, the periodic schedule is either enabled (1) or disabled (0). 13 reclamation ? ro. 0=default. this read-only status bit is used to detect an empty asynchronous schedule. the operational model and valid transitions for this bit are described in section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0. 12 hchalted ? ro. 0 = this bit is a 0 when the run/stop bit is a 1. 1 = the host controller sets this bit to 1 after it has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (e.g., internal error). (default) 11:6 reserved 5 interrupt on async advance ? r/wc. 0=default. system software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a 1 to the interrupt on async advance doorbell bit in the usb2.0_cmd register. this bit indicates the assertion of that interrupt source. 4 host system error ? r/wc. 0 = no serious error occurred during a host system access involving the host controller module 1 = the host controller sets this bit to 1 when a serious error occurs during a host system access involving the host controller module. a hardware interrupt is generated to the system. memory read cycles initiated by the ehc that receive any status other than successful will result in this bit being set. when this error occurs, the host controller clears the run/stop bit in the usb2.0_cmdregister to prevent further execution of the scheduled tds. a hardware interrupt is generated to the system (if enabled in the interrupt enable register). intel ? 82801eb ich5 / 82801er ich5r datasheet 503 ehci controller registers (d29:f7) 3 frame list rollover ? r/wc. 0 = no frame list index rollover from its maximum value to 0. 1 = the host controller sets this bit to a 1 when the frame list index (see section) rolls over from its maximum value to 0. since the intel ? ich5 only supports the 1024-entry frame list size, the frame list index rolls over every time frnum13 toggles. 2 port change detect ? r/wc. this bit is allowed to be maintained in the auxiliary power well. alternatively, it is also acceptable that on a d3 to d0 transition of the ehci hc device, this bit is loaded with the or of all of the portsc change bits (including: force port resume, overcurrent change, enable/disable change and connect status change). regardless of the implementation, when this bit is readable (i.e., in the d0 state), it must provide a valid view of the port status registers. 0 = no change bit transition from a 0 to 1 or no force port resume bit transition from 0 to 1 as a result of a j-k transition detected on a suspended port. 1 = the host controller sets this bit to 1 when any port for which the port owner bit is set to 0 has a change bit transition from a 0 to 1 or a force port resume bit transition from 0 to 1 as a result of a j-k transition detected on a suspended port. 1 usb error interrupt (usberrint) ? r/wc. 0 = no error condition. 1 = the host controller sets this bit to 1 when completion of a usb transaction results in an error condition (e.g., error counter underflow). if the td on which the error interrupt occurred also had its ioc bit set, both this bit and bit 0 are set. see the enhanced host controller interface specification for universal serial bus, revision 1.0 for a list of the usb errors that will result in this interrupt being asserted. 0 usb interrupt (usbint) ? r/wc. 0 = no completion of a usb transaction whose transfer descriptor had its ioc bit set. no short packet is detected. 1 = the host controller sets this bit to 1 when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. the host controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). bit description 504 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.2.7 usb2.0_intr?usb 2.0 interrupt enable register offset: caplength + 08 ? 0bh attribute: r/w default value: 00000000h size: 32 bits this register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. interrupt sources that are disabled in this register still appear in the usb2.0_sts register to allow the software to poll for events. each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism (see section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 , or not. bit description 31:6 reserved. these bits are reserved and should be 0 when writing this register. 5 interrupt on async advance enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the interrupt on async advance bit in the usb2.0_sts register is a 1, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing the interrupt on async advance bit. 4 host system error enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the host system error status bit in the usb2.0_sts register is a 1, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the host system error bit. 3 frame list rollover enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the frame list rollover bit in the usb2.0_sts register is a 1, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the frame list rollover bit. 2 port change interrupt enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the port change detect bit in the usb2.0_sts register is a 1, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the port change detect bit. 1 usb error interrupt enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the usberrint bit in the usb2.0_sts register is a 1, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software by clearing the usberrint bit in the usb2.0_sts register. 0 usb interrupt enable ? r/w. 0 = disable 1 = enable. when this bit is a 1, and the usbint bit in the usb2.0_sts register is a 1, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software by clearing the usbint bit in the usb2.0_sts register. intel ? 82801eb ich5 / 82801er ich5r datasheet 505 ehci controller registers (d29:f7) 13.2.8 frindex?frame index register offset: caplength + 0c ? 0fh attribute: r/w default value: 00000000h size: 32 bits the sof frame number value for the bus sof token is derived or alternatively managed from this register. refer to section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 for a detailed explanation of the sof value management requirements on the host controller. the value of frindex must be within 125 s (1 micro-frame) ahead of the sof token value. the sof value may be implemented as an 11-bit shadow register. for this discussion, this shadow register is 11 bits and is named sofv. sofv updates every 8 micro- frames. (1 millisecond). an example implementation to achieve this behavior is to increment sofv each time the frindex[2:0] increments from 0 to 1. software must use the value of frindex to derive the current micro-frame number, both for high-speed isochronous scheduling purposes and to provide the get micro-frame number function required to client drivers. therefore, the value of frindex and the value of sofv must be kept consistent if chip is reset or software writes to frindex. writes to frindex must also write-through frindex[13:3] to sofv[10:0]. in order to keep the update as simple as possible, software should never write a frindex value where the three least significant bits are 111b or 000b. note: this register is used by the host controller to index into the periodic frame list. the register updates every 125 microseconds (once each micro-frame). bits [12:3] are used to select a particular entry in the periodic frame list during periodic schedule execution. the number of bits used for the index is fixed at 10 for the ich5 since it only supports 1024-entry frame lists. this register must be written as a dword. word and byte writes produce undefined results. this register cannot be written unless the host controller is in the halted state as indicated by the hchalted bit (usb2.0_sts register). a write to this register while the run/stop bit is set to a 1 (usb2.0_cmd register) produces undefined results. writes to this register also effect the sof value. see section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 for details. bit description 31:14 reserved 13:0 frame list current index/frame number ? r/w. the value in this register increments at the end of each time frame (e.g., micro-frame). bits [12:3] are used for the frame list current index. this means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. 506 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.2.9 ctrldssegment?control data structure segment register offset: caplength + 10 ? 13h attribute: r/w, ro default value: 00000000h size: 32 bits this 32-bit register corresponds to the most significant address bits [63:32] for all ehci data structures. since the ich5 hardwires the 64-bit addressing capability field in hccparams to 1, then this register is used with the link pointers to construct 64-bit addresses to ehci control data structures. this register is concatenated with the link pointer from either the periodiclistbase, asynclistaddr, or any control data structure link field to construct a 64-bit address. this register allows the host software to locate all control data structures within the same 4 gb memory segment. 13.2.10 periodiclistbase?periodic frame list base address register offset: caplength + 14 ? 17h attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains the beginning address of the periodic frame list in the system memory. since the ich5 host controller operates in 64-bit mode (as indicated by the 1 in the 64-bit addressing capability field in the hccsparams register), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register. hcd loads this register prior to starting the schedule execution by the host controller. the memory structure referenced by this physical memory pointer is assumed to be 4-kbyte aligned. the contents of this register are combined with the frame index register (frindex) to enable the host controller to step through the periodic frame list in sequence. bit description 31:12 upper address[63:44] ? ro. hardwired to 0s. the intel ? ich5 ehc is only capable of generating addresses up to 16 terabytes (44 bits of address). 11:0 upper address[43:32] ? r/w. this 12-bit field corresponds to address bits 43:32 when forming a control data structure address. bit description 31:12 base address (low) ? r/w. these bits correspond to memory address signals [31:12], respectively. 11:0 reserved. must be written as 0s. during runtime, the value of these bits are undefined. intel ? 82801eb ich5 / 82801er ich5r datasheet 507 ehci controller registers (d29:f7) 13.2.11 asynclistaddr?current asynchronous list address register offset: caplength + 18 ? 1bh attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains the address of the next asynchronous queue head to be executed. since the ich5 host controller operates in 64-bit mode (as indicated by a 1 in 64-bit addressing capability field in the hccparams register), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register. bits [4:0] of this register cannot be modified by system software and will always return 0s when read. the memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. 13.2.12 configflag?configure flag register offset: caplength + 40 ? 43h attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains the address of the next asynchronous queue head to be executed. since the ich5 host controller operates in 64-bit mode (as indicated by a 1 in 64-bit addressing capability field in the hccparams register), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register. bits [4:0] of this register cannot be modified by system software and will always return 0s when read. the memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. bit description 31:5 link pointer low (lpl) ? r/w. these bits correspond to memory address signals [31:5], respectively. this field may only reference a queue head (qh). 4:0 reserved. these bits are reserved and their value has no effect on operation. bit description 31:1 reserved. read from this field will always return 0. 0 configure flag (cf) ? r/w. host software sets this bit as the last action in its process of configuring the host controller. this bit controls the default port-routing control logic. bit values and side-effects are listed below. see section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 for operation details. 0 = port routing control logic default-routes each port to the classic host controllers (default). 1 = port routing control logic default-routes all ports to this host controller. 508 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.2.13 portsc?port n status and control register offset: port 0: caplength + 44 ? 47h port 1: caplength + 48 ? 4bh port 2: caplength + 4c ? 4fh port 3: caplength + 50 ? 53h port 4: caplength + 54 ? 57h port 5: caplength + 58 ? 5bh port 6: caplength + 5c ? 5fh port 7: caplength + 60 ? 63h attribute: r/w, r/wc, ro default value: 00003000h size: 32 bits a host controller must implement one or more port registers. software uses the n_port information from the structural parameters register to determine how many ports need to be serviced. all ports have the structure defined below. software must not write to unreported port status and control registers. this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. the initial conditions of a port are: ? no device connected ? port disabled. when a device is attached, the port state transitions to the attached state and system software will process this as with any status change notification. refer to section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 for operational requirements for how change events interact with port suspend mode. bit description 31:23 reserved. these bits are reserved for future use and will return a value of 0s when read. 22 wake on overcurrent enable (wkoc_e) ? r/w. 0 = disable (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the overcurrent active bit (bit 4 of this register) is set. 21 wake on disconnect enable (wkdscnnt_e) ? r/w. 0 = disable (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the current connect status changes from connected to disconnected (i.e., bit 0 of this register changes from 1 to 0). 20 wake on connect enable (wkcnnt_e) ? r/w. 0 = disable (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the current connect status changes from disconnected to connected (i.e., bit 0 of this register changes from 0 to 1). intel ? 82801eb ich5 / 82801er ich5r datasheet 509 ehci controller registers (d29:f7) 19:16 port test control ? r/w. when this field is 0s, the port is not operating in a test mode. a non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. the encoding of the test mode bits are (0110b ? 1111b are reserved): bits test mode 0000b test mode not enabled (default) 0001b test j_state 0010b test k_state 0011b test se0_nak 0100b test packet 0101b test force_enable refer to universal serial bus revision 2.0 specification , chapter 7 for details on each test mode. 15:14 reserved ? r/w. should be written to =00b. 13 port owner ? r/w. default = 1b. this bit unconditionally goes to a 0 when the configured flag bit in the usb2.0_cmd register makes a 0 to 1 transition. system software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). software writes a 1 to this bit when the attached device is not a high-speed device. a 1 in this bit means that a companion host controller owns and controls the port. see section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 for operational details. 12 port power (pp) ? ro. read-only with a value of 1. this indicates that the port does have power. 11:10 line status ? ro.these bits reflect the current logical levels of the d+ (bit 11) and d? (bit 10) signal lines. these bits are used for detection of low-speed usb devices prior to the port reset and enable sequence. this field is valid only when the port enable bit is 0 and the current connect status bit is set to a 1. 00 = se0 10 = j-state 01 = k-state 11 = undefined 9 reserved. this bit will return a 0 when read. 8 port reset ? r/w. default = 0. when software writes a 1 to this bit (from a 0), the bus reset sequence as defined in the universal serial bus revision 2.0 specification is started. software writes a 0 to this bit to terminate the bus reset sequence. software must keep this bit at a 1 long enough to guarantee the reset sequence completes as specified in the universal serial bus revision 2.0 specification . 1 = port is in reset. 0 = port is not in reset. note: when software writes a 0 to this bit, there may be a delay before the bit status changes to a 0. the bit status will not read as a 0 until after the reset has completed. if the port is in high- speed mode after reset is complete, the host controller will automatically enable this port (e.g., set the port enable bit to a 1). a host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from 0 to 1. for example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2 ms of software writing this bit to a 0. the hchalted bit in the usb2.0_sts register should be a 0 before software attempts to use this bit. the host controller may hold port reset asserted to a 1 when the hchalted bit is a 1. this bit is 0 if port power is 0 note: system software should not attempt to reset a port if the hchalted bit in the usb2.0_sts register is a 1. doing so will result in undefined behavior. bit description 510 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 7 suspend ? r/w. 0 = port not in suspend state.(default) 1 = port in suspend state. port enabled bit and suspend bit of this register define the port states as follows: port enabled, suspend bits port state 0, x disable 1, 0 enable 1, 1 suspend when in suspend state, downstream propagation of data is blocked on this port, except for port reset. note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port depending on the activity on the port. the host controller will unconditionally set this bit to a 0 when software sets the force port resume bit to a 0 (from a 1). a write of 0 to this bit is ignored by the host controller. if host software sets this bit to a 1 when the port is not enabled (i.e., port enabled bit is a 0) the results are undefined. 6 force port resume ? r/w. 0 = no resume (k-state) detected/driven on port. (default) 1 = resume detected/driven on port. software sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected while the port is in the suspend state. when this bit transitions to a 1 because a j-to-k transition is detected, the port change detect bit in the usb2.0_sts register is also set to a 1. if software sets this bit to a 1, the host controller must not set the port change detect bit. note: when the ehci controller owns the port, the resume sequence follows the defined sequence documented in the universal serial bus revision 2.0 specification . the resume signaling (full-speed 'k') is driven on the port as long as this bit remains a 1. software must appropriately time the resume and set this bit to a 0 when the appropriate amount of time has elapsed. writing a 0 (from 1) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle). this bit will remain a 1 until the port has switched to the high-speed idle. 5 overcurrent change ? r/wc. the functionality of this bit is not dependent upon the port owner. software clears this bit by writing a 1 to it. 0 = no change. (default) 1 = there is a change to overcurrent active. 4 overcurrent active ? ro. 0 = this port does not have an overcurrent condition. (default) 1 = this port currently has an overcurrent condition. this bit will automatically transition from 1 to 0 when the over current condition is removed. the intel ? ich5 automatically disables the port when the overcurrent active bit is 1. 3 port enable/disable change ? r/wc. for the root hub, this bit gets set to a 1 only when a port is disabled due to the appropriate conditions existing at the eof2 point (see chapter 11 of the universal serial bus revision 2.0 specification for the definition of a port error). this bit is not set due to the disabled-to-enabled transition, nor due to a disconnect. software clears this bit by writing a 1 to it. 0 = no change in status. (default). 1 = port enabled/disabled status has changed. bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 511 ehci controller registers (d29:f7) 2 port enabled/disabled ? r/w. ports can only be enabled by the host controller as a part of the reset and enable. software cannot enable a port by writing a 1 to this bit. ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. note that the bit status does not change until the port state actually changes. there may be a delay in disabling or enabling a port due to other host controller and bus events. 0 = disable 1 = enable (default) 1 connect status change ? r/wc. this bit indicates a change has occurred in the port?s current connect status. software sets this bit to 0 by writing a 1 to it. 0 = no change (default). 1 = change in current connect status. the host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be ?setting? an already-set bit (i.e., the bit will remain set). 0 current connect status ? ro. this value reflects the current state of the port, and may not correspond directly to the event that caused the connect status change bit (bit 1) to be set. 0 = no device is present. (default) 1 = device is present on port. bit description 512 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) usb 2.0-based debug port register the debug port?s registers are located in the same memory area, defined by the base address register (bar), as the standard ehci registers. the base offset for the debug port registers (a0h) is declared in the debug port base offset capability register at configuration offset 5ah. the specific ehci port that supports this debug capability is indicated by a 4-bit field (bits 20 ? 23) in the hcsparams register of the ehci controller. the address map of the debug port registers is shown in table 165 . notes: 1. all of these registers are implemented in the core well and reset by pcirst#, ehc hcreset, and a ehc d3-to-d0 transition . 2. the hardware associated with this register provides no checks to ensure that software programs the interface correctly. how the hardware behaves when programmed illegally is undefined. 13.2.14 cntl_sts?control/status register offset: a0h attribute: r/w, r/wc, ro, wo default value: 0000h size: 32 bits table 165. debug port register address map offset mnemonic register name default type a0h cntl_sts control/status 0000h r/w, r/wc, ro, wo a4h usbpid usb pids 00h r/w, ro a8h databuf[3:0] data buffer (bytes 3:0) 00000000h r/w ach databuf[7:4] data buffer (bytes 7:4) 00000000h r/w b0h config configuration 00007f01h r/w bit description 31 reserved 30 owner_cnt ? r/w. 0 = ownership of the debug port is not forced to the ehci controller (default) 1 = ownership of the debug port is forced to the ehci controller (i.e. immediately taken away from the companion classic usb host controller) if the port was already owned by the ehci controller, then setting this bit has no effect. this bit overrides all of the ownership-related bits in the standard ehci registers. 29 reserved 28 enabled_cnt ? r/w. 0 = software can clear this by writing a 0 to it. the hardware clears this bit for the same conditions where the port enable/disable change bit (in the portsc register) is set. (default) 1 = debug port is enabled for operation. software can directly set this bit if the port is already enabled in the associated portsc register (this is enforced by the hardware). 27:17 reserved 16 done_sts ? r/wc. software can clear this by writing a 1 to it. 0 = request not complete 1 = set by hardware to indicate that the request is complete. intel ? 82801eb ich5 / 82801er ich5r datasheet 513 ehci controller registers (d29:f7) notes: 1. software should do read-modify-write operations to this register to preserve the contents of bits not being modified. this include reserved bits. 2. to preserve the usage of reserved bits in the future, software should always write the same value read from the bit until it is defined. reserved bits will always return 0 when read. 15:12 link_id_sts ? ro. this field identifies the link interface. 0h = hardwired. indicates that it is a usb debug port. 11 reserved. this bit returns 0 when read. writes have no effect. 10 in_use_cnt ? r/w. set by software to indicate that the port is in use. cleared by software to indicate that the port is free and may be used by other software. this bit is cleared after reset. (this bit has no affect on hardware.) 9:7 exception_sts ? ro. this field indicates the exception when the error_good#_sts bit is set. this field should be ignored if the error_good#_sts bit is 0. 000 =no error. (default) note: this should not be seen, since this field should only be checked if there is an error. 001 =transaction error: indicates the usb 2.0 transaction had an error (crc, bad pid, timeout, etc.) 010 =hardware error. request was attempted (or in progress) when port was suspended or reset. all other combinations are reserved 6 error_good#_sts ? ro. 0 = hardware clears this bit to 0 after the proper completion of a read or write. (default) 1 = error has occurred. details on the nature of the error are provided in the exception field. 5 go_cnt ? wo. 0 = hardware clears this bit when hardware sets the done_sts bit. (default) 1 = causes hardware to perform a read or write request. note: writing a 1 to this bit when it is already set may result in undefined behavior. 4 write_read#_cnt ? r/w. software clears this bit to indicate that the current request is a read. software sets this bit to indicate that the current request is a write. 0 = read (default) 1 = write 3:0 data_len_cnt ? r/w. this field is used to indicate the size of the data to be transferred. default = 0h. for write operations, this field is set by software to indicate to the hardware how many bytes of data in data buffer are to be transferred to the console. a value of 0h indicates that a zero-length packet should be sent. a value of 1?8 indicates 1?8 bytes are to be transferred. values 9?fh are illegal and how hardware behaves if used is undefined. for read operations, this field is set by hardware to indicate to software how many bytes in data buffer are valid in response to a read operation. a value of 0h indicates that a zero-length packet was returned and the state of data buffer is not defined. a value of 1?8 indicates 1?8 bytes were received. hardware is not allowed to return values 9?fh. the transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the transfer size is reached. bit description 514 intel ? 82801eb ich5 / 82801er ich5r datasheet ehci controller registers (d29:f7) 13.2.15 usbpid?usb pids register offset: a4h attribute: rw, ro default value: 0000h size: 32 bits this dword register is used to communicate pid information between the usb debug driver and the usb debug port. the debug port uses some of these fields to generate usb packets, and uses other fields to return pid information to the usb debug driver. 13.2.16 databuf[7:0]?data buffer bytes[7:0] register offset: a8?afh attribute: r/w default value: 0000000000000000h size: 64 bits this register can be accessed as eight, separate 8-bit registers or two, separate 32-bit register. 13.2.17 config?configuration register offset: b0?b3h attribute: r/w default value: 00007f01h size: 32 bits bit description 31:24 reserved: these bits will return 0 when read. writes will have no effect. 23:16 received_pid_sts[23:16] ? ro. hardware updates this field with the received pid for transactions in either direction. when the controller is writing data, this field is updated with the handshake pid that is received from the device. when the host controller is reading data, this field is updated with the data packet pid (if the device sent data), or the handshake pid (if the device naks the request). this field is valid when the hardware clears the go_done#_cnt bit. 15:8 send_pid_cnt[15:8] ? r/w. hardware sends this pid to begin the data packet when sending data to usb (i.e., write_read#_cnt is asserted). software typically sets this field to either data0 or data1 pid values. 7:0 token_pid_cnt[7:0] ? r/w. hardware sends this pid as the token pid for each usb transaction. software typically sets this field to either in, out, or setup pid values. bit description 63:0 databuffer[63:0] ? r/w. this field is the 8 bytes of the data buffer. bits 7:0 correspond to least significant byte (byte 0). bits 63:56 correspond to the most significant byte (byte 7). the bytes in the data buffer must be written with data before software initiates a write request. for a read request, the data buffer contains valid data when done_sts bit is cleared by the hardware, error_good#_sts is cleared by the hardware, and the data_length_cnt field indicates the number of bytes that are valid. bit description 31:15 reserved 14:8 usb_address_cnf ? r/w. this 7-bit field identifies the usb device address used by the controller for all token pid generation. (default = 7fh) 7:4 reserved 3:0 usb_endpoint_cnf ? r/w. this 4-bit field identifies the endpoint used by the controller for all token pid generation. (default = 01h) intel ? 82801eb ich5 / 82801er ich5r datasheet 515 smbus controller registers (d31:f3) smbus controller registers (d31:f3) 14 14.1 pci configuration registers (smbus?d31:f3) note: registers address locations that are not shown in table 166 should be treated as reserved (see section 6.2 for details). 14.1.1 vid?vendor identification register (smbus?d31:f3) address: 00 ? 01h attribute: ro default value: 8086h size: 16 bits table 166. smbus controller pci register address map (smbus?d31:f3) offset mnemonic register name default type 00?01h vid vendor identification 8086 ro 02?03h did device identification 24d3h ro 04?05h pcicmd pc i command 0000h r/w, ro 06?07h pcists pci status 0280h ro, r/wc 08h rid revision identification see register description ro 0ah scc sub class code 05h ro 0bh bcc base class code 0ch ro 20?23h smb_base smbus base address 00000001h r/w, ro 2c?2dh svid subsystem vendor identification 00h ro 2e?2fh sid subsystem identification 00h r/wo 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin 02h ro 40h hostc host configuration 00h r/w bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. 516 intel ? 82801eb ich5 / 82801er ich5r datasheet smbus controller registers (d31:f3) 14.1.2 did?device identification register (smbus?d31:f3) address: 02 ? 03h attribute: ro default value: 24d3h size: 16 bits 14.1.3 pcicmd?pci command register (smbus?d31:f3) address: 04 ? 05h attributes: ro, r/w default value: 0000h size: 16 bits bit description 15:0 device id ? ro. bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = enable 1 = disables smbus to assert its pirqb# signal. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? ro. hardwired to 0. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? ro. hardwired to 0. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? ro. hardwired to 0. 1 memory space enable (mse) ? ro. hardwired to 0. 0 i/o space enable (iose) ? r/w. 0 = disable 1 = enables access to the sm bus i/o space registers as defined by the base address register. intel ? 82801eb ich5 / 82801er ich5r datasheet 517 smbus controller registers (d31:f3) 14.1.4 pcists?pci status register (smbus?d31:f3) address: 06 ? 07h attributes: ro, r/wc default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 14.1.5 rid?revision identification register (smbus?d31:f3) offset address: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? ro. hardwired to 0. 14 signaled system error (sse) ? ro. hardwired to 0. 13 received master abort (rma) ? ro. hardwired to 0. 12 received target abort (rta) ? ro. hardwired to 0. 11 signaled target abort (sta) ? r/wc. 0 = intel ? ich5 did not terminate transaction for this function with a target abort. 1 = the function is targeted with a transaction that the ich5 terminates with a target abort. 10:9 devsel# timing status (devt) ? ro. this 2-bit field defines the timing for devsel# assertion for positive decode. 01 = medium timing. 8 data parity error detected (dped) ? ro. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (udf) ? ro. hardwired to 0. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. hardwired to 0 because there are no capability list structures in this function. 3 interrupt status (ints) ? ro. this bit indicates that an interrupt is pending. it is independent from the state of the interrupt enable bit in the pci command register. 2:0 reserved bit description 7:0 revision id (rid) ? ro. refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. 518 intel ? 82801eb ich5 / 82801er ich5r datasheet smbus controller registers (d31:f3) 14.1.6 scc?sub class code register (smbus?d31:f3) address offset: 0ah attributes: ro default value: 05h size: 8 bits 14.1.7 bcc?base class code register (smbus?d31:f3) address offset: 0bh attributes: ro default value: 0ch size: 8 bits 14.1.8 smb_base?smbus base address register (smbus?d31:f3) address offset: 20 ? 23h attribute: r/w, ro default value: 00000001h size: 32-bits 14.1.9 svid ? subsystem vendor identification register (smbus?d31:f2/f4) address offset: 2ch ? 2dh attribute: ro default value: 00h size: 16 bits lockable: no power well: core bit description 7:0 sub class code (scc) ? ro. 05h = sm bus serial controller. bit description 7:0 base class code (bcc) ? ro. 0ch = serial controller. bit description 31:16 reserved ? ro 15:5 base address ? r/w. this field provides the 32-byte system i/o base address for the intel ? ich5 smb logic. 4:1 reserved ? ro 0 io space indicator ? ro. hardwired to 1 indicating that the smb logic is i/o mapped. bit description 15:0 subsystem vendor id (svid) ? ro. the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide svid register. intel ? 82801eb ich5 / 82801er ich5r datasheet 519 smbus controller registers (d31:f3) 14.1.10 sid ? subsystem identification register (smbus?d31:f2/f4) address offset: 2eh ? 2fh attribute: ro default value: 00h size: 16 bits lockable: no power well: core 14.1.11 int_ln?interrupt line register (smbus?d31:f3) address offset: 3ch attributes: r/w default value: 00h size: 8 bits 14.1.12 int_pn?interrupt pin register (smbus?d31:f3) address offset: 3dh attributes: ro default value: 02h size: 8 bits bit description 15:0 subsystem id (sid) ? ro. the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide sid register. bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich5. it is to communicate to software the interrupt line that the interrupt pin is connected to pirqb#. bit description 7:0 interrupt pin (int_pn) ? ro. 02h = indicates that the intel ? ich5 smbus controller will drive pirqb# as its interrupt line. 520 intel ? 82801eb ich5 / 82801er ich5r datasheet smbus controller registers (d31:f3) 14.1.13 hostc?host configuration register (smbus?d31:f3) address offset: 40h attribute: r/w default value: 00h size: 8 bits bit description 7:3 reserved 2 i 2 c_en ? r/w. 0 = smbus behavior. 1 = the intel ? ich5 is enabled to communicate with i 2 c devices. this will change the formatting of some commands. 1 smb_smi_en ? r/w. 0 = smbus interrupts will not generate an smi#. 1 = any source of an smb interrupt will instead be routed to generate an smi#. refer to section 5.21.4 (interrupts / smi#). this bit needs to be set for smbalert# to be enabled. 0 smbus host enable (hst_en) ? r/w. 0 = disable the smbus host controller. 1 = enable. the smb host controller interface is enabled to execute commands. the intren bit needs to be enabled for the smb host controller to interrupt or smi#. note that the smb host controller will not respond to any new requests until all interrupt requests have been cleared. intel ? 82801eb ich5 / 82801er ich5r datasheet 521 smbus controller registers (d31:f3) 14.2 smbus i/o registers table 167. smbus i/o register address map offset mnemonic register name default type 00h hst_sts host status 00h r/wc, ro, r/wc (special) 02h hst_cnt host control 00h r/w, wo 03h hst_cmd host command 00h r/w 04h xmit_slva transmit slave address 00h r/w 05h hst_d0 host data 0 00h r/w 06h hst_d1 host data 1 00h r/w 07h host_block_db host block data byte 00h r/w 08h pec packet error check 00h r/w 09h rcv_slva receive slave address 44h r/w 0ah slv_data receive slave data 0000h ro 0ch aux_sts auxiliary status 00h r/wc 0dh aux_ctl auxiliary control 00h r/w 0eh smlink_pin_ctl smlink pin control (tco compatible mode) see register description r/w, ro 0fh smbus_pin_ctl smbus pin control see register description r/w, ro 10h slv_sts slave status 00h r/wc 11h slv_cmd slave command 00h r/w 14h notify_daddr notify device address 00h ro 16h notify_dlow notify data low byte 00h ro 17h notify_dhigh notify data high byte 00h ro 522 intel ? 82801eb ich5 / 82801er ich5r datasheet smbus controller registers (d31:f3) 14.2.1 hst_sts?host status register (smbus?d31:f3) register offset: 00h attribute: r/wc, r/wc (special), ro default value: 00h size: 8-bits all status bits are set by hardware and cleared by the software writing a one to the particular bit position. bit description 7 byte done status (ds) ? r/wc. 0 = software can clear this by writing a 1 to it. 1 = host controller received a byte (for block read commands) or if it has completed transmission of a byte (for block write commands) when the 32-byte buffer is not being used. note that this bit will be set, even on the last byte of the transfer. this bit is not set when transmission is due to the d110 interface heartbeat. this bit has no meaning for block transfers when the 32-byte buffer is enabled. note: when the last byte of a block message is received, the host controller will set this bit. however, it will not immediately set the intr bit (bit 1 in this register). when the interrupt handler clears the byte_done_sts bit, the message is considered complete, and the host controller will then set the intr bit (and generate another interrupt). thus, for a block message of n bytes, the intel ? ich5 will generate n+1 interrupts. the interrupt handler needs to be implemented to handle these cases. 6 inuse_sts ? r/wc (special). this bit is used as semaphore among various independent software threads that may need to use the ich5?s smbus logic, and has no other effect on hardware. 0 = after a full pci reset, a read to this bit returns a 0. 1 = after the first read, subsequent reads will return a 1. a write of a 1 to this bit will reset the next read value to 0. writing a 0 to this bit has no effect. software can poll this bit until it reads a 0, and will then own the usage of the host controller. 5 smbalert_sts ? r/wc. 0 = interrupt or smi# was not generated by smbalert#. software clears this bit by writing a 1 to it. 1 = the source of the interrupt or smi# was the smbalert# signal. this bit is only cleared by software writing a 1 to the bit position or by rsmrst# going low. if the signal is programmed as a gpio, then this bit will never be set. 4 failed ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the source of the interrupt or smi# was a failed bus transaction. this bit is set in response to the kill bit being set to terminate the host transaction. 3 bus_err ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the source of the interrupt of smi# was a transaction collision. intel ? 82801eb ich5 / 82801er ich5r datasheet 523 smbus controller registers (d31:f3) 14.2.2 hst_cnt?host control register (smbus?d31:f3) register offset: 02h attribute: r/w, wo default value: 00h size: 8-bits note: a read to this register will clear the byte pointer of the 32-byte buffer. 2 dev_err ? r/wc. 0 = software clears this bit by writing a 1 to it. the ich5 will then deassert the interrupt or smi#. 1 = the source of the interrupt or smi# was due to one of the following: ?illegal command field, ?unclaimed cycle (host initiated), ?host device time-out error. 1 intr ? r/wc (special). this bit can only be set by termination of a command. intr is not dependent on the intren bit of the host controller register (offset 02h). it is only dependent on the termination of the command. if the intren bit is not set, then the intr bit will be set, although the interrupt will not be generated. software can poll the intr bit in this non-interrupt case. 0 = software clears this bit by writing a 1 to it. the ich5 then deasserts the interrupt or smi#. 1 = the source of the interrupt or smi# was the successful completion of its last command. 0 host_busy ? ro. 0 = cleared by the ich5 when the current transaction is completed. 1 = indicates that the ich5 is running a command from the host interface. no smb registers should be accessed while this bit is set, except the block data byte register. the block data byte register can be accessed when this bit is set only when the smb_cmd bits in the host control register are programmed for block command or i 2 c read command. this is necessary in order to check the done_sts bit. bit description bit description 7 pec_en . ? r/w. 0 = smbus host controller does not perform the transaction with the pec phase appended. 1 = causes the host controller to perform the smbus transaction with the packet error checking phase appended. for writes, the value of the pec byte is transferred from the pec register. for reads, the pec byte is loaded in to the pec register. this bit must be written prior to the write in which the start bit is set. 6 start ? wo. 0 = this bit will always return 0 on reads. the host_busy bit in the host status register (offset 00h) can be used to identify when the intel ? ich5 has finished the command. 1 = writing a 1 to this bit initiates the command described in the smb_cmd field. all registers should be setup prior to writing a 1 to this bit position. 5 last_byte ? wo. this bit is used for block read commands. 1 = software sets this bit to indicate that the next byte will be the last byte to be received for the block. this causes the ich5 to send a nack (instead of an ack) after receiving the last byte. note: once the second_to_sts bit in tco2_sts register (d31:f0, tcobase+6h, bit 1) is set, the last_byte bit also gets set. while the second_to_sts bit is set, the last_byte bit cannot be cleared. this prevents the ich5 from running some of the smbus commands (block read/write, i 2 c read, block i 2 c write). 524 intel ? 82801eb ich5 / 82801er ich5r datasheet smbus controller registers (d31:f3) 4:2 smb_cmd ? r/w. the bit encoding below indicates which command the ich5 is to perform. if enabled, the ich5 will generate an interrupt or smi# when the command has completed if the value is for a non-supported or reserved command, the ich5 will set the device error (dev_err) status bit and generate an interrupt when the start bit is set. the ich5 will perform no command, and will not operate until dev_err is cleared. 000 = quick : the slave address and read/write value (bit 0) are stored in the transmit slave address register. 001 = byte : this command uses the transmit slave address and command registers. bit 0 of the slave address register determines if this is a read or write command. 010 = byte data : this command uses the transmit slave address, command, and data0 registers. bit 0 of the slave address register determines if this is a read or write command. if it is a read, the data0 register will contain the read data. 011 = word data : this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave address register determines if this is a read or write command. if it is a read, after the command completes, the data0 and data1 registers will contain the read data. 100 = process call: this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave address register determines if this is a read or write command. after the command completes, the data0 and data1 registers will contain the read data. 101 = block : this command uses the transmit slave address, command, data0 registers, and the block data byte register. for block write, the count is stored in the data0 register and indicates how many bytes of data will be transferred. for block reads, the count is received and stored in the data0 register. bit 0 of the slave address register selects if this is a read or write command. for writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. 110 = i 2 c read : this command uses the transmit slave address, command, data0, data1 registers, and the block data byte register. the read data is stored in the block data byte register. the ich5 continues reading data until the nak is received. 111 = block process: this command uses the transmit slave address, command, data0 and the block data byte register. for block write, the count is stored in the data0 register and indicates how many bytes of data will be transferred. for block read, the count is received and stored in the data0 register. bit 0 of the slave address register always indicate a write command. for writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. note: e32b bit in the auxiliary control register must be set for this command to work. 1 kill ? r/w. 0 = normal smbus host controller functionality. 1 = kills the current host transaction taking place, sets the failed status bit, and asserts the interrupt (or smi#). this bit, once set, must be cleared by software to allow the smbus host controller to function normally. 0 intren ? r/w. 0 = disable 1 = enable the generation of an interrupt or smi# upon the completion of the command. bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 525 smbus controller registers (d31:f3) 14.2.3 hst_cmd?host command register (smbus?d31:f3) register offset: 03h attribute: r/w default value: 00h size: 8 bits 14.2.4 xmit_slva?transmit slave address register (smbus?d31:f3) register offset: 04h attribute: r/w default value: 00h size: 8 bits this register is transmitted by the host controller in the slave address field of the smbus protocol. 14.2.5 hst_d0?host data 0 register (smbus?d31:f3) register offset: 05h attribute: r/w default value: 00h size: 8 bits 14.2.6 hst_d1?host data 1 register (smbus?d31:f3) register offset: 06h attribute: r/w default value: 00h size: 8 bits bit description 7:0 this 8-bit field is transmitted by the host controller in the command field of the smbus protocol during the execution of any command. bit description 7:1 address ? r/w. this field provides a 7-bit address of the targeted slave. 0 rw ? r/w. direction of the host transfer. 0 = write 1 = read bit description 7:0 data0/count ? r/w. this field contains the eight bit data sent in the data0 field of the smbus protocol. for block write commands, this register reflects the number of bytes to transfer. this register should be programmed to a value between 1 and 32 for block counts. a count of 0 or a count above 32 will result in unpredictable behavior. the host controller does not check or log illegal block counts. bit description 7:0 data1 ? r/w. this 8-bit register is transmitted in the data1 field of the smbus protocol during the execution of any command. 526 intel ? 82801eb ich5 / 82801er ich5r datasheet smbus controller registers (d31:f3) 14.2.7 host_block_db?host block data byte register (smbus?d31:f3) register offset: 07h attribute: r/w default value: 00h size: 8 bits 14.2.8 pec?packet error check (pec) register (smbus?d31:f3) register offset: 08h attribute: r/w default value: 00h size: 8 bits bit description 7:0 block data (bdta) ? r/w. this is either a register, or a pointer into a 32-byte block array, depending upon whether the e32b bit is set in the auxiliary control register. when the e32b bit is cleared, this is a register containing a byte of data to be sent on a block write or read from on a block read. when the e32b bit is set, reads and writes to this register are used to access the 32-byte block data storage array. an internal index pointer is used to address the array, which is reset to 0 by reading the hctl register (offset 02h). the index pointer then increments automatically upon each access to this register. the transfer of block data into (read) or out of (write) this storage array during an smbus transaction always starts at index address 0. when the e2b bit is set, for writes, software will write up to 32-bytes to this register as part of the setup for the command. after the host controller has sent the address, command, and byte count fields, it will send the bytes in the sram pointed to by this register. when the e2b bit is cleared for writes, software will place a single byte in this register. after the host controller has sent the address, command, and byte count fields, it will send the byte in this register. if there is more data to send, software will write the next series of bytes to the sram pointed to by this register and clear the done_sts bit. the controller will then send the next byte. during the time between the last byte being transmitted to the next byte being transmitted, the controller will insert wait-states on the interface. when the e2b bit is set for reads, after receiving the byte count into the data0 register, the first series of data bytes go into the sram pointed to by this register. if the byte count has been exhausted or the 32-byte sram has been filled, the controller will generate an smi# or interrupt (depending on configuration) and set the done_sts bit. software will then read the data. during the time between when the last byte is read from the sram to when the done_sts bit is cleared, the controller will insert wait-states on the interface. bit description 7:0 pec_data ? r/w. this 8-bit register is written with the 8-bit crc value that is used as the smbus pec data prior to a write transaction. for read transactions, the pec data is loaded from the smbus into this register and is then read by software. software must ensure that the inuse_sts bit is properly maintained to avoid having this field over-written by a write transaction following a read transaction. intel ? 82801eb ich5 / 82801er ich5r datasheet 527 smbus controller registers (d31:f3) 14.2.9 rcv_slva?receive slave address register (smbus?d31:f3) register offset: 09h attribute: r/w default value: 44h size: 8 bits lockable: no power well: resume 14.2.10 slv_data?receive slave data register (smbus?d31:f3) register offset: 0ah attribute: ro default value: 0000h size: 16 bits lockable: no power well: resume this register contains the 16-bit data value written by the external smbus master. the processor can then read the value from this register. this register is reset by rsmrst#, but not pcirst# . 14.2.11 aux_sts?auxiliary status register (smbus?d31:f3) register offset: 0ch attribute: rw/c, ro default value: 00h size: 8 bits lockable: no power well: resume . bit description 7 reserved 6:0 slave_addr ? r/w. this field is the slave address that the intel ? ich5 decodes for read and write cycles. the default is not 0, so the smbus slave interface can respond even before the processor comes up (or if the processor is dead). this register is cleared by rsmrst#, but not by pcirst#. bit description 15:8 data message byte 1 (data_msg1) ? ro. see section 5.21.7 for a discussion of this field. 7:0 data message byte 0 (data_msg0) ? ro. see section 5.21.7 for a discussion of this field. bit description 7:2 reserved 1 smbus tco mode (stco) ? ro. this bit reflects the strap setting of tco compatible mode vs. advanced tco mode. 0 = intel ? ich5 is in the compatible tco mode. 1 = ich5 is in the advanced tco mode. 0 crc error (crce) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set if a received message contained a crc error. when this bit is set, the derr bit of the host status register will also be set. this bit will be set by the controller if a software abort occurs in the middle of the crc portion of the cycle or an abort happens after the ich5 has received the final data bit transmitted by an external slave. 528 intel ? 82801eb ich5 / 82801er ich5r datasheet smbus controller registers (d31:f3) 14.2.12 aux_ctl?auxiliary control register (smbus?d31:f3) register offset: 0dh attribute: rw default value: 00h size: 8 bits lockable: no power well: resume . 14.2.13 smlink_pin_ctl?smlink pin control register (smbus?d31:f3) register offset: 0eh attribute: r/w, ro default value: see below size: 8 bits note: this register is in the resume well and is reset by rsmrst#. this register is only applicable in the tco compatible mode. bit description 7:2 reserved 1 enable 32-byte buffer (e32b) ? r/w. 0 = disable 1 = enable. when set, the host block data register is a pointer into a 32-byte buffer, as opposed to a single register. this enables the block commands to transfer or receive up to 32-bytes before the intel ? ich5 generates an interrupt. 0 automatically append crc (aac) ? r/w. 0 = ich5 will not automatically append the crc. 1 = the ich5 will automatically append the crc. this bit must not be changed during smbus transactions or undetermined behavior will result. it should be programmed only once during the lifetime of the function. bit description 7:3 reserved 2 smlink_clk_ctl ? r/w. 0 = intel ? ich5 will drive the smlink0 pin low, independent of what the other smlink logic would otherwise indicate for the smlink0 pin. 1 = the smlink0 pin is not overdriven low. the other smlink logic controls the state of the pin. (default) 1 smlink1_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smlink1 pin. this allows software to read the current state of the pin. 0 = low 1 = high 0 smlink0_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smlink0 pin. this allows software to read the current state of the pin. 0 = low 1 = high intel ? 82801eb ich5 / 82801er ich5r datasheet 529 smbus controller registers (d31:f3) 14.2.14 smbus_pin_ctl?smbus pin control register (smbus?d31:f3) register offset: 0fh attribute: r/w, ro default value: see below size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 14.2.15 slv_sts?slave status register (smbus?d31:f3) register offset: 10h attribute: r/wc default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. all bits in this register are implemented in the 64 khz clock domain. therefore, software must poll this register until a write takes effect before assuming that a write has completed internally. bit description 7:3 reserved 2 smbclk_ctl ? r/w. 1 = the smbclk pin is not overdriven low. the other smbus logic controls the state of the pin. 0 = intel ? ich5 drives the smbclk pin low, independent of what the other smb logic would otherwise indicate for the smbclk pin. (default) 1 smbdata_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smbdata pin. this allows software to read the current state of the pin. 0 = low 1 = high 0 smbclk_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smbclk pin. this allows software to read the current state of the pin. 0 = low 1 = high bit description 7:1 reserved 0 host_notify_sts ? r/wc. the intel ? ich5 sets this bit to a 1 when it has completely received a successful host notify command on the smlink pins. software reads this bit to determine that the source of the interrupt or smi# was the reception of the host notify command. software clears this bit after reading any information needed from the notify address and data registers by writing a 1 to this bit. note that the ich5 will allow the notify address and data registers to be over-written once this bit has been cleared. when this bit is 1, the ich5 will nack the first byte (host address) of any new ?host notify? commands on the smlink. writing a 0 to this bit has no effect. 530 intel ? 82801eb ich5 / 82801er ich5r datasheet smbus controller registers (d31:f3) 14.2.16 slv_cmd?slave command register (smbus?d31:f3) register offset: 11h attribute: r/w default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 14.2.17 notify_daddr?notify device address register (smbus?d31:f3) register offset: 14h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. bit description 7:2 reserved 2 smbalert_dis ? r/w. 0 = allows the generation of the interrupt or smi#. 1 = software sets this bit to block the generation of the interrupt or smi# due to the smbalert# source. this bit is logically inverted and anded with the smbalert_sts bit. the resulting signal is distributed to the smi# and/or interrupt generation logic. this bit does not effect the wake logic. 1 host_notify_wken ? r/w. software sets this bit to 1 to enable the reception of a host notify command as a wake event. when enabled this event is ?or?ed in with the other smbus wake events and is reflected in the smb_wak_sts bit of the general purpose event 0 status register. 0 = disable 1 = enable 0 host_notify_intren ? r/w. software sets this bit to 1 to enable the generation of interrupt or smi# when host_notify_sts is 1. this enable does not affect the setting of the host_notify_sts bit. when the interrupt is generated, either pirqb# or smi# is generated, depending on the value of the smb_smi_en bit (d31, f3, off40h, b1). if the host_notify_sts bit is set when this bit is written to a 1, then the interrupt (or smi#) will be generated. the interrupt (or smi#) is logically generated by and?ing the sts and intren bits. 0 = disable 1 = enable bit description 7:1 device_address ? ro. this field contains the 7-bit device address received during the host notify protocol of the system management bus (smbus) specification, version 2.0. software should only consider this field valid when the host_notify_sts bit is set to 1. 0 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 531 smbus controller registers (d31:f3) 14.2.18 notify_dlow?notify data low byte register (smbus?d31:f3) register offset: 16h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 14.2.19 notify_dhigh?notify data high byte register (smbus?d31:f3) register offset: 17h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. bit description 7:0 data_low_byte ? ro. this field contains the first (low) byte of data received during the host notify protocol of the system management bus (smbus) specification, version 2.0. software should only consider this field valid when the host_notify_sts bit is set to 1. bit description 7:0 data_high_byte ? ro. this field contains the second (high) byte of data received during the host notify protocol of the system management bus (smbus) specification, version 2.0. software should only consider this field valid when the host_notify_sts bit is set to 1. 532 intel ? 82801eb ich5 / 82801er ich5r datasheet smbus controller registers (d31:f3) this page is intentionally left blank. intel ? 82801eb ich5 / 82801er ich5r datasheet 533 ac ?97 audio controller registers (d31:f5) ac ?97 audio controller registers (d31:f5) 15 15.1 ac ?97 audio pci configuration space (audio? d31:f5) note: address locations that are not shown in table 168 should be treated as reserved (see section 6.2 for details). note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the following bios programmed registers as bios may not be invoked following the d3-to-d0 transition. all resume well registers will not be reset by the d3 hot to d0 transition. table 168. ac ?97 audio pci register address map (audio?d31:f5) offset mnemonic register name default access 00?01h vid vendor identification 8086h ro 02?03h did device identification 24d5h ro 04?05h pcicmd pci command 0000 r/w, ro 06?07h pcists pci status 0280h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00 ro 0ah scc sub class code 01h ro 0bh bcc base class code 04h ro 0eh headtyp header type 00h ro 10?13h nambbar native audio mixer base address 00000001h ro 14?17h nambbar native audio bus mastering base address 00000001h r/w, ro 18?1bh mmbar mixer base address (mem) 00000000h r/w, ro 1c?1fh mbbar bus master base address (mem) 00000000h r/w, ro 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 34h cap_ptr capabilities pointer 50h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin 02h ro 40h pcid programmable codec id 09h r/w 41h cfg configuration 00h r/w 50?51h pid pci power management capability id 0001h ro 52?53h pc pc -power management capabilities c9c2h ro 54?55h pcs power management control and status 0000h r/w, r/wc 534 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) core well registers not reset by the d3 hot to d0 transition: ? offset 2ch ? 2dh ? subsystem vendor id (svid) ? offset 2eh ? 2fh ? subsystem id (sid) ? offset 40h ? programmable codec id (pcid) ? offset 41h ? configuration (cfg) resume well registers will not be reset by the d3 hot to d0 transition: ? offset 54h ? 55h ? power management control and status (pcs) ? bus mastering register: global status register, bits 17:16 ? bus mastering register: sdata_in map register, bits 7:3 15.1.1 vid?vendor identification register (audio?d31:f5) offset: 00 ? 01h attribute: ro default value: 8086h size: 16 bits lockable: no power well: core 15.1.2 did?device identification register (audio?d31:f5) offset: 02 ? 03h attribute: ro default value: 24d5h size: 16 bits lockable: no power well: core bit description 15:0 vendor id. this is a 16-bit value assigned to intel. bit description 15:0 device id. intel ? 82801eb ich5 / 82801er ich5r datasheet 535 ac ?97 audio controller registers (d31:f5) 15.1.3 pcicmd?pci command register (audio?d31:f5) address offset: 04 ? 05h attribute: r/w, ro default value: 0000h size: 16 bits lockable: no power well: core pcicmd is a 16-bit control register. refer to the pci local bus specification, revision 2.3 f or complete details on each bit. bit description 15:11 reserved. read 0. 10 interrupt disable (id) ? r/w. 0 = the intx# signals may be asserted and msis may be generated. 1 = the ac ?97 controller?s intx# signal will be de-asserted and it may not generate msis. 9 fast back to back enable (fbe) ? ro. not implemented. hardwired to 0. 8 serr# enable (serr_en) ? ro. not implemented. hardwired to 0. 7 wait cycle control (wcc) ? ro. not implemented. hardwired to 0. 6 parity error response (per) ? ro. not implemented. hardwired to 0. 5 vga palette snoop (vps). not implemented. hardwired to 0. 4 memory write and invalidate enable (mwie) ? ro. not implemented. hardwired to 0. 3 special cycle enable (sce). not implemented. hardwired to 0. 2 bus master enable (bme) ? r/w. controls standard pci bus mastering capabilities. 0 = disable 1 = enable 1 memory space enable (mse) ? r/w. enables memory space addresses to the ac ?97 audio controller. 0 = disable 1 = enable 0 i/o space enable (iose) ? r/w. this bit controls access to the ac ?97 audio controller i/o space registers. 0 = disable (default). 1 = enable access to i/o space. the native pci mode base address register should be programmed prior to setting this bit. note: this bit becomes writable when the iose bit in offset 41h is set. if at any point software decides to clear the iose bit, software must first clear the ios bit. 536 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.1.4 pcists?pci status register (audio?d31:f5) offset: 06 ? 07h attribute: ro, r/wc default value 0280h size: 16 bits lockable: no power well: core pcista is a 16-bit status register. refer to the pci local bus specification, revision 2.3 for complete details on each bit. bit description 15 detected parity error (dpe). not implemented. hardwired to 0. 14 signaled system error (sse) ? ro. not implemented. hardwired to 0. 13 master abort status (mas) ? r/wc. software clears this bit by writing a 1 to it. 0 = no master abort generated. 1 = bus master ac '97 2.3 interface function, as a master, generates a master abort. 12 reserved ? ro. will always read as 0. 11 signaled target abort (sta) ? ro. not implemented. hardwired to 0. 10:9 devsel# timing status (dev_sts) ? ro. this 2-bit field reflects the intel ? ich5's devsel# timing when performing a positive decode. 01b = medium timing. 8 data parity error detected (dped) ? ro. not implemented. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. this bit indicates that the ich5 as a target is capable of fast back-to-back transactions. 6 udf supported ? ro. not implemented. hardwired to 0. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. indicates that the controller contains a capabilities pointer list. the first item is pointed to by looking at configuration offset 34h. 3 interrupt status (is) ? ro. 0 = this bit is 0 after the interrupt is cleared. 1 = this bit is 1 when the intx# is asserted. 2:0 reserved. intel ? 82801eb ich5 / 82801er ich5r datasheet 537 ac ?97 audio controller registers (d31:f5) 15.1.5 rid?revision identification register (audio?d31:f5) offset: 08h attribute: ro default value: see bit description size: 8 bits lockable: no power well: core 15.1.6 pi?programming interface register (audio?d31:f5) offset: 09h attribute: ro default value: 00h size: 8 bits lockable: no power well: core 15.1.7 scc?sub class code register (audio?d31:f5) address offset: 0ah attribute: ro default value: 01h size: 8 bits lockable: no power well: core 15.1.8 bcc?base class code register (audio?d31:f5) address offset: 0bh attribute: ro default value: 04h size: 8 bits lockable: no power well: core bit description 7:0 revision id ? ro. refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. bit description 7:0 programming interface ? ro. bit description 7:0 sub class code (scc) ? ro. 01h = audio device bit description 7:0 base class code (bcc) ? ro. 04h = multimedia device 538 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.1.9 headtyp?header type register (audio?d31:f5) address offset: 0eh attribute: ro default value: 00h size: 8 bits lockable: no power well: core 15.1.10 nambar?native audio mixer base address register (audio?d31:f5) address offset: 10 ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits lockable: no power well: core the native pci mode audio function uses pci base address register #1 to request a contiguous block of i/o space that is to be used for the native audio mixer software interface. the mixer requires 256 bytes of i/o space. native audio mixer and modem codec i/o registers are located from 00h to 7fh and reside in the codec. access to these registers will be decoded by the ac ?97 controller and forwarded over the ac-link to the codec. the codec will then respond with the register value. in the case of the split codec implementation, accesses to the different codecs are differentiated by the controller by using address offsets 00h ? 7fh for the primary codec and address offsets 80h ? feh for the secondary codec. note: the tertiary codec cannot be addressed via this address space. the tertiary space is only available from the new mmbar register. this register powers up as read only and only becomes write-able when the iose bit in offset 41h is set. for description of these i/o registers, refer to the ac ?97 v2.3 specification . bit description 7:0 header type ? ro. hardwired to 00h. bit description 31:16 hardwired to 0s. 15:8 base address ? r/w. these bits are used in the i/o space decode of the native audio mixer interface registers. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for the ac ?97 mixer, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. this configuration yields a maximum i/o block size of 256 bytes for this base address. 7:1 reserved. read as 0s. 0 resource type indicator (rte) ? ro. this bit defaults to 0 and changes to 1 if the iose bit is set (d31:f5:offset 41h, bit 0). when 1, this bit indicates a request for i/o space. intel ? 82801eb ich5 / 82801er ich5r datasheet 539 ac ?97 audio controller registers (d31:f5) 15.1.11 nabmbar?native audio bus mastering base address register (audio?d31:f5) address offset: 14 ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits lockable: no power well: core the native pci mode audio function uses pci base address register #1 to request a contiguous block of i/o space that is to be used for the native mode audio software interface. note: the dma registers for s/pdif and microphone in 2 cannot be addressed via this address space. these dma functions are only available from the new mbbar register. this register powers up as read only and only becomes write-able when the iose bit in offset 41h is set. 15.1.12 mmbar?mixer base address register (audio?d31:f5) address offset: 18 ? 1bh attribute: r/w, ro default value: 00000000h size: 32 bits lockable: no power well: core this bar creates 512 bytes of memory space to signify the base address of the register space. the lower 256 bytes of this space map to the same registers as the 256-byte i/o space pointed to by nambar. the lower 384 bytes are divided as follows: ? 128 bytes for the primary codec (offsets 00?7fh) ? 128 bytes for the secondary codec (offsets 80?ffh) ? 128 bytes for the tertiary codec (offsets 100h?17fh). ? 128 bytes of reserved space (offsets 180h?1ffh), returning all 0. bit description 31:16 hardwired to 0s 15:6 base address ? r/w. these bits are used in the i/o space decode of the native audio bus mastering interface registers. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for ac '97 bus mastering, the upper 16 bits are hardwired to 0, while bits 15:6 are programmable. this configuration yields a maximum i/o block size of 64 bytes for this base address. 5:1 reserved. read as 0s. 0 resource type indicator (rte) ? ro. this bit defaults to 0 and changes to 1 if the iose bit is set (d31:f5:offset 41h, bit 0). when 1, this bit indicates a request for i/o space. bit description 31:9 base address ? r/w. this field provides the lower 32-bits of the 512-byte memory offset to use for decoding the primary, secondary, and tertiary codec?s mixer spaces. 8:3 reserved. read as 0s. 2:1 type ? ro. hardwired to 00b to indicate the base address exists in 32-bit address space 0 resource type indicator (rte) ? ro. hardwired to 0 to indicate a request for memory space. 540 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.1.13 mbbar?bus master base address register (audio?d31:f5) address offset: 1c ? 1fh attribute: r/w, ro default value: 00000000h size: 32 bits lockable: no power well: core this bar creates 256-bytes of memory space to signify the base address of the bus master memory space. the lower 64-bytes of the space pointed to by this register point to the same registers as the mbbar. 15.1.14 svid?subsystem vendor identification register (audio?d31:f5) address offset: 2c ? 2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core the svid register, in combination with the subsystem id register, enable the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value can be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. bit description 31:8 base address ? r/w. this field provides the i/o offset to use for decoding the pcm in, pcm out, and microphone 1 dma engines. 7:3 reserved. read as 0s. 2:1 type ? ro. hardwired to 00b to indicate the base address exists in 32-bit address space 0 resource type indicator (rte) ? ro. hardwired to 0 to indicate a request for memory space. bit description 15:0 subsystem vendor id ? r/wo. intel ? 82801eb ich5 / 82801er ich5r datasheet 541 ac ?97 audio controller registers (d31:f5) 15.1.15 sid?subsystem identification register (audio?d31:f5) address offset: 2e ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core the sid register, in combination with the subsystem vendor id register make it possible for the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value can be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. t 15.1.16 cap_ptr?capabilities pointer register (audio?d31:f5) address offset: 34h attribute: ro default value: 50h size: 8 bits lockable: no power well: core this register indicates the offset for the capability pointer. 15.1.17 int_ln?interrupt line register (audio?d31:f5) address offset: 3ch attribute: r/w default value: 00h size: 8 bits lockable: no power well: core this register indicates which pci interrupt line is used for the ac?97 module interrupt. bit description 15:0 subsystem id ? r/wo. bit description 7:0 capabilities pointer (cap_ptr) ? ro. this field indicates that the first capability pointer offset is offset 50h bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich5. it is used to communicate to software the interrupt line that the interrupt pin is connected to. 542 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.1.18 int_pn?interrupt pin register (audio?d31:f5) address offset: 3dh attribute: ro default value: 02h size: 8 bits lockable: no power well: core this register indicates which pci interrupt pin is used for the ac '97 module interrupt. the ac '97 interrupt is internally or?d to the interrupt controller with the pirqb# signal. 15.1.19 pcid?programmable codec identification register (audio?d31:f5) address offset: 40h attribute: r/w default value: 09h size: 8 bits lockable: no power well: core this register is used to specify the id for the secondary and tertiary codecs for i/o accesses. this register is not affected by the d3 hot to d0 transition. the value in this register must be modified only before any ac ?97 codec accesses. bit description 7:3 reserved. 2:0 ac '97 interrupt routing ? ro. hardwired to 010b to select pirqb#. bit description 7:4 reserved. 3:2 tertiary codec id (tid ) ? r/w. these bits define the encoded id that is used to address the tertiary codec i/o space. bit 1 is the first bit sent and bit 0 is the second bit sent on ac_sdout during slot 0. 1:0 secondary codec id (scid) ? r/w. these two bits define the encoded id that is used to address the secondary codec i/o space. the two bits are the id that will be placed on slot 0, bits 0 and 1, upon an i/o access to the secondary codec. bit 1 is the first bit sent and bit 0 is the second bit sent on ac_sdout during slot 0. intel ? 82801eb ich5 / 82801er ich5r datasheet 543 ac ?97 audio controller registers (d31:f5) 15.1.20 cfg?configuration register (audio?d31:f5) address offset: 41h attribute: r/w default value: 00h size: 8 bits lockable: no power well: core this register is used to specify the id for the secondary and tertiary codecs for i/o accesses. this register is not affected by the d3 hot to d0 transition. 15.1.21 pid?pci power management capability identification register (audio?d31:f5) address offset: 50 ? 51h attribute: ro default value: 0001h size: 16 bits lockable: no power well: core bit description 7:1 reserved?ro. 0 i/o space enable (iose) ? r/w. 0 = disable. the ios bit at offset 04h and the i/o space bars at offset 10h and 14h become read only registers. additionally, bit 0 of the i/o bars at offsets 10h and 14h are hardwired to 0 when this bit is 0. this is the default state for the i/o bars. bios must explicitly set this bit to allow a legacy driver to work. 1 = enable bit description 15:8 next capability (next) ? ro. this field indicates that the next item in the list is at offset 00h. 7:0 capability id (cap) ? ro.this field indicates that this pointer is a message signaled interrupt capability. 544 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.1.22 pc?power management capabilities register (audio?d31:f5) address offset: 52 ? 53h attribute: ro default value: c9c2h size: 16 bits lockable: no power well: core this register is not affected by the d3 hot to d0 transition. bit description 15:11 pme support ? ro. this field indicates pme# can be generated from all d states. 10:9 reserved. 8:6 auxiliary current ? ro. this field reports 375 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi)?ro. this field indicates that no device-specific initialization is required. 4 reserved ? ro. 3 pme clock (pmec) ? ro. this field indicates that pci clock is not required to generate pme#. 2:0 version (ver) ? ro. this field indicates support for the pci power management specification, revision 1.1 intel ? 82801eb ich5 / 82801er ich5r datasheet 545 ac ?97 audio controller registers (d31:f5) 15.1.23 pcs?power management control and status register (audio?d31:f5) address offset: 54 ? 55h attribute: r/w, r/wc default value: 0000h size: 16 bits lockable: no power well: resume bit description 15 pme status (pmes) ? r/wc. this bit resides in the resume well. software clears this bit by writing a 1 to it. 0 = pme# signal not asserted by ac ?97 controller. 1 = this bit is set when the ac ?97 controller would normally assert the pme# signal independent of the state of the pme_en bit. 14:9 reserved ? ro. 8 power management event enable (pmee) ? r/w. 0 = disable 1 = enable. when set, and if corresponding pmes is also set, the ac '97 controller sets the ac97_sts bit in the gpe0_sts register 7:2 reserved?ro. 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the ac?97 controller and to set a new power state. the values are: 00 = d0 state 01 = not supported 10 = not supported 11 = d3 hot state when in the d3 hot state, the ac ?97 controller?s configuration space is available, but the i/o and memory spaces are not. additionally, interrupts are blocked. if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. 546 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.2 ac ?97 audio i/o space (d31:f5) the ac ?97 i/o space includes native audio bus master registers and native mixer registers. for the ich5, the offsets are important as they will determine bits 1:0 of the tag field (codec id). audio mixer i/o space can be accessed as a 16-bit field only since the data packet length on ac-link is a word. any s/w access to the codec will be done as a 16-bit access starting from the first active byte. in case no byte enables are active, the access will be done at the first word of the qword that contains the address of this request. table 169. intel ? ich5 audio mixer register configuration (sheet 1 of 2) primary offset (codec id =00) secondary offset (codec id =01) tertiary offset (codec id =10 nambar exposed registers (d31:f5) 00h 80h 100h reset 02h 82h 102h master volume 04h 84h 104h aux out volume 06h 86h 106h mono volume 08h 88h 108h master tone (r & l) 0ah 8ah 10ah pc_beep volume 0ch 8ch 10ch phone volume 0eh 8eh 10eh mic volume 10h 90h 110h line in volume 12h 92h 112h cd volume 14h 94h 114h video volume 16h 96h 116h aux in volume 18h 98h 118h pcm out volume 1ah 9ah 11ah record select 1ch 9ch 11ch record gain 1eh 9eh 11eh record gain mic 20h a0h 120h general purpose 22h a2h 122h 3d control 24h a4h 124h ac?97 reserved 26h a6h 126h powerdown ctrl/stat 28h a8h 128h extended audio 2ah aah 12ah extended audio ctrl/stat 2ch ach 12ch pcm front dac rate 2eh aeh 12eh pcm surround dac rate 30h b0h 130h pcm lfe dac rate 32h b2h 132h pcm lr adc rate 34h b4h 134h mic adc rate 36h b6h 136h 6ch vol: c, lfe 38h b8h 138h 6ch vol: l, r surround 3ah bah 13ah s/pdif control 3c?56h bc?d6h 13c?156h intel reserved 58h d8h 158h ac?97 reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 547 ac ?97 audio controller registers (d31:f5) note: 1. software should not try to access reserved registers 2. primary codec id cannot be changed. secondary codec id can be changed via bits 1:0 of configuration register 40h. tertiary codec id can be changed via bits 3:2 of configuration register 40h. 3. the tertiary offset is only available through the memory space defined by the mmbar register. the bus master registers are located from offset + 00h to offset + 51h and reside in the ac ?97 controller. accesses to these registers do not cause the cycle to be forwarded over the ac-link to the codec. s/w could access these registers as bytes, word, dword or qword quantities, but reads must not cross dword boundaries. in the case of the split codec implementation accesses to the different codecs are differentiated by the controller by using address offsets 00h ? 7fh for the primary codec, address offsets 80h ? ffh for the secondary codec and address offsets 100h ? 17fh for the tertiary codec. the global control (glob_cnt) and global status (glob_sta) registers are aliased to the same global registers in the audio and modem i/o space. therefore a read/write to these registers in either audio or modem i/o space affects the same physical register. bus mastering registers exist in i/o space and reside in the ac ?97 controller. the six channels, pcm in, pcm in 2, pcm out, mic in, mic 2, and s/pdif out, each have their own set of bus mastering registers. the following register descriptions apply to all six channels. the register definition section titles use a generic ?x_? in front of the register to indicate that the register applies to all six channels. the naming prefix convention used in table 170 and in the register description i/o address is as follows: pi = pcm in channel po = pcm out channel mc = mic in channel mc2 = mic 2 channel pi2 = pcm in 2 channel sp = s/pdif out channel. 5ah dah 15ah vendor reserved 7ch fch 17ch vendor id1 7eh feh 17eh vendor id2 table 169. intel ? ich5 audio mixer register configuration (sheet 2 of 2) primary offset (codec id =00) secondary offset (codec id =01) tertiary offset (codec id =10 nambar exposed registers (d31:f5) 548 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) table 170. native audio bus master control registers (sheet 1 of 2) offset mnemonic name default access 00h pi_bdbar pcm in buffer descriptor list base address 00000000h r/w 04h pi_civ pcm in current index value 00h ro 05h pi_lvi pcm in last valid index 00h r/w 06h pi_sr pcm in status 0001h r/wc, ro 08h pi_picb pcm in position in current buffer 0000h ro 0ah pi_piv pcm in prefetched index value 00h ro 0bh pi_cr pcm in control 00h r/w, r/w (special) 10h po_bdbar pcm out buffer descriptor list base address 00000000h r/w 14h po_civ pcm out current index value 00h ro 15h po_lvi pcm out last valid index 00h r/w 16h po_sr pcm out status 0001h r/wc, ro 18h po_picb pcm in position in current buffer 0000h ro 1ah po_piv pcm out prefetched index value 00h ro 1bh po_cr pcm out control 00h r/w, r/w (special) 20h mc_bdbar mic. in buffer descriptor list base address 00000000h r/w 24h mc_civ mic. in current index value 00h ro 25h mc_lvi mic. in last valid index 00h r/w 26h mc_sr mic. in status 0001h r/wc, ro 28h mc_picb mic. in position in current buffer 0000h ro 2ah mc_piv mic. in prefetched index value 00h ro 2bh mc_cr mic. in control 00h r/w, r/w (special) 2ch glob_cnt global control 00000000h r/w, r/w (special) 30h glob_sta global status 00700000h r/w, r/wc, ro 34h cas codec access semaphore 00h r/w (special) 40h mc2_bdbar mic. 2 buffer descriptor list base address 00000000h r/w 44h mc2_civ mic. 2 current index value 00h ro 45h mc2_lvi mic. 2 last valid index 00h r/w 46h mc2_sr mic. 2 status 0001h ro, rwc 48h mc2_picb mic 2 position in current buffer 0000h ro 4ah mc2_piv mic. 2 prefetched index value 00h r/w 4bh mc2_cr mic. 2 control 00h r/w, r/w (special) 50h pi2_bdbar pcm in 2 buffer descriptor list base address 00000000h r/w 54h pi2_civ pcm in 2 current index value 00h ro 55h pi2_lvi pcm in 2 last valid index 00h r/w 56h pi2_sr pcm in 2 status 0001h r/wc, ro 58h pi2_picb pcm in 2 position in current buffer 0000h ro 5ah pi2_piv pcm in 2 prefetched index value 00h ro 5bh pi2_cr pcm in 2 control 00h r/w, r/w (special) 60h sp_bar s/pdif buffer descriptor list base address 00000000h r/w intel ? 82801eb ich5 / 82801er ich5r datasheet 549 ac ?97 audio controller registers (d31:f5) note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the registers shared with the ac ?97 modem (gcr, gsr, casr). all resume well registers will not be reset by the d3 hot to d0 transition. core well registers and bits not reset by the d3 hot to d0 transition: ? offset 2ch ? 2fh ? bits 6:0 global control (glob_cnt) ? offset 30h ? 33h ? bits [29,15,11:10,0] global status (glob_sta) ? offset 34h ? codec access semaphore register (cas) resume well registers and bits will not be reset by the d3 hot to d0 transition: ? offset 30h ? 33h ? bits [17:16] global status (glob_sta) 15.2.1 x _bdbar?buffer descriptor base address register (audio?d31:f5) i/o address: nabmbar + 00h (pibdbar), attribute: r/w nabmbar + 10h (pobdbar), nabmbar + 20h (mcbdbar) mbbar + 40h (mc2bdbar) mbbar + 50h (pi2bdbar) mbbar + 60h (spbar) default value: 00000000h size: 32 bits lockable: no power well: core software can read the register at offset 00h by performing a single 32-bit read from address offset 00h. reads across dword boundaries are not supported. 64h sp_civ s/pdif current index value 00h ro 65h sp_lvi s/pdif last valid index 00h r/w 66h sp_sr s/pdif status 0001h r/wc, ro 68h sp_picb s/pdif position in current buffer 0000h ro 6ah sp_piv s/pdif prefetched index value 00h ro 6bh sp_cr s/pdif control 00h r/w, r/w (special) 80h sdm sdata_in map 00h r/w, ro table 170. native audio bus master control registers (sheet 2 of 2) offset mnemonic name default access bit description 31:3 buffer descriptor base address[31:3] ? r/w. these bits represent address bits 31:3. the data should be aligned on 8-byte boundaries. each buffer descriptor is 8 bytes long and the list can contain a maximum of 32 entries. 2:0 hardwired to 0. 550 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.2.2 x _civ?current index value register (audio?d31:f5) i/o address: nabmbar + 04h (piciv), attribute: ro nabmbar + 14h (pociv), nabmbar + 24h (mcciv) mbbar + 44h (mc2civ) mbbar + 54h (pi2civ) mbbar + 64h (spciv) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 8-bit read to offset 04h. note: reads across dword boundaries are not supported. 15.2.3 x _lvi?last valid index register (audio?d31:f5) i/o address: nabmbar + 05h (pilvi), attribute: r/w nabmbar + 15h (polvi), nabmbar + 25h (mclvi) mbbar + 45h (mc2lvi) mbbar + 55h (pi2lvi) mbbar + 65h (splvi) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 8-bit read to offset 05h. note: reads across dword boundaries are not supported. bit description 7:5 hardwired to 0 4:0 current index value [4:0] ? ro. these bits represent which buffer descriptor within the list of 32 descriptors is currently being processed. as each descriptor is processed, this value is incremented. the value rolls over after it reaches 31. bit description 7:5 hardwired to 0. 4:0 last valid index [4:0] ? r/w. this value represents the last valid descriptor in the list. this value is updated by the software each time it prepares a new buffer and adds it to the list. intel ? 82801eb ich5 / 82801er ich5r datasheet 551 ac ?97 audio controller registers (d31:f5) 15.2.4 x _sr?status register (audio?d31:f5) i/o address: nabmbar + 06h (pisr), attribute: r/wc, ro nabmbar + 16h (posr), nabmbar + 26h (mcsr) mbbar + 46h (mc2sr) mbbar + 56h (pi2sr) mbbar + 66h (spsr) default value: 0001h size: 16 bits lockable: no power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 16-bit read to offset 06h. reads across dword boundaries are not supported. bit description 15:5 reserved. 4 fifo error (fifoe) ? r/wc. software clears this bit by writing a 1 to it. 0 = no fifo error. 1 = fifo error occurs. pisr register: fifo error indicates a fifo overrun. the fifo pointers don't increment, the incoming data is not written into the fifo, thus is lost. posr register: fifo error indicates a fifo underrun. the sample transmitted in this case should be the last valid sample. the intel ? ich5 will set the fifoe bit if the under-run or overrun occurs when there are more valid buffers to process. 3 buffer completion interrupt status (bcis) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by the hardware after the last sample of a buffer has been processed, and if the interrupt on completion (ioc) bit is set in the command byte of the buffer descriptor. it remains active until cleared by software. 2 last valid buffer completion interrupt (lvbci) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = last valid buffer has been processed. it remains active until cleared by software. this bit indicates the occurrence of the event signified by the last valid buffer being processed. thus this is an event status bit that can be cleared by software once this event has been recognized. this event will cause an interrupt if the enable bit in the control register is set. the interrupt is cleared when the software clears this bit. in the case of transmits (pcm out, modem out) this bit is set, after the last valid buffer has been fetched (not after transmitting it). while in the case of receives , this bit is set after the data for the last buffer has been written to memory. 1 current equals last valid (celv) ? ro. 0 = cleared by hardware when controller exists state (i.e., until a new value is written to the lvi register.) 1 = current index is equal to the value in the last valid index register, and the buffer pointed to by the civ has been processed (i.e., after the last valid buffer has been processed). this bit is very similar to bit 2, except this bit reflects the state rather than the event. this bit reflects the state of the controller, and remains set until the controller exits this state. 0 dma controller halted (dch) ? ro. 0 = running. 1 = halted. this could happen because of the start/stop bit being cleared and the dma engines are idle, or it could happen once the controller has processed the last valid buffer. 552 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.2.5 x _picb?position in current buffer register (audio?d31:f5) i/o address: nabmbar + 08h (pipicb), attribute: ro nabmbar + 18h (popicb), nabmbar + 28h (mcpicb) mbbar + 48h (mc2picb) mbbar + 58h (pi2picb) mbbar + 68h (sppicb) default value: 0000h size: 16 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. software can also read this register individually by doing a single, 16-bit read to offset 08h. reads across dword boundaries are not supported. 15.2.6 x _piv?prefetched index value register (audio?d31:f5) i/o address: nabmbar + 0ah (pipiv), attribute: ro nabmbar + 1ah (popiv), nabmbar + 2ah (mcpiv) mbbar + 4ah (mc2piv) mbbar + 5ah (pi2piv) mbbar + 6ah (sppiv) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. software can also read this register individually by doing a single, 8-bit read to offset 0ah. reads across dword boundaries are not supported. bit description 15:0 position in current buffer [15:0] ? ro. these bits represent the number of samples left to be processed in the current buffer. once again, this means, the number of samples not yet read from memory (in the case of reads from memory) or not yet written to memory (in the case of writes to memory), irrespective of the number of samples that have been transmitted/received across ac-link. bit description 7:5 hardwired to 0. 4:0 prefetched index value [4:0] ? ro. these bits represent which buffer descriptor in the list has been prefetched. the bits in this register are also modulo 32 and roll over after they reach 31. intel ? 82801eb ich5 / 82801er ich5r datasheet 553 ac ?97 audio controller registers (d31:f5) 15.2.7 x _cr?control register (audio?d31:f5) i/o address: nabmbar + 0bh (picr), attribute: r/w, r/w (special) nabmbar + 1bh (pocr), nabmbar + 2bh (mccr) mbbar + 4bh (mc2cr) mbbar + 5bh (pi2cr) mbbar + 6bh (spcr) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. software can also read this register individually by doing a single, 8-bit read to offset 0bh. reads across dword boundaries are not supported. bit description 7:5 reserved. 4 interrupt on completion enable (ioce) ? r/w. this bit controls whether or not an interrupt occurs when a buffer completes with the ioc bit set in its descriptor. 0 = disable. interrupt will not occur. 1 = enable 3 fifo error interrupt enable (feie) ? r/w. this bit controls whether the occurrence of a fifo error will cause an interrupt or not. 0 = disable. bit 4 in the status register will be set, but the interrupt will not occur. 1 = enable. interrupt will occur. 2 last valid buffer interrupt enable (lvbie) ? r/w. this bit controls whether the completion of the last valid buffer will cause an interrupt or not. 0 = disable. bit 2 in the status register will still be set, but the interrupt will not occur. 1 = enable 1 reset registers (rr) ? r/w (special). 0 = removes reset condition. 1 = contents of all bus master related registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register). software needs to set this bit but need not clear it since the bit is self clearing. this bit must be set only when the run/pause bit is cleared. setting it when the run bit is set will cause undefined consequences. 0 run/pause bus master (rpbm) ? r/w. 0 = pause bus master operation. this results in all state information being retained (i.e., master mode operation can be stopped and then resumed). 1 = run. bus master operation starts. 554 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.2.8 glob_cnt?global control register (audio?d31:f5) i/o address: nabmbar + 2ch attribute: r/w, r/w (special) default value: 00000000h size: 32 bits lockable: no power well: core bit description 31:30 s/pdif slot map (ssm) ? r/w. if the run/pause bus master bit (bit 0 of offset 2bh) is set, then the value in these bits indicate which slots s/pdif data is transmitted on. software must ensure that the programming here does not conflict with the pcm channels being used. if there is a conflict, unpredictable behavior will result ? the hardware will not check for a conflict. 00 = reserved 01 = slots 7 and 8 10 = slots 6 and 9 11 = slots 10 and 11 29:24 reserved. 23:22 pcm out mode (pom) ? r/w. enables the pcm out channel to use 16 or 20-bit audio on pcm out. this does not affect the microphone of s/pdif dma. when greater than 16 bit audio is used, the data structures are aligned as 32-bits per sample, with the highest order bits representing the data, and the lower order bits as don?t care. 00 = 16 bit audio (default) 01 = 20 bit audio 10 = reserved. if set, indeterminate behavior will result. 11 = reserved. if set, indeterminate behavior will result. 21:20 pcm 4/6 enable ? r/w. this field configures pcm output for 2, 4 or 6 channel mode. 00 = 2-channel mode (default) 01 = 4-channel mode 10 = 6-channel mode 11 = reserved 19:7 reserved. 6 ac_sdin2 interrupt enable ? r/w. 0 = disable 1 = enable an interrupt to occur when the codec on the ac_sdin2 causes a resume event on the ac-link. 5 ac_sdin1 interrupt enable ? r/w. 0 = disable 1 = enable an interrupt to occur when the codec on the ac_sdin1 causes a resume event on the ac-link. 4 ac_sdin0 interrupt enable ? r/w. 0 = disable 1 = enable an interrupt to occur when the codec on ac_sdin0 causes a resume event on the ac- link. 3 aclink shut off (lso) ? r/w. 0 = normal operation. 1 = controller disables all outputs which will be pulled low by internal pull down resistors. intel ? 82801eb ich5 / 82801er ich5r datasheet 555 ac ?97 audio controller registers (d31:f5) note: reads across dword boundaries are not supported. 2 ac ?97 warm reset ? r/w (special). 0 = normal operation. 1 = writing a 1 to this bit causes a warm reset to occur on the ac-link. the warm reset will awaken a suspended codec without clearing its internal registers. if software attempts to perform a warm reset while ac_bit_clk is running, the write will be ignored and the bit will not change. this bit is self-clearing (it remains set until the reset completes and ac_bit_clk is seen on the ac-link, after which it clears itself). 1 ac ?97 cold reset# ? r/w. 0 = writing a 0 to this bit causes a cold reset to occur throughout the ac ?97 circuitry. all data in the controller and the codec will be lost. software needs to clear this bit no sooner than the minimum number of ms have elapsed. 1 = this bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1. the value of this bit is retained after suspends; hence, if this bit is set to a 1 prior to suspending, a cold reset is not generated automatically upon resuming. note: this bit is in the core well. 0 gpi interrupt enable (gie) ? r/w. this bit controls whether the change in status of any gpi causes an interrupt. 0 = bit 0 of the global status register is set, but no interrupt is generated. 1 = the change on value of a gpi causes an interrupt and sets bit 0 of the global status register. bit description 556 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.2.9 glob_sta?global status register (audio?d31:f5) i/o address: nabmbar + 30h attribute: ro, r/w, r/wc default value: 00700000h size: 32 bits lockable: no power well: core bit description 31:30 reserved. 29 ac_sdin2 resume interrupt (s2ri) ? r/wc. this bit indicates a resume event occurred on ac_sdin2. software clears this bit by writing a 1 to it. 0 = resume event did not occur. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 28 ac_sdin2 codec ready (s2cr) ? ro. reflects the state of the codec ready bit on ac_sdin2. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 27 bit clock stopped (bcs) ? ro. this bit indicates that the bit clock is not running. 0 = transition is found on ac_bit_clk. 1 = intel ? ich5 detected that there has been no transition on ac_bit_clk for four consecutive pci clocks. 26 s/pdif interrupt (spint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = s/pdif out channel interrupt status bits have been set. 25 pcm in 2 interrupt (p2int) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm in 2 channel status bits have been set. 24 microphone 2 in interrupt (m2int) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the mic in channel interrupts status bits has been set. 23:22 sample capabilities ? ro. this field indicates the capability to support more greater than 16-bit audio. 00 = reserved 01 = 16 and 20-bit audio supported 10 = reserved 11 = reserved 21:20 multichannel capabilities ? ro. this field indicates the capability to support more 4 and 6 channels on pcm out. 19:18 reserved. 17 md3 ? r/w. power down semaphore for modem. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the ad3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. 16 ad3 ? r/w. power down semaphore for audio. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the md3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. intel ? 82801eb ich5 / 82801er ich5r datasheet 557 ac ?97 audio controller registers (d31:f5) note: reads across dword boundaries are not supported. 15 read completion status (rcs) ? r/wc. this bit indicates the status of codec read completions. 0 = a codec read completes normally. 1 = a codec read results in a time-out. the bit remains set until being cleared by software writing a 1 to the bit location. this bit is not affected by d3 hot to d0 reset. 14 bit 3 of slot 12 ? ro. display bit 3 of the most recent slot 12. 13 bit 2 of slot 12 ? ro. display bit 2 of the most recent slot 12. 12 bit 1 of slot 12 ? ro. display bit 1 of the most recent slot 12. 11 ac_sdin1 resume interrupt (s1r1) ? r/wc. this bit indicates that a resume event occurred on ac_sdin1. software clears this bit by writing a 1 to it. 0 = resume event did not occur 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 10 ac_sdin0 resume interrupt (s0r1) ? r/wc. this bit indicates that a resume event occurred on ac_sdin0. software clears this bit by writing a 1 to it. 0 = resume event did not occur 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 9 ac_sdin1 codec ready (s1cr) ? ro. reflects the state of the codec ready bit in ac_sdin1. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 8 ac_sdin0 codec ready (s0cr) ? ro. reflects the state of the codec ready bit in ac_sdin 0. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 7 microphone in interrupt (mint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the mic in channel interrupts status bits has been set. 6 pcm out interrupt (point) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm out channel interrupts status bits has been set. 5 pcm in interrupt (piint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm in channel interrupts status bits has been set. 4:3 reserved 2 modem out interrupt (moint ) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the modem out channel interrupts status bits has been set. 1 modem in interrupt (miint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the modem in channel interrupts status bits has been set. 0 gpi status change interrupt (gsci) ? rwc. 0 = software clears this bit by writing a 1 to it. 1 = this bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set. this indicates that one of the gpis changed state, and that the new values are available in slot 12. this bit is not affected by d3 hot to d0 reset. bit description 558 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 audio controller registers (d31:f5) 15.2.10 cas?codec access semaphore register (audio?d31:f5) i/o address: nabmbar + 34h attribute: r/w (special) default value: 00h size: 8 bits lockable: no power well: core note: reads across dword boundaries are not supported. 15.2.11 sdm?sdata_in map register (audio?d31:f5) i/o address: nabmbar + 80h attribute: r/w, ro default value: 00h size: 8 bits lockable: no power well: core note: reads across dword boundaries are not supported. bit description 7:1 reserved. 0 codec access semaphore (cas) ? r/w (special). this bit is read by software to check whether a codec access is currently in progress. 0 = no access in progress. 1 = the act of reading this register sets this bit to 1. the driver that read this bit can then perform an i/o access. once the access is completed, hardware automatically clears this bit. bit description 7:6 pcm in 2, microphone in 2 data in line (di2l) ? r/w. when the se bit is set, these bits indicates which ac_sdin line should be used by the hardware for decoding the input slots for pcm in 2 and microphone in 2. when the se bit is cleared, the value of these bits are irrelevant, and pcm in 2 and mic in 2 dma engines are not available. 00 = ac_sdin0 01 = ac_sdin1 10 = ac_sdin2 11 = reserved 5:4 pcm in 1, microphone in 1 data in line (di1l) ? r/w. when the se bit is set, these bits indicates which ac_sdin line should be used by the hardware for decoding the input slots for pcm in 1 and microphone in 1. when the se bit is cleared, the value of these bits are irrelevant, and the pcm in 1 and mic in 1 engines use the or?d ac_sdin lines. 00 = ac_sdin0 01 = ac_sdin1 10 = ac_sdin2 11 = reserved 3 steer enable (se) ? r/w. when set, the ac_sdin lines are treated separately and not or?d together before being sent to the dma engines. when cleared, the ac_sdin lines are or?d together, and the ?microphone in 2? and ?pcm in 2? dma engines are not available. 2 reserved ? ro. 1:0 last codec read data input (ldi) ? ro. when a codec register is read, this indicates which ac_sdin the read data returned on. software can use this to determine how the codecs are mapped. the values are: 00 = ac_sdin0 01 = ac_sdin1 10 = ac_sdin2 11 = reserved intel ? 82801eb ich5 / 82801er ich5r datasheet 559 ac ?97 modem controller registers (d31:f6) ac ?97 modem controller registers (d31:f6) 16 16.1 ac ?97 modem pci configuration space (d31:f6) note: address locations that are not shown in table 171 should be treated as reserved (see section 6.2 for details). note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the following bios programmed registers as bios may not be invoked following the d3-to-d0 transition. all resume well registers will not be reset by the d3 hot to d0 transition. core well registers not reset by the d3 hot to d0 transition: ? offset 2ch ? 2dh ? subsystem vendor id (svid) ? offset 2eh ? 2fh ? subsystem id (sid) resume well registers will not be reset by the d3 hot to d0 transition: ? offset 54h ? 55h ? power management control and status (pcs) table 171. ac ?97 modem pci register address map (modem?d31:f6) offset mnemonic register default access 00?01h vid vendor identification 8086 ro 02?03h did device identification 24d6 ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h pcists pci status 0290h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 03h ro 0bh bcc base class code 07h ro 0eh headtyp header type 00h ro 10?13h mmbar modem mixer base address 00000001h r/w, ro 14?17h mbar modem base address 00000001h r/w, ro 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 34h cap_ptr capabilities pointer 50h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin 02h ro 50?51h pid pci power management capability id 0001h ro 52?53h pc power management capabilities c9c2h ro 54?55h pcs power management control and status 0000h r/w, r/wc 560 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 modem controller registers (d31:f6) 16.1.1 vid?vendor identification register (modem?d31:f6) address offset: 00 ? 01h attribute: ro default value: 8086 size: 16 bits lockable: no power well: core 16.1.2 did?device identification register (modem?d31:f6) address offset: 02 ? 03h attribute: ro default value: 24d6h size: 16 bits lockable: no power well: core bit description 15:0 vendor id. bit description 15:0 device id. intel ? 82801eb ich5 / 82801er ich5r datasheet 561 ac ?97 modem controller registers (d31:f6) 16.1.3 pcicmd?pci command register (modem?d31:f6) address offset: 04 ? 05h attribute: r/w, ro default value: 0000h size: 16 bits lockable: no power well: core pcicmd is a 16-bit control register. refer to the pci local bus specification, revision 2.3 for complete details on each bit. bit description 15:11 reserved. read 0. 10 interrupt disable (id) ? r/w. 0 = the intx# signals may be asserted and msis may be generated. 1 = the ac ?97 controller?s intx# signal will be de-asserted and it may not generate msis. 9 fast back to back enable (fbe) ? ro. not implemented. hardwired to 0. 8 serr# enable (serr_en) ? ro. not implemented. hardwired to 0. 7 wait cycle control (wcc) ? ro. not implemented. hardwired to 0. 6 parity error response (per) ? ro. not implemented. hardwired to 0. 5 vga palette snoop (vps) ? ro. not implemented. hardwired to 0. 4 memory write and invalidate enable (mwie) ? ro. not implemented. hardwired to 0. 3 special cycle enable (sce) ? ro. not implemented. hardwired to 0. 2 bus master enable (bme) ? r/w. this bit controls standard pci bus mastering capabilities. 0 = disable 1 = enable 1 memory space enable (mse) ? ro. hardwired to 0, ac ?97 does not respond to memory accesses. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disable access. (default = 0). 1 = enable access to i/o space. the native pci mode base address register should be programmed prior to setting this bit. 562 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 modem controller registers (d31:f6) 16.1.4 pcists?pci status register (modem?d31:f6) address offset: 06 ? 07h attribute: r/wc, ro default value: 0290h size: 16 bits lockable: no power well: core pcista is a 16-bit status register. refer to the pci local bus specification, revision 2.3 for complete details on each bit. note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 16.1.5 rid?revision identification register (modem?d31:f6) address offset: 08h attribute: ro default value: see bit description size: 8 bits lockable: no power well: core bit description 15 detected parity error (dpe) ? ro. not implemented. hardwired to 0. 14 signaled system error (sse) ?ro. not implemented. hardwired to 0. 13 master abort status (mas) ? r/wc. 0 = master abort not generated by bus master ac ?97 function. 1 = bus master ac ?97 interface function, as a master, generates a master abort. 12 reserved. read as 0. 11 signaled target abort (sta) ? ro. not implemented. hardwired to 0. 10:9 devsel# timing status (dev_sts) ? ro. this 2-bit field reflects the intel ? ich5's devsel# timing parameter. these read only bits indicate the ich5's devsel# timing when performing a positive decode. 8 data parity error detected (dped) ? ro. not implemented. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. this bit indicates that the ich5 as a target is capable of fast back-to-back transactions. 6 user definable features (udf) ? ro. not implemented. hardwired to 0. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. indicates that the controller contains a capabilities pointer list. the first item is pointed to by looking at configuration offset 34h. 3 interrupt status (ints) ? ro. 0 = this bit is 0 after the interrupt is cleared. 1 = this bit is 1 when the intx# is asserted. 2:0 reserved bit description 7:0 revision id ? ro. refer to the latest intel ? ich5 / ich5r specification update for the value of the revision identification register. intel ? 82801eb ich5 / 82801er ich5r datasheet 563 ac ?97 modem controller registers (d31:f6) 16.1.6 pi?programming interface register (modem?d31:f6) address offset: 09h attribute: ro default value: 00h size: 8 bits lockable: no power well: core 16.1.7 scc?sub class code register (modem?d31:f6) address offset: 0ah attribute: ro default value: 03h size: 8 bits lockable: no power well: core 16.1.8 bcc?base class code register (modem?d31:f6) address offset: 0bh attribute: ro default value: 07h size: 8 bits lockable: no power well: core 16.1.9 headtyp?header type register (modem?d31:f6) address offset: 0eh attribute: ro default value: 00h size: 8 bits lockable: no power well: core bit description 7:0 programming interface ? ro. bit description 7:0 sub class code ? ro. 03h = generic modem. bit description 7:0 base class code ? ro. 07h = simple communications controller. bit description 7:0 header type ? ro. 564 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 modem controller registers (d31:f6) 16.1.10 mmbar?modem mixer base address register (modem?d31:f6) address offset: 10 ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits the native pci mode modem uses pci base address register #1 to request a contiguous block of i/o space that is to be used for the modem mixer software interface. the mixer requires 256 bytes of i/o space. all accesses to the mixer registers are forwarded over the ac-link to the codec where the registers reside. in the case of the split codec implementation accesses to the different codecs are differentiated by the controller by using address offsets 00h ? 7fh for the primary codec and address offsets 80h ? feh for the secondary codec. 16.1.11 mbar?modem base address register (modem?d31:f6) address offset: 14 ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits the modem function uses pci base address register #1 to request a contiguous block of i/o space that is to be used for the modem software interface. the modem bus mastering register space requires 128 bytes of i/o space. all modem registers reside in the controller, therefore cycles are not forwarded over the ac-link to the codec. bit description 31:16 hardwired to 0s. 15:8 base address ? r/w. these bits are used in the i/o space decode of the modem interface registers. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for the ac ?97 modem, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. this configuration yields a maximum i/o block size of 256 bytes for this base address. 7:1 reserved. read as 0. 0 resource type indicator (rte) ? ro. hardwired to 1indicating a request for i/o space. bit description 31:16 hardwired to 0s. 15:7 base address ? r/w. these bits are used in the i/o space decode of the modem interface registers. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for the ac ?97 modem, the upper 16 bits are hardwired to 0, while bits 15:7 are programmable. this configuration yields a maximum i/o block size of 128 bytes for this base address. 6:1 reserved. read as 0. 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. intel ? 82801eb ich5 / 82801er ich5r datasheet 565 ac ?97 modem controller registers (d31:f6) 16.1.12 svid?subsystem vendor identification register (modem?d31:f6) address offset: 2c ? 2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core the svid register, in combination with the subsystem id register, enable the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value can be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. 16.1.13 sid?subsystem identification register (modem?d31:f6) address offset: 2e ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core the sid register, in combination with the subsystem vendor id register make it possible for the operating environment to distinguish one audio subsystem from another. this register is implemented as write-once register. once a value is written to it, the value can be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. 16.1.14 cap_ptr?capabilities pointer register (modem?d31:f6) address offset: 34h attribute: ro default value: 50h size: 8 bits lockable: no power well: core this register indicates the offset for the capability pointer. bit description 15:0 subsystem vendor id ? r/wo. bit description 15:0 subsystem id ? r/wo. bit description 7:0 capabilities pointer (cap_ptr) ? ro. this field indicates that the first capability pointer offset is offset 50h. 566 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 modem controller registers (d31:f6) 16.1.15 int_ln?interrupt line register (modem?d31:f6) address offset: 3ch attribute: r/w default value: 00h size: 8 bits lockable: no power well: core this register indicates which pci interrupt line is used for the ac ?97 module interrupt. 16.1.16 int_pin?interrupt pin register (modem?d31:f6) address offset: 3dh attribute: ro default value: 02h size: 8 bits lockable: no power well: core this register indicates which pci interrupt pin is used for the ac ?97 modem interrupt. the ac ?97 interrupt is internally or?d to the interrupt controller with the pirqb# signal. 16.1.17 pid?pci power management capability identification register (modem?d31:f6) address offset: 50h attribute: ro default value: 0001h size: 16 bits lockable: no power well: core bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich5. it is used to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:3 reserved 2:0 interrupt pin (int_pn) ? ro. hardwired to 010b to select pirqb#. bit description 15:8 next capability (next) ? ro. this field indicates that this is the last item in the list. 7:0 capability id (cap) ? ro. this field indicates that this pointer is a message signaled interrupt capability. intel ? 82801eb ich5 / 82801er ich5r datasheet 567 ac ?97 modem controller registers (d31:f6) 16.1.18 pc?power management capabilities register (modem?d31:f6) address offset: 52h attribute: ro default value: c9c2h size: 16 bits lockable: no power well: core 16.1.19 pcs?power management control and status register (modem?d31:f6) address offset: 54h attribute: r/w, r/wc default value: 0000h size: 16 bits lockable: no power well: resume this register is not affected by the d3 hot to d0 transition. bit description 15:11 pme support ? ro. this field indicates pme# can be generated from all d states. 10:9 reserved. 8:6 auxiliary current ? ro. this field reports 375 ma maximum suspend well current required when in the d3cold state. 5 device specific initialization (dsi) ? ro. this bit indicates that no device-specific initialization is required. 4 reserved ? ro. 3 pme clock (pmec) ? ro. this bit indicates that pci clock is not required to generate pme#. 2:0 version (vs) ? ro. this field indicates support for the pci power management specification, revision 1.1 . bit description 15 pme status (pmes) ? rw/c. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the ac ?97 controller would normally assert the pme# signal independent of the state of the pme_en bit. this bit resides in the resume well. 14:9 reserved ? ro. 8 pme enable (pmee) ? r/w. 0 = disable 1 = enable. when set, and if corresponding pmes is also set, the ac '97 controller sets the ac97_sts bit in the gpe0_sts register. 7:2 reserved ? ro. 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the ac ?97 controller and to set a new power state. the values are: 00 = d0 state 01 = not supported 10 = not supported 11 = d3 hot state when in the d3 hot state, the ac ?97 controller?s configuration space is available, but the i/o and memory spaces are not. additionally, interrupts are blocked. if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. 568 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 modem controller registers (d31:f6) 16.2 ac ?97 modem i/o space (d31:f6) in the case of the split codec implementation accesses to the modem mixer registers in different codecs are differentiated by the controller by using address offsets 00h ? 7fh for the primary codec and address offsets 80h ? feh for the secondary codec. table 172 shows the register addresses for the modem mixer registers. notes: 1. registers in italics are for functions not supported by the ich5 2. software should not try to access reserved registers. 3. the ich5 supports a modem codec connected to ac_sdin[2:0], as long as the codec id is 00 or 01. however, the ich5 does not support more than one modem codec. for a complete list of topologies, see your ich5 enabled platform design guide. the global control (glob_cnt) and global status (glob_sta) registers are aliased to the same global registers in the audio and modem i/o space. therefore a read/write to these registers in either audio or modem i/o space affects the same physical register. software could access these registers as bytes, word, dword quantities, but reads must not cross dword boundaries. table 172. intel ? ich5 modem mixer register configuration register mmbar exposed registers (d31:f6) primary secondary name 00h:38h 80h:b8h intel reserved 3ch bch extended modem id 3eh beh extended modem stat/ctrl 40h c0h line 1 dac/adc rate 42h c2h line 2 dac/adc rate 44h c4h handset dac/adc rate 46h c6h line 1 dac/adc level mute 48h c8h line 2 dac/adc level mute 4ah cah handset dac/adc level mute 4ch cch gpio pin config 4eh ceh gpio polarity/type 50h d0h gpio pin sticky 52h d2h gpio pin wake up 54h d4h gpio pin status 56h d6h misc. modem afe stat/ctrl 58h d8h ac ?97 reserved 5ah dah vendor reserved 7ch fch vendor id1 7eh feh vendor id2 intel ? 82801eb ich5 / 82801er ich5r datasheet 569 ac ?97 modem controller registers (d31:f6) these registers exist in i/o space and reside in the ac ?97 controller. the two channels, modem in and modem out, each have their own set of bus mastering registers. the following register descriptions apply to both channels. the naming prefix convention used is as follows: mi = modem in channel mo = modem out channel note: 1. mi = modem in channel; mo = modem out channel note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the registers shared with the ac ?97 audio controller (gcr, gsr, casr). all resume well registers will not be reset by the d3 hot to d0 transition. core well registers and bits not reset by the d3 hot to d0 transition: ? offset 3ch ? 3fh ? bits [6:0] global control (glob_cnt) ? offset 40h ? 43h ? bits [29,15,11:10] global status (glob_sta) ? offset 44h ? codec access semaphore register (cas) resume well registers and bits will not be reset by the d3 hot to d0 transition: ? offset 40h ? 43h ? bits [17:16] global status (glob_sta) table 173. modem registers offset mnemonic name default access 00h?03h mi_bdbar modem in buffer descriptor list base address 00000000h r/w 04h mi_civ modem in current index value 00h ro 05h mi_lvi modem in last valid index 00h r/w 06h?07h mi_sr modem in status 0001h r/wc, ro 08h?09h mi_picb modem in position in current buffer 0000h ro 0ah mi_piv modem in prefetch index value 00h ro 0bh mi_cr modem in control 00h r/w, r/w (special) 10h?13h mo_bdbar modem out buffer descriptor list base address 00000000h r/w 14h mo_civ modem out current index value 00h ro 15h mo_lvi modem out last valid 00h r/w 16h?17h mo_sr modem out status 0001h r/wc, ro 18h?19h mi_picb modem in position in current buffer 0000h ro 1ah mo_piv modem out prefetched index 00h ro 1bh mo_cr modem out control 00h r/w, r/w (special) 3ch?3fh glob_cnt global control 00000000h r/w, r/w (special) 40h?43h glob_sta global status 00300000h ro, r/w, r/wc 44h cas codec access semaphore 00h r/w (special) 570 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 modem controller registers (d31:f6) 16.2.1 x _bdbar?buffer descriptor list base address register (modem?d31:f6) i/o address: mbar + 00h (mibdbar), attribute: r/w mbar + 10h (mobdbar) default value: 00000000h size: 32bits lockable: no power well: core software can read the register at offset 00h by performing a single, 32-bit read from address offset 00h. reads across dword boundaries are not supported. 16.2.2 x _civ?current index value register (modem?d31:f6) i/o address: mbar + 04h (miciv), attribute: ro mbar + 14h (mociv), default value: 00h size: 8bits lockable: no power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 8-bit read to offset 04h. reads across dword boundaries are not supported. bit description 31:3 buffer descriptor list base address [31:3] ? r/w. these bits represent address bits 31:3. the entries should be aligned on 8-byte boundaries. 2:0 hardwired to 0. bit description 7:5 hardwired to 0. 4:0 current index value [4:0] ? ro. these bits represent which buffer descriptor within the list of 16 descriptors is being processed currently. as each descriptor is processed, this value is incremented. intel ? 82801eb ich5 / 82801er ich5r datasheet 571 ac ?97 modem controller registers (d31:f6) 16.2.3 x _lvi?last valid index register (modem?d31:f6) i/o address: mbar + 05h (milvi), attribute: r/w mbar + 15h (molvi) default value: 00h power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 8-bit read to offset 05h. reads across dword boundaries are not supported. bit description 7:5 hardwired to 0 4:0 last valid index [4:0] ? r/w. these bits indicate the last valid descriptor in the list. this value is updated by the software as it prepares new buffers and adds to the list. 572 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 modem controller registers (d31:f6) 16.2.4 x _sr?status register (modem?d31:f6) i/o address: mbar + 06h (misr), attribute: r/wc, ro mbar + 16h (mosr) default value: 0001h size: 16 bits lockable: no power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 16-bit read to offset 06h. reads across dword boundaries are not supported. bit description 15:5 reserved 4 fifo error (fifoe) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = fifo error occurs. modem in: fifo error indicates a fifo overrun. the fifo pointers don't increment, the incoming data is not written into the fifo, thereby being lost. modem out: fifo error indicates a fifo underrun. the sample transmitted in this case should be the last valid sample. the intel ? ich5 will set the fifoe bit if the under-run or overrun occurs when there are more valid buffers to process. 3 buffer completion interrupt status (bcis) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by the hardware after the last sample of a buffer has been processed, and if the interrupt on completion (ioc) bit is set in the command byte of the buffer descriptor. remains active until software clears bit. 2 last valid buffer completion interrupt (lvbci) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when last valid buffer has been processed. it remains active until cleared by software. this bit indicates the occurrence of the event signified by the last valid buffer being processed. thus, this is an event status bit that can be cleared by software once this event has been recognized. this event will cause an interrupt if the enable bit in the control register is set. the interrupt is cleared when the software clears this bit. in the case of transmits (pcm out, modem out) this bit is set, after the last valid buffer has been fetched (not after transmitting it). while in the case of receives, this bit is set after the data for the last buffer has been written to memory. 1 current equals last valid (celv) ? ro. 0 = hardware clears when controller exists state (i.e., until a new value is written to the lvi register). 1 = current index is equal to the value in the last valid index register, and the buffer pointed to by the civ has been processed (i.e., after the last valid buffer has been processed). this bit is very similar to bit 2, except, this bit reflects the state rather than the event. this bit reflects the state of the controller, and remains set until the controller exits this state. 0 dma controller halted (dch) ? ro. 0 = running. 1 = halted. this could happen because of the start/stop bit being cleared and the dma engines are idle, or it could happen once the controller has processed the last valid buffer. intel ? 82801eb ich5 / 82801er ich5r datasheet 573 ac ?97 modem controller registers (d31:f6) 16.2.5 x _picb?position in current buffer register (modem?d31:f6) i/o address: mbar + 08h (mipicb), attribute: ro mbar + 18h (mopicb), default value: 0000h size: 16 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. software can also read this register individually by doing a single, 16-bit read to offset 08h. reads across dword boundaries are not supported. 16.2.6 x _piv?prefetch index value register (modem?d31:f6) i/o address: mbar + 0ah (mipiv), attribute: ro mbar + 1ah (mopiv) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. software can also read this register individually by doing a single, 8-bit read to offset 0ah. reads across dword boundaries are not supported. bit description 15:0 position in current buffer[15:0] ? ro. these bits represent the number of samples left to be processed in the current buffer. bit description 7:5 hardwired to 0. 4:0 prefetched index value [4:0] ? ro. these bits represent which buffer descriptor in the list has been prefetched. 574 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 modem controller registers (d31:f6) 16.2.7 x _cr?control register (modem?d31:f6) i/o address: mbar + 0bh (micr), attribute: r/w, r/w (special) mbar + 1bh (mocr) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. software can also read this register individually by doing a single, 8-bit read to offset 0bh. reads across dword boundaries are not supported. bit description 7:5 reserved 4 interrupt on completion enable (ioce) ? r/w. this bit controls whether or not an interrupt occurs when a buffer completes with the ioc bit set in its descriptor. 0 = disable 1 = enable 3 fifo error interrupt enable (feie) ? r/w. this bit controls whether the occurrence of a fifo error will cause an interrupt or not. 0 = disable. bit 4 in the status register will be set, but the interrupt will not occur. 1 = enable. interrupt will occur 2 last valid buffer interrupt enable (lvbie) ? r/w. this bit controls whether the completion of the last valid buffer will cause an interrupt or not. 0 = disable. bit 2 in the status register will still be set, but the interrupt will not occur. 1 = enable 1 reset registers (rr) ? r/w (special). 0 = removes reset condition. 1 = contents of all registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register). software needs to set this bit. it must be set only when the run/pause bit is cleared. setting it when the run bit is set will cause undefined consequences. this bit is self-clearing (software needs not clear it). 0 run/pause bus master (rpbm) ? r/w. 0 = pause bus master operation. this results in all state information being retained (i.e., master mode operation can be stopped and then resumed). 1 = run. bus master operation starts. intel ? 82801eb ich5 / 82801er ich5r datasheet 575 ac ?97 modem controller registers (d31:f6) 16.2.8 glob_cnt?global control register (modem?d31:f6) i/o address: mbar + 3ch attribute: r/w, r/w (special) default value: 00000000h size: 32 bits lockable: no power well: core note: reads across dword boundaries are not supported. bit description 31:6 reserved. 6 ac_sdin2 interrupt enable (s2re) ? r/w. 0 = disable 1 = enable an interrupt to occur when the codec on the ac_sdin2 causes a resume event on the ac-link. 5 ac_sdin1 resume interrupt enable (s1re) ? r/w. 0 = disable 1 = enable an interrupt to occur when the codec on the ac_sdin1 causes a resume event on the ac-link. 4 ac_sdin0 resume interrupt enable (s0re) ? r/w. 0 = disable 1 = enable an interrupt to occur when the codec on ac_sdin0 causes a resume event on the ac- link. 3 aclink shut off (lso) ? r/w. 0 = normal operation. 1 = controller disables all outputs which will be pulled low by internal pull down resistors. 2 ac ?97 warm reset ? r/w (special). 0 = normal operation. 1 = writing a 1 to this bit causes a warm reset to occur on the ac-link. the warm reset will awaken a suspended codec without clearing its internal registers. if software attempts to perform a warm reset while ac_bit_clk is running, the write will be ignored and the bit will not change. this bit is self-clearing (it remains set until the reset completes and ac_bit_clk is seen on the ac-link, after which it clears itself). 1 ac ?97 cold reset# ? r/w. 0 = writing a 0 to this bit causes a cold reset to occur throughout the ac ?97 circuitry. all data in the controller and the codec will be lost. software needs to clear this bit no sooner than the minimum number of ms have elapsed. 1 = this bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1. the value of this bit is retained after suspends; hence, if this bit is set to a 1 prior to suspending, a cold reset is not generated automatically upon resuming. note: this bit is in the core well. 0 gpi interrupt enable (gie) ? r/w. this bit controls whether the change in status of any gpi causes an interrupt. 0 = bit 0 of the global status register is set, but no interrupt is generated. 1 = the change on value of a gpi causes an interrupt and sets bit 0 of the global status register. 576 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 modem controller registers (d31:f6) 16.2.9 glob_sta?global status register (modem?d31:f6) i/o address: mbar + 40h attribute: ro, r/w, r/wc default value: 00300000h size: 32 bits lockable: no power well: core bit description 31:30 reserved. 29 ac_sdin2 resume interrupt (s2ri) ? r/wc. this bit indicates a resume event occurred on ac_sdin2. 0 = software clears this bit by writing a 1 to it. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 28 ac_sdin2 codec ready (s2cr) ? ro. this bit reflects the state of the codec ready bit on ac_sdin2. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 27 bit clock stopped (bcs) ? ro. this bit indicates that the bit clock is not running. 0 = transition is found on ac_bit_clk. 1 = intel ? ich5 detects that there has been no transition on ac_bit_clk for four consecutive pci clocks. 26 s/pdif interrupt (spint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = s/pdif out channel interrupt status bits have been set. 25 pcm in 2 interrupt (p2int) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm in 2 channel status bits have been set. 24 microphone 2 in interrupt (m2int) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the mic in channel interrupts status bits has been set. 23:22 sample capabilities ? ro. this field indicates the capability to support more greater than 16-bit audio. 00 = reserved 01 = 16 and 20-bit audio supported (ich5 value) 10 = reserved 11 = reserved 21:20 multichannel capabilities ? ro. this field indicates the capability to support 4 and 6 channels on pcm out. 19:18 reserved. 17 md3 ? r/w. power down semaphore for modem. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the ad3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. 16 ad3 ? r/w. power down semaphore for audio. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the md3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. intel ? 82801eb ich5 / 82801er ich5r datasheet 577 ac ?97 modem controller registers (d31:f6) 15 read completion status (rcs) ? r/wc. this bit indicates the status of codec read completions. software clears this bit by writing a 1 to it. 0 = a codec read completes normally. 1 = a codec read results in a time-out. this bit is not affected by d3 hot to d0 reset. 14 bit 3 of slot 12 ? ro. display bit 3 of the most recent slot 12. 13 bit 2 of slot 12 ? ro. display bit 2 of the most recent slot 12. 12 bit 1 of slot 12 ? ro. display bit 1 of the most recent slot 12. 11 ac_sdin1 resume interrupt (s1ri) ? r/wc. this bit indicates that a resume event occurred on ac_sdin1. software clears this bit by writing a 1 to it. 0 = resume event did not occur. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 10 ac_sdin0 resume interrupt (s0ri) ? r/wc. this bit indicates that a resume event occurred on ac_sdin0. software clears this bit by writing a 1 to it. 0 = resume event did not occur. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 9 ac_sdin1 codec ready (s1cr) ? ro. this bit reflects the state of the codec ready bit in ac_sdin1. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 8 ac_sdin0 codec ready (s0cr) ? ro. this bit reflects the state of the codec ready bit in ac_sdin 0. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 7 microphone in interrupt (mint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the mic in channel interrupts status bits has been set. 6 pcm out interrupt (point) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm out channel interrupts status bits has been set. 5 pcm in interrupt (piint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm in channel interrupts status bits has been set. 4:3 reserved 2 modem out interrupt (moint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the modem out channel interrupts status bits has been set. 1 modem in interrupt (miint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the modem in channel interrupts status bits has been set. 0 gpi status change interrupt (gsci) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set. this indicates that one of the gpi?s changed state, and that the new values are available in slot 12. this bit is not affected by d3 hot to d0 reset. bit description 578 intel ? 82801eb ich5 / 82801er ich5r datasheet ac ?97 modem controller registers (d31:f6) note: on reads from a codec, the controller will give the codec a maximum of four frames to respond, after which if no response is received, it will return a dummy read completion to the processor (with all f?s on the data) and also set the read completion status bit in the gsr. note: reads across dword boundaries are not supported. 16.2.10 cas?codec access semaphore register (modem?d31:f6) i/o address: nabmbar + 44h attribute: r/w (special) default value: 00h size: 8 bits lockable: no power well: core note: reads across dword boundaries are not supported. bit description 7:1 reserved 0 codec access semaphore (cas) ? r/w (special). this bit is read by software to check whether a codec access is currently in progress. 0 = no access in progress. 1 = the act of reading this register sets this bit to 1. the driver that read this bit can then perform an i/o access. once the access is completed, hardware automatically clears this bit. intel ? 82801eb ich5 / 82801er ich5r datasheet 579 high-precision event timer registers high-precision event timer registers 17 the timer registers are memory-mapped in a non-indexed scheme. this allows the processor to directly access each register without having to use an index register. the timer register space is 1024 bytes. the registers are generally aligned on 64-bit boundaries to simplify implementation with ia64 processors. there are four possible memory address ranges beginning at 1) fed0_0000h, 2) fed0_1000h, 3) fed0_2000h., 4) fed0_4000h. the choice of address range will be selected by configuration bits in general control register (offset d0h) in device 31, function 0. behavioral rules: 1. software must not attempt to read or write across register boundaries. for example, a 32-bit access should be to offset x0h, x4h, x8h, or xch. 32-bit accesses should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0ah, 0bh, 0dh, 0eh, or 0fh. any accesses to these offsets will result in an unexpected behavior, and may result in a master abort. however, these accesses should not result in system hangs. 64-bit accesses can only be to x0h and must not cross 64-bit boundaries. 2. software should not write to read-only registers. 3. software should not expect any particular or consistent value when reading reserved registers or bits. table 174. memory-mapped registers offset mnemonic register default type 000?007h gcap_id general capabilities and identification 0429b17f80 86a201h ro 008?00fh ? reserved ? ? 010?017h gen_conf general configuration 0000h r/w 018?01fh ? reserved ? ? 020?027h gintr_sta general interrupt status 0000h r/wc 028?0efh ? reserved ? ? 0f0?0f7h main_cnt main counter value n/a r/w 0f8?0ffh ? reserved ? ? 100?107h tim1_conf timer 0 configuration and capabilities n/a r/w 108?10fh tim1_comp timer 0 comparator value n/a r/w 110?11fh ? reserved ? ? 120?127h tim2_conf timer 1 configuration and capabilities n/a r/w 128?12fh tim2_comp timer 1 comparator value n/a r/w 130?13fh ? reserved ? ? 140?147h tim3_conf timer 2 configuration and capabilities n/a r/w 148?14fh tim3_comp timer 2 comparator value n/a r/w 150?15fh ? reserved ? ? 160?3ffh ? reserved ? ? 580 intel ? 82801eb ich5 / 82801er ich5r datasheet high-precision event timer registers notes: 1. reads to reserved registers or bits will return a value of 0. 2. software must not attempt locks to the memory-mapped i/o ranges for multimedia timers. if attempted, the lock is not honored, which means potential deadlock conditions may occur. intel ? 82801eb ich5 / 82801er ich5r datasheet 581 high-precision event timer registers 17.1 gcap_id?general capabilities and identification register address offset: 00h attribute: ro default value: 0429b17f8086a201h size: 64 bits 17.2 gen_conf?general configuration register address offset: 010h attribute: r/w default value: 0000h size: 64 bits bit description 63:32 main counter tick period (counter_clk_per_cap) ? ro. this field indicates the period at which the counter increments in femptoseconds (10^-15 seconds). this will return 0429b17f when read. this indicates a period of 69841279 fs (69.841279 ns). 31:16 vendor id capability (vendor_id_cap) ? ro. this is a 16-bit value assigned to intel. 15 legacy rout capable (leg_rt_cap) ? ro. hardwired to 1. legacy interrupt rout option is supported. 14 reserved. this bit returns 0 when read. 13 counter size capability (count_size_cap) ? ro. hardwired to 1. counter is 64-bit wide. 12:8 number of timer capability (num_tim_cap) ? ro. this field indicates the number of timers in this block. 02h = three timers. 7:0 revision identification (rev_id) ? ro. this indicates which revision of the function is implemented. default value will be 01h. bit description 63:2 reserved. these bits return 0 when read. 1 legacy rout (leg_rt_cnf) ? r/w. if the enable_cnf bit and the leg_rt_cnf bit are both set, then the interrupts will be routed as follows: ? timer 0 is routed to irq0 in 8259 or irq2 in the i/o apic. ? timer 1 is routed to irq8 in 8259 or irq8 in the i/o apic. ? timer 2-n is routed as per the routing in the timer n config registers. ? if the legacy rout bit is set, the individual routing bits for timers 0 and 1 (apic) will have no impact. ? if the legacy rout bit is not set, the individual routing bits for each of the timers are used. ? this bit will default to 0. bios can set it to 1 to enable the legacy routing, or 0 to disable the legacy routing. 0 overall enable (enable_cnf) ? r/w. this bit must be set to enable any of the timers to generate interrupts. if this bit is 0, then the main counter will halt (will not increment) and no interrupts will be caused by any of these timers. for level-triggered interrupts, if an interrupt is pending when the enable_cnf bit is changed from 1 to 0, the interrupt status indications (in the various txx_int_sts bits) will not be cleared. software must write to the txx_int_sts bits to clear the interrupts. note: this bit will default to 0. bios can set it to 1 or 0. 582 intel ? 82801eb ich5 / 82801er ich5r datasheet high-precision event timer registers 17.3 gintr_sta?general interrupt status register address offset: 020h attribute: r/w, r/wc default value: 0000h size: 64 bits . 17.4 main_cnt?main counter value register address offset: 0f0h attribute: r/w default value: n/a size: 64 bits . bit description 63:3 reserved. these bits will return 0 when read. 2 timer 2 interrupt active (t02_int_sts) ? r/w. same functionality as timer 0. 1 timer 1 interrupt active (t01_int_sts) ? r/w. same functionality as timer 0. 0 timer 0 interrupt active (t00_int_sts) ? r/wc. the functionality of this bit depends on whether the edge or level-triggered mode is used for this timer. (default = 0) if set to level-triggered mode: this bit will be set by hardware if the corresponding timer interrupt is active. once the bit is set, it can be cleared by software writing a 1 to the same bit position. writes of 0 to this bit will have no effect. if set to edge-triggered mode: this bit should be ignored by software. software should always write 0 to this bit. note: defaults to 0. in edge triggered mode, this bit will always read as 0 and writes will have no effect. bit description 63:0 counter value (counter_val[63:0]) ? r/w. reads return the current value of the counter. writes load the new value to the counter. notes: 1. writes to this register should only be done while the counter is halted. 2. reads to this register return the current value of the main counter. 3. 32-bit counters will always return 0 for the upper 32-bits of this register. 4. if 32-bit software attempts to read a 64-bit counter, it should first halt the counter. since this delays the interrupts for all of the timers, this should be done only if the consequences are understood. it is strongly recommended that 32-bit software only operate the timer in 32-bit mode. 5. reads to this register are monotonic. no two consecutive reads return the same value. the second of two reads always returns a larger value (unless the timer has rolled over to 0). intel ? 82801eb ich5 / 82801er ich5r datasheet 583 high-precision event timer registers 17.5 timn_conf?timer n configuration and capabilities register address offset: timer 0: 100?107h, attribute: ro, r/w timer 1: 120?127h, timer 2: 140?147h default value: n/a size: 64 bits note: the letter n can be 0, 1, or 2, referring to timer 0, 1 or 2. bit description 64:56 reserved. these bits will return 0 when read. 55:52, 43 timer interrupt rout capability (timern_int_rout_cap) ?ro. timer 0, 1:bits 52, 53, 54, and 55 in this field (corresponding to irq 20, 21, 22, and 23) have a value of 1. writes will have no effect. timer 2:bits 43, 52, 53, 54, and 55 in this field (corresponding to irq 11, 20, 21, 22, and 23) have a value of 1. writes will have no effect. note: if irq 11 is used for hpet #2, software should ensure irq 11 is not shared with any other devices to guarantee the proper operation of hpet #2. 51:44, 42:14 reserved . these bits return 0 when read. 13:9 interrupt rout (timern_int_rout_cnf) ? r/w. this 5-bit field indicates the routing for the interrupt to the i/o (x) apic. software writes to this field to select which interrupt in the i/o (x) will be used for this timer?s interrupt. if the value is not supported by this particular timer, then the value read back will not match what is written. the software must only write valid values. notes: 1. if the legacy rout bit is set, then timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers. 2. timer 0,1: software is responsible to make sure it programs a valid value (20, 21, 22, or 23) for this field. the intel ? ich5 logic does not check the validity of the value written. 3. timer 2: software is responsible to make sure it programs a valid value (11, 20, 21, 22, or 23) for this field. the ich5 logic does not check the validity of the value written. 8 timer n 32-bit mode (timern_32mode_cnf) ? r/w or ro. software can set this bit to force a 64-bit timer to behave as a 32-bit timer. timer 0:bit is read/write (default to 0). 1 = 64 bit; 0 = 32 bit timers 1, 2:hardwired to 0. writes have no effect (since these two timers are 32-bits). 7 reserved . this bit returns 0 when read. 6 timer n value set (timern_val_set_cnf) ? r/w. software uses this bit only for timer 0 if it has been set to periodic mode. by writing this bit to a 1, the software is then allowed to directly set the timer?s accumulator. software does not have to write this bit back to 1 (it automatically clears). software should not write a 1 to this bit position if the timer is set to non-periodic mode. note: this bit will return 0 when read. writes will only have an effect for timer 0 if it is set to periodic mode. writes will have no effect for timers 1 and 2. 5 timer n size (timern_size_cap) ? ro. this read only field indicates the size of the timer. timer 0:value is 1 (64-bits). timers 1, 2:value is 0 (32-bits). 4 periodic interrupt capable (timern_per_int_cap) ? ro. if this bit is 1, the hardware supports a periodic mode for this timer?s interrupt. timer 0: hardwired to 1 (supports the periodic interrupt). timers 1, 2: hardwired to 0 (does not support periodic interrupt). 584 intel ? 82801eb ich5 / 82801er ich5r datasheet high-precision event timer registers note: reads or writes to unimplemented timers should not be attempted. read from any unimplemented registers will return an undetermined value. 3 timer n type (timern_type_cnf) ? r/w or ro. timer 0:bit is read/write. 0 = disable timer to generate periodic interrupt; 1 = enable timer to generate a periodic interrupt. timers 1, 2: hardwired to 0. writes have no affect. 2 timer n interrupt enable (timern_int_enb_cnf) ? r/w. this bit must be set to enable timer n to cause an interrupt when it times out. 1 = enable 0 = disable (default). the timer can still count and generate appropriate status bits, but will not cause an interrupt. 1 timer interrupt type (timern_int_type_cnf) ? r/w. 0 =the timer interrupt is edge triggered. this means that an edge-type interrupt is generated. if another interrupt occurs, another edge will be generated. 1 =the timer interrupt is level triggered. this means that a level-triggered interrupt is generated. the interrupt will be held active until it is cleared by writing to the bit in the general interrupt status register. if another interrupt occurs before the interrupt is cleared, the interrupt will remain active. 0 reserved. these bits will return 0 when read. bit description intel ? 82801eb ich5 / 82801er ich5r datasheet 585 high-precision event timer registers 17.6 timn_comp?timer n comparator value register address offset: timer 0: 108h?10fh, timer 1: 128h?12fh, timer 2: 148h?14fh attribute: r/w default value: n/a size: 64 bit bit description 63:0 timer compare value ? r/w. reads to this register return the current value of the comparator. timers 0, 1, or 2 are configured to non-periodic mode: writes to this register load the value against which the main counter should be compared for this timer. ? when the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). ? the value in this register does not change based on the interrupt being generated. timer 0 is configured to periodic mode: ? when the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). ? after the main counter equals the value in this register, the value in this register is increased by the value last written to the register. for example, if the value written to the register is 00000123h, then 1. an interrupt will be generated when the main counter reaches 00000123h. 2. the value in this register will then be adjusted by the hardware to 00000246h. 3. another interrupt will be generated when the main counter reaches 00000246h 4. the value in this register will then be adjusted by the hardware to 00000369h ? as each periodic interrupt occurs, the value in this register will increment. when the incremented value is greater than the maximum value possible for this register (ffffffffh for a 32-bit timer or ffffffffffffffffh for a 64-bit timer), the value will wrap around through 0. for example, if the current value in a 32-bit timer is ffff0000h and the last value written to this register is 20000, then after the next interrupt the value will change to 00010000h default value for each timer is all 1s for the bits that are implemented. for example, a 32-bit timer has a default value of 00000000ffffffffh. a 64-bit timer has a default value of ffffffffffffffffh. 586 intel ? 82801eb ich5 / 82801er ich5r datasheet high-precision event timer registers this page is intentionally left blank. intel ? 82801eb ich5 / 82801er ich5r datasheet 587 ballout definition ballout definition 18 this section contains the ich5 ballout information. figure 1 and figure 2 are the ballout map of the 460 mbga package. table 175 is an mbga ball list, sorted alphabetically by signal name. table 176 is an mbga ball list, sorted alphabetically by ball number. 588 intel ? 82801eb ich5 / 82801er ich5r datasheet ballout definition figure 1. intel ? ich5 ballout (topview?left side) begin123456789101112 a vss pirqc# gnt1# gnt4# / gpio48 reqa# / gpio0 pirqf# / gpio3 vss v5ref ac_sdout vss no connect ee_shclk b pirqh# / gpio5 ad18 pirqa# gntb# / gnt5# / gpio17 vcc3_3 req3# gnt2# ac_sync ee_dout ee_cs ee_din lan_txd2 c req1# pirqd# vss ad22 req2# req4# / gpio40 gnt3# vss lan_rxd1 lan_rxd0 lan_rxd2 ac_rst# d vss frame# ad26 gnt0# req0# vss pirqe# / gpio2 ac_bit_clk lan_txd0 lan _rstsync vss ac_sdin1 e pirqb# pirqg# / gpio4 c/be0# trdy# stop# ad24 reqb# / req5#/ gpio1 gnta# / gpio16 lan_txd1 lan_clk vccsus3_3 ac_sdin0 f par ad9 vss ad30 ad28 vcc3_3 vccsus1_5 _c vccsus1_5 _c vss vccsus3_3 vccsus3_3 void g vcc3_3 ad13 ad2 ad16 ad15 vss void void void void void void h vss ad5 ad20 ad11 ad4 vcc3_3 void void void void void void j c/be1# ad7 ad6 ad0 ad1 vss void void void void void void k ad14 perr# vss ad3 ad8 vcc3_3 void void void vcc1_5 vss vcc1_5 l ad17 plock# devsel# serr# ad12 vcc3_3 void void void vss vss vss m vss c/be3# irdy# ad10 vss void void void void vcc3_3 vss vss n pciclk ad27 c/be2# ad23 ad21 void void void void vcc3_3 vss vss p vss ad31 ad25 ad29 ad19 vcc3_3 void void void vss vss vss r gpio21 ldrq1# / gpio41 lad2 / fb2 lad1 / fb1 gpio6 vcc1_5 void void void vcc1_5 vss vcc1_5 t gpio32 thrm# vss lframe# / fb4 lad0 / fb0 vss void void void void void void u sys_reset# slp_s4# gpio7 lad3 / fb3 ldrq0# vccsus3_3 void void void void void void v vss pme# gpio27 pcirst# linkalert# vccsus3_3 void void void void void void w slp_s3# gpio28 gpio25 gpio12 gpio13 vcc1_5 vcc1_5 vcc1_5 vcc1_5 vcc1_5 vcc1_5 void y susclk gpio8 vss pwrbtn# vccsus1_5 _b vss vss vss satarbias# vss satarbias intruder# aa lan_rst# smlink1 slp_s5# vccsus1_5 _b vss vccsata pll vss sata0txp vss sata1txp vss rtcrst# ab sus_stat# tp0 ri# vccsus1_5 _b vss vccsata pll vss sata0txn vss sata1txn vss rtcx2 ac gpio24 vss smbalert# / gpio11 vss clk100p vss sata0rxp vss sata1rxp vss rtcx1 pwrok ad smbdata smbclk smlink0 vss clk100n vss sata0rxn vss sata1rxn intvrmen vccrtc vss end 123456789101112 intel ? 82801eb ich5 / 82801er ich5r datasheet 589 ballout definition figure 2. intel ? ich5 ballout (topview?right side) 13 14 15 16 17 18 19 20 21 22 23 24 ac_sdin2 oc5# / gpio10 vss usbp7p vss usbp5p vss usbp3p vss usbp1p vss usbrbias a vss oc4# / gpio9 vccsus3_3 usbp7n vss usbp5n vss usbp3n vss usbp1n vss usbrbias# b oc7# / gpio15 oc3# oc0# vss usbp6p vss usbp4p vss usbp2p vss usbp0p vccusb pll c oc6# / gpio14 oc2# oc1# vss usbp6n vss usbp4n vss usbp2n vss usbp0n vss d vccsus3_3 vccsus3_3 vcc1_5 v5ref_sus vss vccsus3_3 vss vss vss vcc1_5 vss spkr e void vcc1_5 vcc1_5 vccsus3_3 vccsus3_3 vccsus3_3 vccsus1_5 _a clk14 gpio34 gpio23 serirq clk48 f void void void void void void vcc3_3 vss vcc3_3 hi11 sataled# vss g void void void void void void vss hi0 hi1 vss hi3 vcc1_5 h void void void void void void vcc1_5 hi2 vss hi9 vss hi_stbs j vcc1_5 vss vccsus3_3 void void void vcc1_5 vss hi10 vss hi_stbf vss k vss vss vss void void void vcc1_5 hi_vswing vss hi8 vss hiref l vss vss vcc1_5 void void void void hi7 hi5 vss hi4 vss m vss vss vcc1_5 void void void void vss hi6 clk66 vcc1_5 hircomp n vss vss vss void void void vcc1_5 tp1 vss cpuslp# rcin# cpupwrgd / gpio49 p vcc3_3 vss v_cpu_io void void void v_cpu_io vrmpwrgd ignne# nmi init# tp2 r void void void void void void v_cpu_io gpio19 thrmtrip# a20gate vss stpclk# t void void void void void void vss gpio22 gpio18 gpio20 intr ferr# u void void void void void void vcc3_3 sdcs3# vss sdcs1# a20m# smi# v void v5ref vcc3_3 vss vcc3_3 vss vcc1_5 sddack# sda2 sda0 sda1 vcc3_3 w pdd1 pdd2 pdd9 pdd13 irq14 pdcs3# sdd8 sddreq siordy sdiow# sdior# irq15 y vss pdd4 pdd11 pdd14 pdiow# piordy pda0 sdd11 vss sdd0 sdd15 vss aa rsmrst# pdd7 vss pdd0 pdd15 vss pdcs1# sdd6 sdd4 sdd12 sdd1 sdd14 ab vss pdd3 pdd5 pdd12 pddreq pddack# pda2 sdd7 sdd5 sdd10 vss sdd13 ac vcc3_3 pdd6 pdd8 pdd10 vss pdior# pda1 vcc3_3 vss sdd9 sdd2 sdd3 ad 13 14 15 16 17 18 19 20 21 22 23 24 590 intel ? 82801eb ich5 / 82801er ich5r datasheet ballout definition table 175. intel ? ich5 ballout by signal name signal name ball # a20gate t22 a20m# v23 ac_bit_clk d8 ac_rst# c12 ac_sdin0 e12 ac_sdin1 d12 ac_sdin2 a13 ac_sdout a9 ac_sync b8 ad0 j4 ad1 j5 ad2 g3 ad3 k4 ad4 h5 ad5 h2 ad6 j3 ad7 j2 ad8 k5 ad9 f2 ad10 m4 ad11 h4 ad12 l5 ad13 g2 ad14 k1 ad15 g5 ad16 g4 ad17 l1 ad18 b2 ad19 p5 ad20 h3 ad21 n5 ad22 c4 ad23 n4 ad24 e6 ad25 p3 ad26 d3 ad27 n2 ad28 f5 ad29 p4 ad30 f4 ad31 p2 gpio6 r5 tp0 ab2 c/be0# e3 c/be1# j1 c/be2# n3 c/be3# m2 gpio21 r1 clk14 f20 clk48 f24 clk66 n22 clk100n ad5 clk100p ac5 gpio24 ac1 gpio22 u20 cpupwrgd/gpio49 p24 cpuslp# p22 devsel# l3 tp1 p20 tp2 r24 ee_cs b10 ee_din b11 ee_dout b9 ee_shclk a12 ferr# u24 frame# d2 gnt0# d4 gnt1# a3 gnt2# b7 gnt3# c7 gnt4#/gpio48 a4 gnta#/gpio16 e8 gntb#/ gnt5#gpio17 b4 gpio7 u3 gpio8 y2 gpio12 w4 gpio13 w5 gpio25 w3 gpio27 v3 gpio28 w2 gpio32 t1 table 175. intel ? ich5 ballout by signal name signal name ball # gpio34 f21 hi_stbf k23 hi_stbs j24 hi0 h20 hi1 h21 hi2 j20 hi3 h23 hi4 m23 hi5 m21 hi6 n21 hi7 m20 hi8 l22 hi9 j22 hi10 k21 hi11 g22 hircomp n24 hiref l24 hi_vswing l20 ignne# r21 init# r23 intr u23 intruder# y12 intvrmen ad10 irdy# m3 irq14 y17 irq15 y24 lad0 t5 lad1 r4 lad2 r3 lad3 u4 lan_clk e10 lan_rst# aa1 lan_rstsync d10 lan_rxd0 c10 lan_rxd1 c9 lan_rxd2 c11 lan_txd0 d9 lan_txd1 e9 lan_txd2 b12 ldrq0# u5 ldrq1# / gpio41 r2 table 175. intel ? ich5 ballout by signal name signal name ball # intel ? 82801eb ich5 / 82801er ich5r datasheet 591 ballout definition lframe# t4 linkalert# v5 nmi r22 no connect a11 oc0# c15 oc1# d15 oc2# d14 oc3# c14 oc4# / gpio9 b14 oc5# / gpio10 a14 oc6# / gpio14 d13 oc7# / gpio15 c13 par f1 pciclk n1 pcirst# v4 pda0 aa19 pda1 ad19 pda2 ac19 pdcs1# ab19 pdcs3# y18 pdd0 ab16 pdd1 y13 pdd2 y14 pdd3 ac14 pdd4 aa14 pdd5 ac15 pdd6 ad14 pdd7 ab14 pdd8 ad15 pdd9 y15 pdd10 ad16 pdd11 aa15 pdd12 ac16 pdd13 y16 pdd14 aa16 pdd15 ab17 pddack# ac18 pddreq ac17 pdior# ad18 pdiow# aa17 perr# k2 table 175. intel ? ich5 ballout by signal name signal name ball # piordy aa18 pirqa# b3 pirqb# e1 pirqc# a2 pirqd# c2 pirqe#/gpio2 d7 pirqf#/gpio3 a6 pirqg#/gpio4 e2 pirqh#/gpio5 b1 plock# l2 pme# v2 pwrbtn# y4 pwrok ac12 rcin# p23 req0# d5 req1# c1 req2# c5 req3# b6 req4#/gpio40 c6 reqa#/gpio0 a5 reqb#/req5#/ gpio1 e7 ri# ab3 rsmrst# ab13 rtcrst# aa12 rtcx1 ac11 rtcx2 ab12 sataled# g23 satarbias# y9 satarbias y11 sata0rxn ad7 sata0rxp ac7 sata1rxn ad9 sata1rxp ac9 sata0txn ab8 sata0txp aa8 sata1txn ab10 sata1txp aa10 sda0 w22 sda1 w23 sda2 w21 table 175. intel ? ich5 ballout by signal name signal name ball # sdcs1# v22 sdcs3# v20 sdd0 aa22 sdd1 ab23 sdd2 ad23 sdd3 ad24 sdd4 ab21 sdd5 ac21 sdd6 ab20 sdd7 ac20 sdd8 y19 sdd9 ad22 sdd10 ac22 sdd11 aa20 sdd12 ab22 sdd13 ac24 sdd14 ab24 sdd15 aa23 sddack# w20 sddreq y20 sdior# y23 sdiow# y22 serirq f23 serr# l4 siordy y21 gpio19 t20 slp_s3# w1 slp_s4# u2 slp_s5# aa3 smbalert#/gpio11 ac3 smbclk ad2 smbdata ad1 smi# v24 smlink0 ad3 smlink1 aa2 spkr e24 gpio23 f22 stop# e5 gpio20 u22 gpio18 u21 stpclk# t24 table 175. intel ? ich5 ballout by signal name signal name ball # 592 intel ? 82801eb ich5 / 82801er ich5r datasheet ballout definition sus_stat# ab1 susclk y1 sys_reset# u1 thrm# t2 thrmtrip# t21 trdy# e4 usbp0n d23 usbp0p c23 usbp1n b22 usbp1p a22 usbp2n d21 usbp2p c21 usbp3n b20 usbp3p a20 usbp4n d19 usbp4p c19 usbp5n b18 usbp5p a18 usbp6n d17 usbp6p c17 usbp7n b16 usbp7p a16 usbrbias a24 usbrbias# b24 v_cpu_io r15 v_cpu_io r19 v_cpu_io t19 v5ref a8 v5ref w14 v5ref_sus e16 vcc1_5 e15 vcc1_5 f14 vcc1_5 f15 vcc1_5 h24 vcc1_5 j19 vcc1_5 k19 vcc1_5 k10 vcc1_5 k12 vcc1_5 k13 vcc1_5 l19 vcc1_5 m15 table 175. intel ? ich5 ballout by signal name signal name ball # vcc1_5 n15 vcc1_5 n23 vcc1_5 p19 vcc1_5 r10 vcc1_5 r12 vcc1_5 r6 vcc1_5 w10 vcc1_5 w11 vcc1_5 w19 vcc1_5 w6 vcc1_5 w7 vcc1_5 w8 vcc1_5 w9 vcc3_3 ad13 vcc3_3 ad20 vcc3_3 b5 vcc3_3 f6 vcc3_3 g1 vcc3_3 g19 vcc3_3 g21 vcc3_3 h6 vcc3_3 k6 vcc3_3 l6 vcc3_3 m10 vcc3_3 n10 vcc3_3 p6 vcc3_3 r13 vcc3_3 v19 vcc3_3 w15 vcc3_3 w17 vcc3_3 w24 vccsus1_5_c f7 vccsus1_5_c f8 vccsus3_3 e11 vccsus3_3 f10 vccsus3_3 f11 vccrtc ad11 vccsatapll aa6 vccsatapll ab6 vccsus1_5_b aa4 vccsus1_5_b ab4 table 175. intel ? ich5 ballout by signal name signal name ball # vcc1_5 e22 vccsus1_5_a f19 vccsus1_5_b y5 vccsus3_3 b15 vccsus3_3 k15 vccsus3_3 e13 vccsus3_3 e14 vccsus3_3 e18 vccsus3_3 f16 vccsus3_3 f17 vccsus3_3 f18 vccsus3_3 u6 vccsus3_3 v6 vccusbpll c24 vrmpwrgd r20 vss a1 vss a10 vss a15 vss a17 vss a19 vss a21 vss a23 vss a7 vss aa11 vss aa13 vss aa21 vss aa24 vss aa5 vss aa7 vss aa9 vss ab11 vss ab15 vss ab18 vss ab5 vss ab7 vss ab9 vss ac10 vss ac13 vss ac2 vss ac23 vss ac4 table 175. intel ? ich5 ballout by signal name signal name ball # intel ? 82801eb ich5 / 82801er ich5r datasheet 593 ballout definition vss ac6 vss ac8 vss ad4 vss ad6 vss ad8 vss ad12 vss ad17 vss ad21 vss b13 vss b17 vss b19 vss b21 vss b23 vss c16 vss c18 vss c20 vss c22 vss c3 vss c8 vss d1 vss d11 vss d16 vss d18 vss d20 vss d22 vss d24 vss d6 vss e17 vss e19 vss e20 vss e21 vss e23 vss f3 vss f9 vss g20 vss g24 vss g6 vss h1 vss h19 vss h22 vss j21 table 175. intel ? ich5 ballout by signal name signal name ball # vss j23 vss j6 vss k11 vss k14 vss k20 vss k22 vss k24 vss k3 vss l10 vss l11 vss l12 vss l13 vss l14 vss l15 vss l21 vss l23 vss m1 vss m11 vss m12 vss m13 vss m14 vss m22 vss m24 vss m5 vss n11 vss n12 vss n13 vss n14 vss n20 vss p1 vss p10 vss p11 vss p12 vss p13 vss p14 vss p15 vss p21 vss r11 vss r14 vss t23 vss t3 table 175. intel ? ich5 ballout by signal name signal name ball # vss t6 vss u19 vss v1 vss v21 vss w16 vss w18 vss y10 vss y3 vss y6 vss y7 vss y8 table 175. intel ? ich5 ballout by signal name signal name ball # 594 intel ? 82801eb ich5 / 82801er ich5r datasheet ballout definition table 176. intel ? ich5 ballout by ball number ball # signal name a1 vss a2 pirqc# a3 gnt1# a4 gnt4#/gpio48 a5 reqa#/gpio0 a6 pirqf#/gpio3 a7 vss a8 v5ref a9 ac_sdout a10 vss a11 no connect a12 ee_shclk a13 ac_sdin2 a14 oc5# / gpio10 a15 vss a16 usbp7p a17 vss a18 usbp5p a19 vss a20 usbp3p a21 vss a22 usbp1p a23 vss a24 usbrbias aa1 lan_rst# aa2 smlink1 aa3 slp_s5# aa4 vccsus1_5_b aa5 vss aa6 vccsatapll aa7 vss aa8 sata0txp aa9 vss aa10 sata1txp aa11 vss aa12 rtcrst# aa13 vss aa14 pdd4 aa15 pdd11 aa16 pdd14 aa17 pdiow# aa18 piordy aa19 pda0 aa20 sdd11 aa21 vss aa22 sdd0 aa23 sdd15 aa24 vss ab1 sus_stat# ab2 tp0 ab3 ri# ab4 vccsus1_5_b ab5 vss ab6 vccsatapll ab7 vss ab8 sata0txn ab9 vss ab10 sata1txn ab11 vss ab12 rtcx2 ab13 rsmrst# ab14 pdd7 ab15 vss ab16 pdd0 ab17 pdd15 ab18 vss ab19 pdcs1# ab20 sdd6 ab21 sdd4 ab22 sdd12 ab23 sdd1 ab24 sdd14 ac1 gpio24 ac2 vss ac3 smbalert#/gpio11 ac4 vss ac5 clk100p ac6 vss ac7 sata0rxp ac8 vss ac9 sata1rxp ac10 vss table 176. intel ? ich5 ballout by ball number ball # signal name ac11 rtcx1 ac12 pwrok ac13 vss ac14 pdd3 ac15 pdd5 ac16 pdd12 ac17 pddreq ac18 pddack# ac19 pda2 ac20 sdd7 ac21 sdd5 ac22 sdd10 ac23 vss ac24 sdd13 ad1 smbdata ad2 smbclk ad3 smlink0 ad4 vss ad5 clk100n ad6 vss ad7 sata0rxn ad8 vss ad9 sata1rxn ad10 intvrmen ad11 vccrtc ad12 vss ad13 vcc3_3 ad14 pdd6 ad15 pdd8 ad16 pdd10 ad17 vss ad18 pdior# ad19 pda1 ad20 vcc3_3 ad21 vss ad22 sdd9 ad23 sdd2 ad24 sdd3 b1 pirqh#/gpio5 b2 ad18 b3 pirqa# table 176. intel ? ich5 ballout by ball number ball # signal name intel ? 82801eb ich5 / 82801er ich5r datasheet 595 ballout definition b4 gntb#/ gnt5#gpio17 b5 vcc3_3 b6 req3# b7 gnt2# b8 ac_sync b9 ee_dout b10 ee_cs b11 ee_din b12 lan_txd2 b13 vss b14 oc4# / gpio9 b15 vccsus3_3 b16 usbp7n b17 vss b18 usbp5n b19 vss b20 usbp3n b21 vss b22 usbp1n b23 vss b24 usbrbias# c1 req1# c2 pirqd# c3 vss c4 ad22 c5 req2# c6 req4#/gpio40 c7 gnt3# c8 vss c9 lan_rxd1 c10 lan_rxd0 c11 lan_rxd2 c12 ac_rst# c13 oc7# / gpio15 c14 oc3# c15 oc0# c16 vss c17 usbp6p c18 vss c19 usbp4p table 176. intel ? ich5 ballout by ball number ball # signal name c20 vss c21 usbp2p c22 vss c23 usbp0p c24 vccusbpll d1 vss d2 frame# d3 ad26 d4 gnt0# d5 req0# d6 vss d7 pirqe#/gpio2 d8 ac_bit_clk d9 lan_txd0 d10 lan_rstsync d11 vss d12 ac_sdin1 d13 oc6# / gpio14 d14 oc2# d15 oc1# d16 vss d17 usbp6n d18 vss d19 usbp4n d20 vss d21 usbp2n d22 vss d23 usbp0n d24 vss e1 pirqb# e2 pirqg#/gpio4 e3 c/be0# e4 trdy# e5 stop# e6 ad24 e7 reqb#/req5#/ gpio1 e8 gnta#/gpio16 e9 lan_txd1 e10 lan_clk e11 vccsus3_3 table 176. intel ? ich5 ballout by ball number ball # signal name e12 ac_sdin0 e13 vccsus3_3 e14 vccsus3_3 e15 vcc1_5 e16 v5ref_sus e17 vss e18 vccsus3_3 e19 vss e20 vss e21 vss e22 vcc1_5 e23 vss e24 spkr f1 par f2 ad9 f3 vss f4 ad30 f5 ad28 f6 vcc3_3 f7 vccsus1_5_c f8 vccsus1_5_c f9 vss f10 vccsus3_3 f11 vccsus3_3 f14 vcc1_5 f15 vcc1_5 f16 vccsus3_3 f17 vccsus3_3 f18 vccsus3_3 f19 vccsus1_5_a f20 clk14 f21 gpio34 f22 gpio23 f23 serirq f24 clk48 g1 vcc3_3 g2 ad13 g3 ad2 g4 ad16 g5 ad15 g6 vss table 176. intel ? ich5 ballout by ball number ball # signal name 596 intel ? 82801eb ich5 / 82801er ich5r datasheet ballout definition g19 vcc3_3 g20 vss g21 vcc3_3 g22 hi11 g23 sataled# g24 vss h1 vss h2 ad5 h3 ad20 h4 ad11 h5 ad4 h6 vcc3_3 h19 vss h20 hi0 h21 hi1 h22 vss h23 hi3 h24 vcc1_5 j1 c/be1# j2 ad7 j3 ad6 j4 ad0 j5 ad1 j6 vss j19 vcc1_5 j20 hi2 j21 vss j22 hi9 j23 vss j24 hi_stbs k1 ad14 k2 perr# k3 vss k4 ad3 k5 ad8 k6 vcc3_3 k10 vcc1_5 k11 vss k12 vcc1_5 k13 vcc1_5 k14 vss table 176. intel ? ich5 ballout by ball number ball # signal name k15 vccsus3_3 k19 vcc1_5 k20 vss k21 hi10 k22 vss k23 hi_stbf k24 vss l1 ad17 l2 plock# l3 devsel# l4 serr# l5 ad12 l6 vcc3_3 l10 vss l11 vss l12 vss l13 vss l14 vss l15 vss l19 vcc1_5 l20 hi_vswing l21 vss l22 hi8 l23 vss l24 hiref m1 vss m2 c/be3# m3 irdy# m4 ad10 m5 vss m10 vcc3_3 m11 vss m12 vss m13 vss m14 vss m15 vcc1_5 m20 hi7 m21 hi5 m22 vss m23 hi4 m24 vss table 176. intel ? ich5 ballout by ball number ball # signal name n1 pciclk n2 ad27 n3 c/be2# n4 ad23 n5 ad21 n10 vcc3_3 n11 vss n12 vss n13 vss n14 vss n15 vcc1_5 n20 vss n21 hi6 n22 clk66 n23 vcc1_5 n24 hircomp p1 vss p2 ad31 p3 ad25 p4 ad29 p5 ad19 p6 vcc3_3 p10 vss p11 vss p12 vss p13 vss p14 vss p15 vss p19 vcc1_5 p20 tp1 p21 vss p22 cpuslp# p23 rcin# p24 cpupwrgd/gpio49 r1 gpio21 r2 ldrq1# / gpio41 r3 lad2 r4 lad1 r5 gpio6 r6 vcc1_5 r10 vcc1_5 table 176. intel ? ich5 ballout by ball number ball # signal name intel ? 82801eb ich5 / 82801er ich5r datasheet 597 ballout definition r11 vss r12 vcc1_5 r13 vcc3_3 r14 vss r15 v_cpu_io r19 v_cpu_io r20 vrmpwrgd r21 ignne# r22 nmi r23 init# r24 tp2 t1 gpio32 t2 thrm# t3 vss t4 lframe# t5 lad0 t6 vss t19 v_cpu_io t20 gpio19 t21 thrmtrip# t22 a20gate t23 vss t24 stpclk# u1 sys_reset# u2 slp_s4# u3 gpio7 u4 lad3 u5 ldrq0# u6 vccsus3_3 u19 vss u20 gpio22 u21 gpio18 u22 gpio20 u23 intr u24 ferr# v1 vss v2 pme# v3 gpio27 v4 pcirst# v5 linkalert# v6 vccsus3_3 table 176. intel ? ich5 ballout by ball number ball # signal name v19 vcc3_3 v20 sdcs3# v21 vss v22 sdcs1# v23 a20m# v24 smi# w1 slp_s3# w2 gpio28 w3 gpio25 w4 gpio12 w5 gpio13 w6 vcc1_5 w7 vcc1_5 w8 vcc1_5 w9 vcc1_5 w10 vcc1_5 w11 vcc1_5 w14 v5ref w15 vcc3_3 w16 vss w17 vcc3_3 w18 vss w19 vcc1_5 w20 sddack# w21 sda2 w22 sda0 w23 sda1 w24 vcc3_3 y1 susclk y2 gpio8 y3 vss y4 pwrbtn# y5 vccsus1_5_b y6 vss y7 vss y8 vss y9 satarbias# y10 vss y11 satarbias y12 intruder# y13 pdd1 table 176. intel ? ich5 ballout by ball number ball # signal name y14 pdd2 y15 pdd9 y16 pdd13 y17 irq14 y18 pdcs3# y19 sdd8 y20 sddreq y21 siordy y22 sdiow# y23 sdior# y24 irq15 table 176. intel ? ich5 ballout by ball number ball # signal name 598 intel ? 82801eb ich5 / 82801er ich5r datasheet ballout definition this page is intentionally left blank. intel ? 82801eb ich5 / 82801er ich5r datasheet 599 electrical characteristics electrical characteristics 19 this chapter contains thermal, dc, and ac characteristics for the ich5. ac timing diagrams are included. 19.1 thermal specifications refer to the intel ? 82801eb i/o controller hub (ich5) / intel ? 82801er i/o controller hub 5 r (ich5r) thermal design guide for ich5 thermal information. 19.2 dc characteristics 1. only the g3 state for this power well is shown to provide an estimate of battery life. 2. icc(rtc) data is taken with vccrtc at 3.0 v while the system is in a mechanical off (g3) state at room temperature. 3. due to the integrated voltage regulator, vccsus1_5 is part of the vccsus3_3 power rail. table 177. dc current characteristics power plane maximum power consumption so s1 s3 s4/s5 g3 vcc1_5 core 770 ma 201 ma n/a n/a n/a vcc3_3 i/o 480 ma 1 ma n/a n/a n/a vccsus3_3 (3) 360 ma 73 ma 73 ma 73 ma n/a vccrtc n/a n/a n/a n/a 6 a (1,2) v_cpu_io 2.5 ma 2.5 ma n/a n/a n/a v5ref 250 a 250 an/a n/a n/a v5ref_sus 200 a 200 a 200 a 200 an/a 600 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics table 178. dc characteristic input signal association symbol associated signals v ih1 /v il1 (5v tolerant) pc/pci signals: ad[31:0], c/be[3:0]#, devsel#, frame#, irdy#, trdy#, stop#, par, perr#, plock#, serr#, req[4:0]#, reqa#, reqb#/req5# gpio signals: gpio[40, 1:0] v ih2 /v il2 (5v tolerant) interrupt signals: irq[15:14], pirq[d:a]#, pirq[h:e]#/gpio[5:2] legacy signals: rcin#, a20gate gpio signals: gpio[7:6] v ih3 /v il3 clock signals : clk66, clk48, clk14 interrupt signals: serirq power management signals: pme#, pwrbtn#, ri#, lan_rst#, rtcrst#, sys_reset#, thrm#, vrmpwrgd eeprom signals: ee_din sata signals: sata_led# gpio signals: gpio[34, 32, 28:27, 25:24, 13:12, 8] v ih4 /v il4 clock signals: pciclk lpc/flash bios signals: ldrq[1:0]#, lad[3:0]/fb[3:0] gpio signals: gpio41 v ih5 /v il5 smbus signals: smbclk, smbdata system management signals: intruder#, smlink[1:0], smbalert#/gpio11, linkalert# power management signals: rsmrst#, pwrok v il6 /v ih6 lan signals: lan_rxd[2:0], lan_clk v il7 /v ih7 processor signals: ferr#, thrmtrip# v il8 /v ih8 hub interface signals : hi[11:0], hi_stbs, hi_stbf v il9 /v ih9 real time clock signals: rtcx1 v il10 /v ih10 sata signals: sata[1:0]rx[p,n] v il11 /v ih11 (5v tolerant) usb signals: oc[7:0]# gpio signals: gpio[15:14, 10:9] v il12 /v ih12 ac?97 signals: ac_bitclk, ac_sdin[2:0] v il13 /v ih13 / vcross(abs) clock signals: clk100p, clk100n v+/v-/vhys/ vthravg/vring (5v tolerant) ide signals: pdd[15:0], sdd[15:0], pddreq, piordy, sddreq, siordy for ultra dma mode 4 and lower these signals, follow the dc characteristics for v ih2 / v il2 . v di / v cm / v se (5v tolerant) usb signals: usbp[7:0][p,n] (low-speed and full-speed) v hssq / v hsdsc / v hscm (5v tolerant) usb signals: usbp[7:0][p,n] (in high-speed mode) intel ? 82801eb ich5 / 82801er ich5r datasheet 601 electrical characteristics table 179. dc input characteristics (sheet 1 of 2) symbol parameter min max unit notes v il1 input low voltage ? 0.5 0.3vcc3_3 v v ih1 input high voltage 0.5vcc3_3 v5ref + 0.5 v v il2 input low voltage ? 0.5 0.8 v v ih2 input high voltage 2.0 v5ref + 0.5 v v il3 input low voltage ? 0.5 0.8 v v ih3 input high voltage 2.0 vcc3_3 + 0.5 v v il4 input low voltage ? 0.5 0.3vcc3_3 v v ih4 input high voltage 0.5vcc3_3 vcc3_3 + 0.5 v v il5 input low voltage ? 0.5 0.8 v v ih5 input high voltage 2.1 vccsus3_3 + 0.5 v v il6 input low voltage ? 0.5 0.3vcc3_3 v v ih6 input high voltage 0.6vcc3_3 vcc3_3 + 0.5 v v il7 input low voltage ? 0.15 0.58(v_cpu_io) v v ih7 input high voltage 0.73(v_cpu_io) v_cpu_io v v il8 input low voltage ? 0.3 hiref ? 0.10 v v ih8 input high voltage hiref + 0.10 1.2 v v il9 input low voltage ? 0.5 0.10 v v ih9 input high voltage 0.40 2.0 v v il10 input low voltage 325 mvp - p6 v ih10 input high voltage 600 mvp-p 6 v il11 input low voltage ? 0.5 0.8 v v ih11 input high voltage 2.0 v5ref_sus + 0.5 v v il12 input low voltage ? 0.5 0.35vcc3_3 v v ih12 input high voltage 0.65vcc3_3 vcc3_3 + 0.3 v v il13 input low voltage ?0.150 0.150 v v ih13 input high voltage 0.660 0.850 v vcross(abs) absolute crossing point 0.250 0.550 7,8 v+ low to high input threshold 1.5 2.0 v 1 v ? high to low input threshold 1.0 1.5 v 1 vhys difference between input thresholds: (v+current value) ? (v ? current value) 320 mv 1 vthravg average of thresholds: ((v+current value) + (v ? current value))/2 1.3 1.7 v 1 vring ac voltage at recipient connector ? 1 6 v 1,2 v di differential input sensitivity 0.2 v 3,5 602 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics notes: 1. applies to ultra dma modes greater than ultra dma mode 4. 2. this is an ac characteristic that represents transient values for these signals. 3. v di = | usbpx[p] ? usbpx[n] 4. includes v di range. 5. applies to high-speed usb 2.0. 6. sata vdiff,rx is measured at the sata connector on the receive side. 7. crossing voltage is defined as the instantaneous voltage value when the rising edge of clk100p equals the falling edge of clk100n. 8. vhavg is the statistical average of the vh measured by the oscilloscope v cm differential common mode range 0.8 2.5 v 4,5 v se single-ended receiver threshold 0.8 2.0 v 5 v hssq hs squelch detection threshold 100 150 mv 5 v hsdsc hs disconnect detection threshold 525 625 mv 5 v hscm hs data signaling common mode voltage range ? 50 500 mv 5 v hssq hs squelch detection threshold 100 150 mv 5 v hsdsc hs disconnect detection threshold 525 625 mv 5 v hscm hs data signaling common mode voltage range ? 50 500 mv 5 table 179. dc input characteristics (sheet 2 of 2) symbol parameter min max unit notes intel ? 82801eb ich5 / 82801er ich5r datasheet 603 electrical characteristics note: 1. these signals are open drain. table 180. dc characteristic output signal association symbol associated signals v oh1 /v ol1 ide signals: pdd[15:0], sdd[15:0], pdiow#/pdstop, sdiow#/sdstop, pdior#/ pdwstb/prdmardy, sdior#/stwstb/srdmardy, pddack#, sddack#, pda[2:0], sda[2:0], pdcs[3,1]#, sdcs[3,1]# v oh2 /v ol2 processor signals: a20m#, cpupwrgd (1) , cpuslp#, ignne#, init#, intr, nmi, smi#, stpclk# v oh3 /v ol3 eeprom signals: ee_cs, ee_dout, ee_shclk v oh4 /v ol4 pci signals: gnt5#/gntb#/gpio17, gnta#/gpio16, ad[31:0], c/be[3:0]#, pcirst#, gnt[4:0]#, par, devsel#, perr#, plock#, stop#, trdy#, irdy#, frame#, serr# (1) lpc/flash bios signals: lad[3:0]/fb[3:0], lframe#/fb4 ac?97 signals: ac_rst#, ac_sdout, ac_sync lan signals: lan_rstsync, lan_txd[2:0] v ol5 /v oh5 smbus signals: smbclk (1) , smbdata (1) system management signals: linkalert#, smlink[1:0] (1) v ol6 /v oh6 power management signals: pme# (1) , slp_s3#, slp_s4#, slp_s5#, sus_stat#, susclk gpio signals: gpio[34, 32, 28:27, 25:22, 21:18] interrupt signals: serirq, pirq[d:a]# (1) , pirq[h:e]#/gpio[5:2] (1) other signals: spkr, sataled# v ol7 /v oh7 usb signals : usbp[7:0][p,n] in low and full speed modes v ol8 /v oh8 zpd/zpu hub interface signals : hi[11:0], hi_stbs, hi_stbf v ol9 /v oh9 sata signals: sata[1:0]tx[p,n] v hsoi v hsoh v hsol v chirpj v chirpk usb signals: usbp[7:0][p:n] in high speed modes 604 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics notes: 1. the cpupwrgd, serr#, pirq[a:h], gpio22, smbdata, smbclk, linkalert#, and smlink[1:0] signal has an open drain driver, and the v oh spec does not apply. this signal must have external pull up resistor. 2. sata vdiff,tx is measured at the sata connector on the transmit side 3. i oh2 = - (v_cpu_io - 0.9) * e-3 table 181. dc output characteristics symbol parameter min max unit i ol / i oh notes v ol1 output low voltage 0.51 v 6 ma v oh1 output high voltage vcc3_3 ? 0.51 v ?6 ma v ol2 output low voltage ? 0.15 .25(v_cpu_io) v 1.5 ma v oh2 output high voltage 0.9(v_cpu_io) v note 3 1 v ol3 output low voltage 0.4 v 6 ma v oh3 output high voltage 2.4 v ?1 ma 1 v ol4 output low voltage 0.1vcc3_3 v 6 ma v oh4 output high voltage 0.9vcc3_3 v ?0.5 ma 1 v ol5 output low voltage 0.4 v 4 ma v oh5 output high voltage n/a v n/a 1 v ol6 output low voltage 0.4 v 4 ma v oh6 output high voltage vcc3_3 ? 0.5 v ?2 ma 1 v ol7 output low voltage 0.4 v 5 ma v oh7 output high voltage vcc3_3 ? 0.5 v ?2 ma v ol8 output low voltage 0.05 v 0.5 ma v oh8 output high voltage 0.750 .850 v ? 12 ma v ol9 output low voltage 400 mvp-p 2 v oh9 output high voltage 600 mvp-p 2 zpd pull down impedance 48 ohm zpu pull up impedance 46 ohm v hsoi hs idle level ? 10.0 10.0 mv v hsoh hs data signaling high 360 440 mv v hsol hs data signaling low ? 10.0 10.0 mv v chirpj chirp j level 700 1100 mv v chirpk chirp k level ? 900 ? 500 mv intel ? 82801eb ich5 / 82801er ich5r datasheet 605 electrical characteristics notes: 1. hiref and hi_vswing are derived from 1.5 v which is the nominal core voltage for the ich5. voltage supply tolerance for a particular interface driver voltage must be within a 5% range of nominal. 2. includes clk14, clk48, clk66, lan_clk and pciclk 3. nominal value of hiref is 0.350 v. the spec is at nominal vcc1_5. note that hiref will vary linearly with vcc1_5, and so vcc1_5 variation ( 5%) must be accounted for in the hiref spec in addition to the 2% variation of hiref in the table. 4. nominal value of hivswing is 0.800 v. the spec is at nominal vcc1_5. note that hivswing will vary linearly with vcc1_5, and so vcc1_5 variation ( 5%) must be accounted for in the hivswing spec in addition to the 2% variation of hivswing in the table. table 182. other dc characteristics symbol parameter min max unit notes v5ref intel ? ich5 core well reference voltage 4.75 5.25 v vcc3_3 i/o buffer voltage 3.135 3.465 v vcc1_5, vccpll internal logic voltage 1.425 1.575 v hiref hub interface reference voltage 0.343 0.357 v note 1, 3 hivswing hub interface voltage swing (input to hi_vswing pin) 0.784 0.816 v note 1,4 v5ref_sus suspend well reference voltage 4.75 5.25 v vccsus3_3 suspend well i/o buffer voltage 3.135 3.465 v vccsus1_5 suspend well logic voltage 1.425 1.575 v vccrtc battery voltage 1.0 3.6 v v it+ hysteresis input rising threshold 1.9 v applied to usbp[7:0][p,n] v it ? hysteresis input falling threshold 1.3 v applied to usbp[7:0]p,n] v di differential input sensitivity 0.2 v |(usbpx+,usbpx ? )| v cm differential common mode range 0.8 2.5 v includes v di v crs output signal crossover voltage 1.3 2.0 v v se single ended rcvr threshold 0.8 2.0 v i li1 ata input leakage current ? 200 200 a (0 v < v in < 5v) i li2 pci_3v hi-z state data line leakage ? 10 10 a (0 v < v in < 3.3v) i li3 pci_5v hi-z state data line leakage ? 70 70 a max v in = 2.7 v min v in = 0.5 v i li4 input leakage current ? clock signals ? 100 +100 a note 2 c in input capacitance ? hub interface input capacitance ? all other 8 12 pf f c = 1 mhz c out output capacitance 12 pf f c = 1 mhz c i/o i/o capacitance 12 pf f c = 1 mhz typical value c l xtal1 6 pf c l xtal2 6 pf 606 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics 19.3 ac characteristics 1 table 183. clock timings (sheet 1 of 2) sym parameter min max unit notes figure pci clock (pciclk) t1 period 30 33.3 ns 3 t2 high time 12 ns 3 t3 low time 12 ns 3 t4 rise time 3 ns 3 t5 fall time 3 ns 3 oscillator clock (osc) t6 period 67 70 ns 3 t7 high time 20 3 t8 low time 20 ns 3 usb clock (usbclk) f clk48 operating frequency 48 mhz 1 t9 frequency tolerance 500 ppm 2 t10 high time 7 ns 3 t11 low time 7 ns 3 t12 rise time 1.2 ns 3 t13 fall time 1.2 ns 3 smbus clock (smbclk) f smb operating frequency 10 16 khz t18 high time 4.0 50 us 3 18 t19 low time 4.7 us 18 t20 rise time 1000 ns 18 t21 fall time 300 ns 18 intel ? 82801eb ich5 / 82801er ich5r datasheet 607 electrical characteristics notes: 1. the usbclk is a 48 mhz that expects a 40/60% duty cycle. 2. usbclk is a pass-thru clock that is not altered by the ich5. this frequency tolerance specification is required for usb 2.0 compliance and is affected by external elements such as the clock generator and the system board. 3. the maximum high time (t18 max) provide a simple guaranteed method for devices to detect bus idle conditions. 4. bitclk rise and fall times are measured from 10%vdd and 90%vdd. 5. this specification includes pin-to-pin skew from the clock generator as well as board skew. 6. susclk duty cycle can range from 30% minimum to 70% maximum. ac?97 clock (bitclk) f ac97 operating frequency 12.288 mhz t26 output jitter 750 ps t27 high time 32.56 48.84 ns 3 t28 low time 32.56 48.84 ns 3 t29 rise time 2.0 6.0 ns 4 3 t30 fall time 2.0 6.0 ns 4 3 hub interface clock f hi operating frequency 66 mhz t31 high time 6.0 ns 3 t32 low time 6.0 ns 3 t33 rise time 0.25 1.2 ns 3 t34 fall time 0.25 1.2 ns 3 t35 clk66 leads pciclk 1.0 4.5 ns 5 sata clock (clk100p, clk100n) t36 period 9.997 10.003 ns t37 rise time 175 700 ps t38 fall time 175 700 ps suspend clock (susclk) f susclk operating frequency 32 khz 6 t39 high time 10 us 6 t39b low time 10 us 6 table 183. clock timings (sheet 2 of 2) sym parameter min max unit notes figure 608 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics notes: 1. refer to pci local bus specification, revision 2.3. table 184. pci interface timing sym parameter min max units notes figure t40 ad[31:0] valid delay 2 11 ns min: 0 pf max: 50 pf note 1 4 t41 ad[31:0] setup time to pciclk rising 7 ns 5 t42 ad[31:0] hold time from pciclk rising 0 ns 5 t43 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, perr#, plock#, devsel# valid delay from pciclk rising 211ns min: 0 pf max: 50 pf 4 t44 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, perr#, plock#, idsel, devsel# output enable delay from pciclk rising 2ns 8 t45 c/be[3:0]#, frame#, trdy#, irdy#, stop#, perr#, plock#, devsel#, gnt[a:b]# float delay from pciclk rising 228ns 6 t46 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, perr#, devsel#, setup time to pciclk rising 7ns 5 t47 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, perr#, devsel#, req[a:b]# hold time from pclkin rising 0ns 5 t48 pcirst# low pulse width 1 ms 7 t49 gnt[a:b}#, gnt[5:0]# valid delay from pciclk rising 2 12 ns t50 req[a:b]#, req[5:0]# setup timer to pciclk rising 12 ns intel ? 82801eb ich5 / 82801er ich5r datasheet 609 electrical characteristics notes: 1. iordy is internally synchronized. this timing is to guarantee recognition on the next clock. 2. piordy sample point from diox# assertion and pdiox# active pulse width is programmable from 2 ? 5 pci clocks when the drive mode is mode 2 or greater. refer to the isp field in the ide timing register. 3. piordy sample point from diox# assertion, pdiox# active pulse width and pdiox# inactive pulse width cycle time is the compatible timing when the drive mode is mode 0/1. refer to the tim0/1 field in the ide timing register. 4. pdiox# inactive pulse width is programmable from 1 ? 4 pci clocks when the drive mode is mode 2 or greater. refer to the rct field in the ide timing register. table 185. ide pio and multiword dma modetiming sym parameter min max units notes figure t60 pdior#/pdiow#/sdior#/sdiow# active from clk66 rising 220ns 9 10 t61 pdior#/pdiow#/sdior#/sdiow# inactive from clk66 rising 220ns 9 10 t62 pda[2:0]/sda[2:0] valid delay from clk66 rising 2 30 ns 9 t63 pdcs1#/sdcs1#, pdcs3#/sdcs3# active from clk66 rising 230ns 9 t64 pdcs1#/sdcs1#, pdcs3#/sdcs3# inactive from clk66 rising 230ns 9 t65 pddack#/sddack# active from clk66 rising 2 20 ns 10 t66 pddack#/sddack# inactive from clk66 rising 2 20 ns t67 pddreq/sddreq setup time to clk66 rising 7 ns 10 t68 pddreq/sddreq hold from clk66 rising 7 ns 10 t69 pdd[15:0]/sdd[15:0] valid delay from clk66 rising 2 30 ns 9 10 t70 pdd[15:0]/sdd[15:0] setup time to clk66 rising 10 ns 9 10 t71 pdd[15:0]/sdd[15:0] hold from clk66 rising 7 ns 9 10 t72 piordy/siordy setup time to clk66 rising 7 ns 1 9 t73 piordy/siordy hold from clk66 rising 7 ns 1 9 t74 piordy/siordy inactive pulse width 48 ns 9 t75 pdior#/pdiow#/sdior#/sdiow# pulse width low 2,3 9 10 t76 pdior#/pdiow#/sdior#/sdiow# pulse width high 3,4 9 10 610 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics table 186. ultra ata timing (mode 0, mode 1, mode 2) (sheet 1 of 2) sym parameter (1) mode 0 (ns) mode 1 (ns) mode 2 (ns) measuring location figure min max min max min max t80 sustained cycle time (t2cyctyp) 240 160 120 sender connector t81 cycle time (tcyc) 112 73 54 end recipient connector 12 t82 two cycle time (t2cyc) 230 153 115 sender connector 12 t83a data setup time (tds) 15 10 7 recipient connector 12 t83b recipient ic data setup time (from data valid until strobe edge) (see note 2) (tdsic) 14.7 9.7 6.8 intel ? ich5 ball t84a data hold time (tdh) 5 5 5 recipient connector 12 t84b recipient ic data hold time (from strobe edge until data may become invalid) (see note 2) (tdhic) 4.8 4.8 4.8 ich5 ball t85a data valid setup time (tdvs) 70 48 31 sender connector 12 t85b sender ic data valid setup time (from data valid until strobe edge) (see note 2) (tdvsic) 72.9 50.9 33.9 ich5 ball t86a data valid hold time (tdvh) 6.2 6.2 6.2 sender connector 12 t86b sender ic data valid hold time (from strobe edge until data may become invalid) (see note 2) (tdvhic) 9 9 9 ich5 ball t87 limited interlock time (tli) 0 150 0 150 0 150 see note 2 14 t88 interlock time w/ minimum (tmli) 20 20 20 host connector 14 t89 envelope time (tenv) 20 70 20 70 20 70 host connector 11 t90 ready to pause time (trp) 160 125 100 recipient connector 13 t91 dmack setup/hold time (tack) 20 20 20 host connector 11 , 14 t92a crc word setup time at host (tcvs) 70 48 31 host connector t92b crc word valid hold time at sender (from dmack# negation until crc may become invalid) (see note 2) (tcvh) 6.2 6.2 6.2 host connector intel ? 82801eb ich5 / 82801er ich5r datasheet 611 electrical characteristics notes: 1. the specification symbols in parentheses correspond to the at attachment ? 6 with packet interface (ata/atapi ? 6) specification name. 2. see the at attachment ? 6 with packet interface (ata/atapi ? 6) specification for further details on measuring these timing parameters. t93 strobe output released-to- driving to the first transition of critical timing (tzfs) 000 device connector 14 t94 data output released-to-driving until the first tunisian of critical timing (tdzfs) 70 48 31 sender connector 11 t95 unlimited interlock time (tui) 0 0 0 host connector 11 t96a maximum time allowed for output drivers to release (from asserted or negated) (taz) 10 10 10 see note 2 t96b minimum time for drivers to assert or negate (from released) (tzad) 000 device connector t97 ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy#) (trfs) 75 70 60 sender connector 11 t98a maximum time before releasing iordy (tiordyz) 20 20 20 device connector t98b minimum time before driving iordy (see note 2) (tziordy) 000 device connector t99 time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) (tss) 50 50 50 sender connector 13 table 186. ultra ata timing (mode 0, mode 1, mode 2) (sheet 2 of 2) sym parameter (1) mode 0 (ns) mode 1 (ns) mode 2 (ns) measuring location figure min max min max min max 612 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics table 187. ultra ata timing (mode 3, mode 4, mode 5) (sheet 1 of 2) sym parameter (1) mode 3 (ns) mode 4 (ns) mode 5 (ns) measuring location figure minmaxminmaxminmax t80 sustained cycle time (t2cyctyp) 90 60 40 sender connector t81 cycle time (tcyc) 39 25 16.8 end recipient connector 12 t82 two cycle time (t2cyc) 86 57 38 sender connector 12 t83 data setup time (tds) 7 5 4.0 recipient connector 12 t83b recipient ic data setup time (from data valid until strobe edge) (see note 2) (tdsic) 6.8 4.8 2.3 intel ? ich5 balls t84 data hold time (tdh) 5 5 4.6 recipient connector 12 t84b recipient ic data hold time (from strobe edge until data may become invalid) (see note 2) (tdhic) 4.8 4.8 2.8 ich5 balls t85 data valid setup time (tdvs) 20 6.7 4.8 sender connector 11 12 t85b sender ic data valid setup time (from data valid until strobe edge) (see note 2) (tdvsic) 22.6 9.5 6.0 ich5 balls t86 data valid hold time (tdvh) 6.2 6.2 4.8 sender connector 11 12 t86b sender ic data valid hold time (from strobe edge until data may become invalid) (see note 2) (tdvhic) 9.0 9.0 6.0 ich5 balls t87 limited interlock time (tli) 0 100 0 100 0 75 see note 2 14 t88 interlock time w/ minimum (tmli) 20 20 20 host connector 14 t89 envelope time (tenv) 20 55 20 55 20 50 host connector 12 t90 ready to pause time (trp) 100 100 85 recipient connector 13 t91 dmack setup/hold time (tack) 20 20 20 host connector 14 t92a crc word setup time at host (tcvs) 20 6.7 10 host connector t92b crc word hold time at sender crc word valid hold time at sender (from dmack# negation until crc may become invalid) (see note 2) (tcvh) 6.2 6.2 10.0 host connector intel ? 82801eb ich5 / 82801er ich5r datasheet 613 electrical characteristics notes: 1. the specification symbols in parentheses correspond to the at attachment ? 6 with packet interface (ata/atapi ? 6) specification name. 2. see the at attachment ? 6 with packet interface (ata/atapi ? 6) specification for further details on measuring these timing parameters. t93 strobe output released-to- driving to the first transition of critical timing (tzfs) 0035 device connector 14 t94 data output released-to- driving until the first transition of critical timing (tdzfs) 20.0 6.7 25 sender connector t95 unlimited interlock time (tui) 0 0 0 host connector t96a maximum time allowed for output drivers to release (from asserted or negated) (taz) 10 10 10 see note 2 t96b drivers to assert or negate (from released) (tzad) 000 device connector t97 ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy#) (trfs) 60 60 50 sender connector t98a maximum time before releasing iordy (tiordyz) 20 20 20 device connector t98b minimum time before driving iordy (see note 2) (tziordy) 000 device connector t99 time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) (tss) 50 50 50 sender connector 13 table 187. ultra ata timing (mode 3, mode 4, mode 5) (sheet 2 of 2) sym parameter (1) mode 3 (ns) mode 4 (ns) mode 5 (ns) measuring location figure minmaxminmaxminmax 614 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics notes: 1. driver output resistance under steady state drive is spec?d at 28 ohms at minimum and 43 ohms at maximum. 2. timing difference between the differential data signals. 3. measured at crossover point of differential data signals. 4. measured at 50% swing point of data signals. 5. measured from last crossover point to 50% swing point of data line at leading edge of eop. 6. measured from 10% to 90% of the data signal. 7. full speed data rate has minimum of 11.97 mbps and maximum of 12.03 mbps. 8. low speed data rate has a minimum of 1.48 mbps and a maximum of 1.52 mbps. table 188. universal serial bus timing sym parameter min max units notes fig full speed source (note 7) t100 usbpx+, usbpx- driver rise time 4 20 ns 1, c l = 50 pf 15 t101 usbpx+, usbpx- driver fall time 4 20 ns 1, c l = 50 pf 15 t102 source differential driver jitter to next transition for paired transitions ? 3.5 ? 4 3.5 4 ns ns 2, 3 16 t103 source se0 interval of eop 160 175 ns 4 17 t104 source jitter for differential transition to se0 transition ? 25 ns 5 t105 receiver data jitter tolerance to next transition for paired transitions ? 18.5 ? 9 18.5 9 ns ns 3 16 t106 eop width: must accept as eop 82 ns 4 17 t107 width of se0 interval during differential transition 14 ns low speed source (note 8) t108 usbpx+, usbpx ? driver rise time 75 300 ns 1, 6 c l = 50 pf c l = 350 pf 15 t109 usbpx+, usbpx ? driver fall time 75 300 ns 1,6 c l = 50 pf c l = 350 pf 15 t110 source differential driver jitter to next transition for paired transitions ? 25 ? 14 25 14 ns ns 2, 3 16 t111 source se0 interval of eop 1.25 1.50 s 4 17 t112 source jitter for differential transition to se0 transition ? 40 100 ns 5 t113 receiver data jitter tolerance to next transition for paired transitions ? 152 ? 200 152 200 ns ns 3 16 t114 eop width: must accept as eop 670 ns 4 17 t115 width of se0 interval during differential transition 210 ns intel ? 82801eb ich5 / 82801er ich5r datasheet 615 electrical characteristics notes: 1. 20% ? 80% at transmitter 2. 80% ? 20% at transmitter 3. as measured from 100mv differential crosspoints of last and first edges of burst. 4. operating data period during out-of-band burst transmissions. notes: 1. a device will timeout when any clock low exceeds this value. 2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. if a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop. 4. t134 has a minimum timing for i2c of 0 ns, while the minimum timing for smbus is 300 ns. table 189. sata interface timings sym parameter min max units notes figure ui operating data period 666.43 670.12 ps rise time 0.2 0.41 ui 1 fall time 0.2 0.41 ui 2 tx differential skew 20 ps comreset 310.4 329.6 ns 3 comwake transmit spacing 103.5 109.9 ns 3 oob operating data period 646.67 686.67 ns 4 table 190. smbus timing sym parameter min max units notes fig t130 bus tree time between stop and start condition 4.7 s 18 t131 hold time after (repeated) start condition. after this period, the first clock is generated. 4.0 s 18 t132 repeated start condition setup time 4.7 s 18 t133 stop condition setup time 4.0 s 18 t134 data hold time 0 ns 4 18 t135 data setup time 250 ns 18 t136 device time out 25 35 ms 1 t137 cumulative clock low extend time (slave device) 25 ms 2 19 t138 cumulative clock low extend time (master device) 10 ms 3 19 616 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics table 191. ac?97 timing sym parameter min max units notes fig t140 acsdin[2:0] setup to falling edge of bitclk 10 ns 24 t141 acsdin[2:0] hold from falling edge of bitclk 10 ns 24 t142 acsync, acsdoutvalid delay from rising edge of bitclk 15 ns 24 table 192. lpc timing sym parameter min max units notes fig t150 lad[3:0] valid delay from pciclk rising 2 11 ns 4 t151 lad[3:0] output enable delay from pciclk rising 2 ns 8 t152 lad[3:0] float delay from pciclk rising 28 ns 6 t153 lad[3:0] setup time to pciclk rising 7 ns 5 t154 lad[3:0] hold time from pciclk rising 0 ns 5 t155 ldrq[1:0]# setup time to pciclk rising 12 ns 5 t156 ldrq[1:0]# hold time from pciclk rising 0 ns 5 t157 lframe# valid delay from pciclk rising 2 12 ns 4 table 193. miscellaneous timings sym parameter min max units notes fig t160 serirq setup time to pciclk rising 7 ns 5 t161 serirq hold time from pciclk rising 0 ns 5 t162 ri#, extsmi#, gpi, usb resume pulse width 2 rtcclk 7 t163 spkr valid delay from osc rising 200 ns 4 t164 serr# active to nmi active 200 ns t165 ignne# inactive from ferr# inactive 230 ns intel ? 82801eb ich5 / 82801er ich5r datasheet 617 electrical characteristics notes: 1. the v5ref supply must power up before or simultaneous with its associated 3.3 v supply, and must power down simultaneous with or after the 3.3 v supply. see section 2.21.3.1 for details. 2. the associated 3.3 v and 1.5 v supplies are assumed to power up or down ?together?. vccsus3_3 must ramp up with or before vccsus1_5_x and vccsus3_3 must power down after vccsus1_5. 3. the vccsus supplies must never be active while the vccrtc supply is inactive. likewise, the vcc supplies must never be active while the vccsus supplies are inactive. 4. sysreset# is not checked for triggering t177. table 194. power sequencing and reset signal timings sym parameter min max units notes fig t170 vccrtc active to rtcrst# inactive 5 ? ms 20 t171 v5refsus active to vccsus3_3, vccsus1_5_x active 0 ? ms 1, 2 20 t172 vccrtc supply active to vccsus supplies active 0 ? ms 3 20 t173 vccsus supplies active to lan_rst# active, rsmrst# inactive 10 ? ms 20 21 t174 v5ref active to vcc3_3, vcc1_5 active 0 ? ms 1, 2 20 t175 vccsus supplies active to vcc supplies active 0 ? ms 3 20 t176 vcc supplies active to pwrok, vrmpwrgd active 99 ? ms 20 21 23 t177 pwrok and vrmpwrgd active to sus_stat# inactive and frequency straps at appropriate value 32 38 rtcclk 4 21 23 t178 sus_stat# inactive to pcirst# inactive 2 3 rtcclk 21 23 t179 ac_rst# active low pulse width 1 us t180 ac_rst# inactive to ac_bit_clk startup delay 162.8 ns 618 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics notes: 1. these transitions are clocked off the internal rtc. 1 rtc clock is approximately 32 s. 2. this transition is clocked off the 66 mhz clk66. 1 clk66 is approximately 15 ns. 3. the ich5 stpclk# assertion will trigger the processor to send a stop grant acknowledge cycle. the timing for this cycle getting to the ich5 is dependant on the processor and the memory controller. 4. these transitions are clocked off the 33 mhz pciclk. 1 pciclk is approximately 30ns. 5. the ich5 has no maximum timing requirement for this transition. it is up to the system designer to determine if the slp_s3#, slp_s4# and slp_s5# signals are used to control the power planes. 6. if the transition to s5 is due to power button override, slp_s3#, slp_s4# and slp_s5# are asserted together similar to timing t194 (pcirst# active to slp_s3# active). 7. if there is no rtc battery in the system, so vccrtc and the vccsus supplies come up together, the delay from rtcrst# and rsmrst# inactive to susclk toggling may be as much as 2.5 s. 8. this value is programmable in multiples of 1024 pci clks. maximum is 8192 pci clks (245.6 s). 9. for timing t198d, the min/max times depend on the programming of the ?slp_s4# minimum assertion width? and the ?slp_s4# assertion stretch enable bits (d31:f0:a4h bits 5:3). table 195. power management timings sym parameter min max units notes fig t181 vccsus active to slp_s5#, sus_stat# and pcirst# active 50 ns 21 t182 t183 rsmrst# inactive to susclk running, slp_s5# inactive 110 ms 7 21 t183a slps5# inactive to slp_s4# inactive 1 2 rtcclk 21 t183b slps4# inactive to slp_s3# inactive 1 2 rtcclk 21 t184 vcc active to stpclk# and cpuslp# inactive, and processor frequency strap signals high 50 ns 21 23 t185 pwrok and vrmpwrgd active and sys_reset# inactive to sus_stat# inactive and processor frequency straps latched to strap values 32 38 rtcclk 1 21 t186 processor reset complete to frequency strap signals unlatched from strap values 79clk662 21 t187 stpclk# active to stop grant cycle n/a n/a 3 22 t188 stop grant cycle to cpuslp# active 60 63 pciclk 4 22 23 t189 s1 wake event to cpuslp# inactive 1 25 pciclk 4 22 t190 cpuslp# inactive to stpclk# inactive 3.87 245 s 22 t192 cpuslp# active to sus_stat# active 2 4 rtcclk 1 23 t193 sus_stat# active to pcirst# active 9 21 rtcclk 1 t194 pcirst# active to slp_s3# active 1 2 rtcclk 1 23 t194a slp_s3# active to slp_s4# active 1 2 rtcclk 1 23 t195 slp_s4# active to slp_s5# active 1 2 rtcclk 1, 6 23 t196 slp_s3# active to pwrok, vrmpwrgd inactive 0 ms 5 23 t197 pwrok, vrmpwrgd inactive to vcc supplies inactive 20 ns 23 t198 wake event to slp_s5# inactive 1 10 rtcclk 1 t198a wake event to slp_s4# inactive(s4 wake) 1 10 rtcclk 1 t198b s3 wake event to slp_s3# inactive(s3 wake) 0 2 rtcclk 1 t198d slp_s5# inactive or s4 wake event to slp_s4# inactive see note below 9 23 t198e slp_s4# inactive to slp_s3# inactive 1 2 rtcclk 1 23 t220 thrmtrip# active to slp_s3#, slp_s4#, slp_s5# active 3 pci clk intel ? 82801eb ich5 / 82801er ich5r datasheet 619 electrical characteristics 19.4 timing diagrams figure 3. clock timing figure 4. valid delay from rising clock edge figure 5. setup and hold times 2.0v 0.8v period high time low time fall time rise time clock 1.5v valid delay vt output clock vt input hold time setup time vt 1.5v 620 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics figure 6. float delay figure 7. pulse width figure 8. output enable delay input vt output float delay vt pulse width vt clock output output enable delay vt 1.5v intel ? 82801eb ich5 / 82801er ich5r datasheet 621 electrical characteristics figure 9. ide pio mode figure 10. ide multiword dma t62,t63 t64 da[2:0], cs1#, cs3# t75 t69 t69 t70 t71 t72 t73 t61 read data clk66 diox# dd[15:0] write dd[15:0] read iordy t60 t76 write data sample point t74 clk66 t67 ddreq[1:0] ddack[1:0] t65 diox# dd[15:0] read dd[15:0] write t60 t61 t75 t76 t70 t71 t69 t69 read data write data write data read data t68 622 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics figure 11. ultra ata mode (drive initiating a burst read) figure 12. ultra ata mode (sustained burst) dmarq (drive) t91 t89 t89 dmack# (host) stop (host) dmardy# (host) strobe (drive) dd[15:0] da[2:0], cs[1:0] t96 t98 t94 t95 t85 t86 t97 t99b strobe @ sender t81 data @ sender t86 t85 t86 t85 t81 t82 t86 strobe @ receiver data @ receiver t84 t83 t84 t83 t84 t99e t99e t99e t99d t99d t99g t99g t99g t99f t99f intel ? 82801eb ich5 / 82801er ich5r datasheet 623 electrical characteristics figure 13. ultra ata mode (pausing a dma burst) figure 14. ultra ata mode (terminating a dma burst) figure 15. usb rise and fall times t90 strobe data s top (host) dmardy# t99 t88 stop (host) strobe (host) dmardy# (drive) data (host) dmack# (host) t87 dmarq (drive) crc t99c t87 t 9 t 9 t92 t93 differential data lines 90% 10% 10% 90% tr tf rise time fall time c l c l low speed: 75 ns at c l = 50 pf, 300 ns at c l = 350 pf full speed: 4 to 20 ns at c l = 50 pf high speed: 0.8 to 1.2 ns at c l = 10 pf 624 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics figure 16. usb jitter figure 17. usb eop width figure 18. smbus transaction paired transitions consecutive transitions crossover points t period differential data lines jitter differential data lines eop width data crossover level tperiod t130 smbclk smbdata t131 t19 t134 t20 t21 t135 t132 t18 t133 intel ? 82801eb ich5 / 82801er ich5r datasheet 625 electrical characteristics figure 19. smbus timeout figure 20. power sequencing and reset signal timings start stop t137 clk ack clk ack t138 t138 smbclk smbdata vccrtc v5ref vcc3_3, vcc1_5, v_cpu_io vccsus3_3, vccsus1_5 v5refsus rtcrst# rsmrst#, lan_rst# pw rok, vrmpwrgd t170 t171 t172 t173 t174 t175 t176 626 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics figure 21. g3 (mechanical off) to s0 timings figure 22. s0 to s1 to s0 timing vccsus running susclk slp_s3# vcc pw rok, vrmpw rgd sus_stat# pcirst# frequency straps stpclk#, cpuslp# strap values norm al operation hub interface "cpu reset complete" m essage rsmrst#, lan_rst# t173 t176 t177 t178 t181 t181 t182 t184 t185 t186 g3 s 3 s 0 s0 state g 3 s 5 system state s4 slp_s4# slp_s5# t183 t183a t183b t187 t188 t189 t190 s0 s0 s1 s1 s1 s0 s0 state stpclk# pci stop grant cycle cpuslp# wake event intel ? 82801eb ich5 / 82801er ich5r datasheet 627 electrical characteristics note: t198d - refer to table 195 note #9 for slp_s4# assertion width timing details. figure 23. s0 to s5 to s0 timings figure 24. ac?97 data input and output timings stpclk# stop grant cycle cpuslp# sus_stat# pcirst# slp_s3# slp_s5# wake event pw rok, vrmpw rgd vcc s0 s 0 s 3 s3 s5 s0 t188 t192 t193 t194 t196 t197 t176 t177 t178 t184 t187 slp_s4# t194a t195 t198d t198e s4 s4 s3 s 3 /s 4 /s 5 s 0 v oh v ol ac_sdout ac_sdin[2:0] ac_sync ac_bit_clk v i h v i l tco t hold t setup 628 intel ? 82801eb ich5 / 82801er ich5r datasheet electrical characteristics this page is intentionally left blank. intel ? 82801eb ich5 / 82801er ich5r datasheet 629 package information package information 20 the ich5 package information is shown in figure 25 and figure 26 . figure 25. intel ? ich5 package (top and side views) pin a1 identifier pin a1 corner 31.00 0.10 26.00 0.20 top view 45 chamfer (4 places) 16.96 ref 0.127 a -a- -b- 0.127 a 22.10 ref 26.00 0.20 31.00 0.10 3 x ? 1.00 thru 0.61 0.06 side view seating plane (see note 3) -c- 30 0.60 0.10 1.17 0.05 2.38 0.21 0.20 0.15 c notes: 1. all dimensions are in millimeters. 2. all dimensions and tolerances conform to ansi y14.5m - 1982. 3. primary datum (-c-) and seating plane are defined by the sperical crowns of the solder balls. 630 intel ? 82801eb ich5 / 82801er ich5r datasheet package information figure 26. intel ? ich5 package (bottom view) 0.8950 pin a1 corner bottom view a b c d e f g h j k l p r t u v y ab aa n w m notes: 1. all dimensions are in millimeters. 2. all dimensions and tolerances conform to ansi y14.5m - 1982. 3. dimension is measured at the maximum solder ball diameter. parallel to datum (-c-) on side view illustration. 1.27 0.90 ? 0.60 note 3 s b s a c s ? 0.30 1.27 ac ad 2 10 16 20 22 3 5 7 9 11 13 15 17 19 1 21 4 6 18 8 12 14 23 24 0.8950 0.8950 intel ? 82801eb ich5 / 82801er ich5r datasheet 631 testability testability 21 21.1 test mode description the ich5 supports two types of test modes, a tri-state test mode and a xor chain test mode. driving rtcrst# low for a specific number of pci clocks while pwrok is high will activate a particular test mode as described in table 196 . note: rtcrst# can be driven low any time after pcirst# is inactive. . figure 27 illustrates the entry into a test mode. a particular test mode is entered upon the rising edge of the rtcrst# after being asserted for a specific number of pci clocks while pwrok is active. to change test modes, the same sequence should be followed again. to restore the ich5 to normal operation, execute the sequence with rtcrst# being asserted so that no test mode is selected as specified in table 196 . table 196. test mode selection number of pci clocks rtcrst# driven low after pwrok active test mode <4 no test mode selected 4 xor chain 1 5 xor chain 2 6 xor chain 3 7 xor chain 4 8all ?z? 9 ? 42 reserved. do not attempt 43 ? 51 no test mode selected 52 xor chain 6 53 xor chain 4 bandgap >53 no test mode selected figure 27. test mode entry (xor chain example) rsmrst# pwrok rtcrst# other signal outputs n number of pci clocks test mode entered all output signals tri-stated xor chain output enabled 632 intel ? 82801eb ich5 / 82801er ich5r datasheet testability 21.2 tri-state mode when in the tri-state mode, all outputs and bi-directional pin are tri-stated, including the xor chain outputs. 21.3 xor chain mode in the ich5, provisions for automated test equipment (ate) board level testing are implemented with xor chains. the ich5 signals are grouped into four independent xor chains which are enabled individually. when an xor chain is enabled, all output and bi-directional buffers within that chain are tri-stated, except for the xor chain output. every signal in the enabled xor chain (except for the xor chain?s output) functions as an input. all output and bi-directional buffers for pins not in the selected xor chain are tri-stated. figure 28 is a schematic example of xor chain circuitry. 21.3.1 xor chain testability algorithm example xor chain testing allows motherboard manufacturers to check component connectivity (e.g., opens and shorts to vcc or gnd). an example algorithm to do this is shown in table 197 . in this example, vector 1 applies all 0s to the chain inputs. the outputs being non-inverting will consistently produce a 1 at the xor output on a good board. one short to vcc (or open floating to vcc) will result in a 0 at the chain output, signaling a defect. likewise, applying vector 7 (all 1s) to the chain inputs (given that there are an even number of input signals in the chain), will consistently produce a 1 at the xor chain output on a good board. one short to vss (or open floating to vss) will result in a 0 at the chain output, signaling a defect. figure 28. example xor chain circuitry input pin 2 vcc input pin 1 input pin 3 input pin 4 input pin 5 input pin 6 xor chain output table 197. xor test pattern example vector input pin 1 input pin 2 input pin 3 input pin 4 input pin 5 input pin 6 xor output 1000000 1 2100000 0 3110000 1 4111000 0 5111100 1 6111110 0 7111111 1 intel ? 82801eb ich5 / 82801er ich5r datasheet 633 testability it is important to note that the number of inputs pulled to 1 will affect the expected chain output value. if the number of chain inputs pulled to 1 is even, then expect 1 at the output. if the number of chain inputs pulled to 1 is odd, expect 0 at the output. continuing with the example in table 197 , as the input pins are driven to 1 across the chain in sequence, the xor output will toggle between 0 and 1. any break in the toggling sequence (e.g., ?1011?) will identify the location of the short or open. table 198. xor chain #1 (rtcrst# asserted for 4 pci clocks while pwrok active) pin name ball # notes pin name ball # notes ac_bit_clk d8 top of xor chain ad15 g5 ac_sync b8 2nd signal in xor gnt0# d4 ac_sdout a9 ad22 c4 pirqe#/gpio2 d7 ad30 f4 gnt2# b7 ad20 h3 req3 b6 ad16 g4 gnt3# c7 ad4 h5 gnta#/gpio16 e8 ad24 e6 reqb#/req5#/ gpio1 e7 ad0 j4 req4# c6 stop# e5 reqa#/gpio0 a5 ad11 h4 pirqf#/gpio3 a6 ad26 d3 gnt4# a4 ad6 j3 gntb#/ gnt5#gpio17 b4 trdy# e4 gnt1# a3 frame# d2 pirqc# a2 ad9 f2 pirqa# b3 ad2 g3 pirqh#/gpio5 b1 par f1 pirqd# c2 ad5 h2 req1# c1 ad13 g2 req2# c5 ad1 j5 ad18 b2 serr# l4 req0# d5 c/be0# e3 pirqg#/gpio4 e2 c/be1# j1 ad28 f5 ad3 k4 pirqb# e1 ad10 m4 xor chain #1 tp0 ab2 output 634 intel ? 82801eb ich5 / 82801er ich5r datasheet testability table 199. xor chain #2 (rtcrst# asserted for 5 pci clocks while pwrok active) pin name ball # notes pin name ball # notes ad7 j2 top of xor chain lad3/fwh3 u4 ad8 k5 2nd signal in xor ldrq1# r2 irdy# m3 lframe# / fwh4 t4 perr# k2 gpio32 t1 ad14 k1 thrm# t2 ad12 l5 clk100n ad5 ad23 n4 clk100p ac5 c/be2# n3 sata0rxn ad7 devsel# l3 sata0rxp ac7 plock# l2 sata0txn ab8 ad17 l1 sata0txp aa8 ad19 p5 sata1rxn ad9 ad21 n5 sata1rxp ac9 c/be3# m2 sata1txn ab10 ad25 p3 sata1txp aa10 ad27 n2 satarbiasn y9 ad29 p4 satarbiasp y11 ad31 p2 gpio8 y2 gpio6 r5 ri# ab3 pciclk n1 pwrbtn# y4 gpio7 u3 slp_s5# aa3 lad0/fwh0 t5 tp0 ab2 lad1/fwh1 r4 ac_sdin0 e12 gpio21 r1 ac_sdin2 a13 ldrq0# u5 ac_sdin1 d12 lad2/fwh2 r3 xor chain #2 gpio0 / reqa# a5 output intel ? 82801eb ich5 / 82801er ich5r datasheet 635 testability table 200. xor chain #3 (rtcrst# asserted for 6 pci clocks while pwrok active) pin name ball # notes pin name ball # notes pdd6 ad14 top of xor chain pdcs3# y18 pdd4 aa14 2nd signal in xor irq15 y24 pdd7 ab14 gpio19 t20 pdd11 aa15 gpio18 u21 pdd5 ac15 gpio22 u20 pdd8 ad15 gpio20 u22 pdd9 y15 vrmpwrgd r20 pdd13 y16 a20gate t22 pdd2 y14 rcin# p23 pdd3 ac14 tp1 p20 pdd10 ad16 thrmtrip# t21 pddreq ac17 a20m# v23 pdd12 ac16 cpupwrgd p24 pdd14 aa16 intr u23 pdd1 y13 nmi r22 pdd15 ab17 init# r23 pdd0 ab16 stpclk# t24 pdior# ad18 cpuslp# p22 piordy aa18 tp2 r24 pddack# ac18 hi_stb/ hi_stbs j24 pdiow# aa17 gpio23 f22 irq14 y17 sataled# g23 pda1 ad19 gpio34 f21 pda0 aa19 intvrmen ad10 pdcs1# ab19 intruder y12 pda2 ac19 rtc_rst# aa12 xor chain #3 ri# ab3 output 636 intel ? 82801eb ich5 / 82801er ich5r datasheet testability 2 table 201. xor chain #4-1 (rtcrst# asserted for 7 pci clocks while pwrok active) pin name ball # notes pin name ball # notes sdd7 ac20 top of xor chain sdcs3# v20 sdd9 ad22 2nd signal in xor sda0 w22 sdd5 ac21 ferr# u24 sdd8 y19 ignne# r21 sdd3 ad24 smi# v24 sdd6 ab20 clk66 n22 sdd10 ac22 hi6 n21 sdd12 ab22 hi5 m21 sdd11 aa20 hi7 m20 sdd1 ab23 hi4 m23 sdd4 ab21 hicomp n24 sdd13 ac24 hi_stb#/ hi_stbf k23 sddreq y20 hi3 h23 sdd14 ab24 hi2 j20 sddack# w20 hi1 h21 siordy y21 hi0 h20 sda1 w23 hi10 k21 sdd15 aa23 hi8 l22 sdd2 ad23 hi9 j22 sda2 w21 hi11 g22 sdiow# y22 serirq f23 sdd0 aa22 clk14 f20 sdcs1# v22 spkr e24 sdior# y23 clk48 f24 xor chain #4-1 gpio8 y2 output intel ? 82801eb ich5 / 82801er ich5r datasheet 637 testability 2 table 202. xor chain #4-2 (rtcrst# asserted for 7 pci clocks while pwrok active) pin name ball # notes pin name ball # notes pme# v2 top of xor chain usbp0p c23 gpio25 w3 2nd signal in xor usbp0n d23 gpio12 w4 usbp1p a22 gpio27 v3 usbp1n b22 pcirst# v4 usbp2p c21 gpio13 w5 usbp2n d21 gpio28 w2 usbp3p a20 slp_s4# u2 usbp3n b20 sys_reset# u1 usbp4p c19 smlink1 aa2 usbp4n d19 gpio24 ac1 usbp5p a18 susclk y1 usbp5n b18 sus_stat#/ lpcpd# ab1 usbp6p c17 smlink0 ad3 usbp6n d17 slp_s3# w1 usbp7p a16 smbdata ad1 usbp7n b16 smbclk ad2 ee_shclk a12 smbalert#/ gpio11 ac3 lan_txd2 b12 linkalert# v5 lan_clk e10 oc0# c15 ee_din b11 oc2# d14 lan_rxd2 c11 oc5# a14 lan_rstsync d10 oc1# d15 ee_cs b10 oc3# c14 lan_txd0 d9 oc4# b14 lan_rxd0 c10 oc6# b13 no connect a11 oc7# c13 lan_txd1 e9 ee_dout b9 lan_rxd1 c9 xor chain #4-2 ac_sdin1 d12 output table 203. xor chain #6 (rtcrst# asserted for 52 pci clocks while pwrok active) pin name ball # notes pin name ball # notes rtcx1 ac11 top of xor chain xor chain #6 tp0 ab2 output 638 intel ? 82801eb ich5 / 82801er ich5r datasheet testability 2 this page is intentionally left blank. intel ? 82801eb ich5 / 82801er ich5r datasheet 639 register index register index a table 204. intel ? ich5 pci configuration registers (sheet 1 of 11) register name offset datasheet section and location lan controller (b1:d8:f0) vendor identification 00 ? 01h section 7.1.1, ?vid?vendor identification register (lan controller?b1:d8:f0)? on page 276 device identification 02 ? 03h section 7.1.2, ?did?device identification register (lan controller?b1:d8:f0)? on page 276 pci command 04 ? 05h section 7.1.3, ?pcicmd?pci command register (lan controller?b1:d8:f0)? on page 277 pci device status 06 ? 07h section 7.1.4, ?pcists?pci status register (lan controller? b1:d8:f0)? on page 278 revision identification 08h section 7.1.5, ?rid?revision identification register (lan controller?b1:d8:f0)? on page 279 programming interface 09h sub class code 0ah section 7.1.6, ?scc?sub-class code register (lan controller?b1:d8:f0)? on page 279 base class code 0bh section 7.1.7, ?bcc?base-class code register (lan controller?b1:d8:f0)? on page 279 cache line size 0ch section 7.1.8, ?cls?cache line size register (lan controller?b1:d8:f0)? on page 280 master latency timer 0dh section 7.1.9, ?pmlt?primary master latency timer register (lan controller?b1:d8:f0)? on page 280 header type 0eh section 7.1.10, ?headtyp?header type register (lan controller?b1:d8:f0)? on page 280 csr memory-mapped base address 10 ? 13h section 7.1.11, ?csr_mem_base ? csr memory-mapped base address register (lan controller?b1:d8:f0)? on page 281 csr i/o-mapped base address 14 ? 17h section 7.1.12, ?csr_io_base ? csr i/o-mapped base address register (lan controller?b1:d8:f0)? on page 281 subsystem vendor id 2c ? 2dh section 7.1.13, ?svid ? subsystem vendor identification register (lan controller?b1:d8:f0)? on page 281 subsystem id 2e ? 2fh section 7.1.14, ?sid ? subsystem identification register (lan controller?b1:d8:f0)? on page 282 capabilities pointer 34h section 7.1.15, ?cap_ptr ? capabilities pointer register (lan controller?b1:d8:f0)? on page 282 interrupt line register 3ch section 7.1.16, ?int_ln ? interrupt line register (lan controller?b1:d8:f0)? on page 282 interrupt pin register 3dh section 7.1.17, ?int_pn ? interrupt pin register (lan controller?b1:d8:f0)? on page 283 minimum grant register 3eh section 7.1.18, ?min_gnt ? minimum grant register (lan controller?b1:d8:f0)? on page 283 maximum latency register 3fh section 7.1.19, ?max_lat ? maximum latency register (lan controller?b1:d8:f0)? on page 283 640 intel ? 82801eb ich5 / 82801er ich5r datasheet register index capability id register dch section 7.1.20, ?cap_id ? capability identification register (lan controller?b1:d8:f0)? on page 283 next item pointer ddh section 7.1.21, ?nxt_ptr ? next item pointer register (lan controller?b1:d8:f0)? on page 284 power management capabilities de ? dfh section 7.1.22, ?pm_cap ? power management capabilities register (lan controller?b1:d8:f0)? on page 284 power management control/status register e0 ? e1h section 7.1.23, ?pmcsr ? power management control/status register (lan controller?b1:d8:f0)? on page 285 data register e3h section 7.1.24, ?pcidata ? pci power management data register (lan controller?b1:d8:f0)? on page 286 hub interface to pci bridge d30:f0 vendor id 00 ? 01h section 8.1.1, ?vid?vendor identification register (hub-pci? d30:f0)? on page 302 device id 02 ? 03h section 8.1.2, ?did?device identification register (hub-pci? d30:f0)? on page 302 pci device command register 04 ? 05h section 8.1.3, ?pcicmd?pci command register (hub-pci? d30:f0)? on page 303 pci device status register 06 ? 07h section 8.1.4, ?pcists?pci status register (hub-pci? d30:f0)? on page 304 revision id 08h section 8.1.6, ?scc?sub-class code register (hub-pci? d30:f0)? on page 305 sub class code 0ah section 8.1.6, ?scc?sub-class code register (hub-pci? d30:f0)? on page 305 base class code 0bh section 8.1.7, ?bcc?base-class code register (hub-pci? d30:f0)? on page 305 primary master latency timer 0dh section 8.1.8, ?pmlt?primary master latency timer register (hub-pci?d30:f0)? on page 305 header type 0eh section 8.1.9, ?headtyp?header type register (hub-pci? d30:f0)? on page 306 primary bus number 18h section 8.1.10, ?pbus_num?primary bus number register (hub-pci?d30:f0)? on page 306 secondary bus number 19h section 8.1.11, ?sbus_num?secondary bus number register (hub-pci?d30:f0)? on page 306 subordinate bus number 1ah section 8.1.12, ?sub_bus_num?subordinate bus number register (hub-pci?d30:f0)? on page 306 secondary master latency timer 1bh section 8.1.13, ?smlt?secondary master latency timer register (hub-pci?d30:f0)? on page 307 io base register 1ch section 8.1.14, ?iobase?i/o base register (hub-pci? d30:f0)? on page 307 io limit register 1dh section 8.1.15, ?iolim?i/o limit register (hub-pci?d30:f0)? on page 307 secondary status register 1e ? 1fh section 8.1.16, ?secsts?secondary status register (hub- pci?d30:f0)? on page 308 memory base 20 ? 21h section 8.1.17, ?membase?memory base register (hub- pci?d30:f0)? on page 309 memory limit 22 ? 23h section 8.1.18, ?memlim?memory limit register (hub-pci? d30:f0)? on page 309 prefetchable memory base 24 ? 25h section 8.1.19, ?pref_mem_base?prefetchable memory base register (hub-pci?d30:f0)? on page 309 table 204. intel ? ich5 pci configuration registers (sheet 2 of 11) register name offset datasheet section and location intel ? 82801eb ich5 / 82801er ich5r datasheet 641 register index prefetchable memory limit 26 ? 27h section 8.1.20, ?pref_mem_mlt?prefetchable memory limit register (hub-pci?d30:f0)? on page 310 i/o base upper 16 bits 30 ? 31h section 8.1.21, ?iobase_hi?i/o base upper 16 bits register (hub-pci?d30:f0)? on page 310 i/o limit upper 16 bits 32 ? 33h section 8.1.22, ?iolim_hi?i/o limit upper 16 bits register (hub-pci?d30:f0)? on page 310 interrupt line 3ch section 8.1.23, ?int_ln?interrupt line register (hub-pci? d30:f0)? on page 310 bridge control 3e ? 3fh section 8.1.24, ?bridge_cnt?bridge control register (hub- pci?d30:f0)? on page 311 hub interface 1 command control 40 ? 43h section 8.1.25, ?hi1_cmd?hub interface 1 command control register (hub-pci?d30:f0)? on page 312 secondary pci device hiding 44 ? 45h section 8.1.26, ?device_hide?secondary pci device hiding register (hub-pci?d30:f0)? on page 313 policy configuration register 50 ? 53h section 8.1.27, ?cnf?policy configuration register (hub- pci?d30:f0)? on page 314 multi-transaction timer 70h section 8.1.28, ?mtt?multi-transaction timer register (hub- pci?d30:f0)? on page 315 pci master status 82h section 8.1.29, ?pci_mast_sts?pci master status register (hub-pci?d30:f0)? on page 315 error command register 90h section 8.1.30, ?err_cmd?error command register (hub- pci?d30:f0)? on page 316 error status register 92h section 8.1.31, ?err_sts?error status register (hub-pci? d30:f0)? on page 316 lpc bridge d31:f0 vendor id 00 ? 01h section 9.1.1, ?vid?vendor identification register (lpc i/f? d31:f0)? on page 318 device id 02 ? 03h section 9.1.2, ?did?device identification register (lpc i/f? d31:f0)? on page 318 pci command register 04 ? 05h section 9.1.3, ?pcicmd?pci command register (lpc i/f? d31:f0)? on page 319 pci device status register 06 ? 07h section 9.1.4, ?pcists?pci status register (lpc i/f? d31:f0)? on page 320 revision id 08h section 9.1.6, ?pi?programming interface register (lpc i/f? d31:f0)? on page 321 programming interface 09h section 9.1.6, ?pi?programming interface register (lpc i/f? d31:f0)? on page 321 sub class code 0ah section 9.1.7, ?scc?sub class code register (lpc i/f? d31:f0)? on page 321 base class code 0bh section 9.1.8, ?bcc?base class code register (lpc i/f? d31:f0)? on page 321 header type 0eh section 9.1.9, ?headtyp?header type register (lpc i/f? d31:f0)? on page 322 acpi base address register 40 ? 43h section 9.1.10, ?pmbase?acpi base address register (lpc i/f?d31:f0)? on page 322 acpi control 44h section 9.1.11, ?acpi_cntl?acpi control register (lpc i/f ? d31:f0)? on page 323 bios control register 4e ? 4fh section 9.1.13, ?tco_cntl ? tco control register (lpc i/f ? d31:f0)? on page 324 table 204. intel ? ich5 pci configuration registers (sheet 3 of 11) register name offset datasheet section and location 642 intel ? 82801eb ich5 / 82801er ich5r datasheet register index tco control 54h section 9.1.13, ?tco_cntl ? tco control register (lpc i/f ? d31:f0)? on page 324 gpio base address register 58 ? 5bh section 9.1.14, ?gpio_base?gpio base address register (lpc i/f?d31:f0)? on page 325 gpio control register 5ch section 9.1.15, ?gpio_cntl?gpio control register (lpc i/ f?d31:f0)? on page 325 pirq[a:d] routing control 60 ? 63h section 9.1.16, ?pirq[n]_rout?pirq[a,b,c,d] routing control register (lpc i/f?d31:f0)? on page 326 serial irq control register 64h section 9.1.17, ?sirq_cntl?serial irq control register (lpc i/f?d31:f0)? on page 327 pirq[e:h] routing control 68 ? 6bh section 9.1.8, ?bcc?base class code register (lpc i/f? d31:f0)? on page 321 device 31 error config register 88h section 9.1.19, ?d31_err_cfg?device 31 error configuration register (lpc i/f?d31:f0)? on page 328 device 31 error status register 8ah section 9.1.20, ?d31_err_sts?device 31 error status register (lpc i/f?d31:f0)? on page 329 pci dma configuration registers 90 ? 91h section 9.1.21, ?pci_dma_cfg?pci dma configuration register (lpc i/f?d31:f0)? on page 329 general power management configuration 1 a0h section 9.8.1, ?gen_pmcon_1?general pm configuration 1 register (pm?d31:f0)? on page 377 general power management configuration 2 a2h section 9.8.2, ?gen_pmcon_2?general pm configuration 2 register (pm?d31:f0)? on page 378 general power management configuration 3 a4h section 9.8.3, ?gen_pmcon_3?general pm configuration 3 register (pm?d31:f0)? on page 379 stop clock delay register a8h section 9.8.4, ?stpclk_del?stop clock delay register (pm?d31:f0)? on page 380 gpi_rout b8 ? bbh section 9.8.7, ?gpi_rout?gpi routing control register (pm?d31:f0)? on page 381 i/o monitor trap forwarding enable register c0h section 9.8.8, ?trp_fwd_en?io monitor trap forwarding enable register (pm?d31:f0)? on page 382 i/o monitor [4:7] trap range registers c4h, c6h, c8h, cah section 9.8.9, ?mon[n]_trp_rng?i/o monitor [4:7] trap range register for devices 4?7 (pm?d31:f0)? on page 383 i/o monitor [4:7] trap mask register cch section 9.8.10, ?mon_trp_msk?i/o monitor trap range mask register for devices 4?7 (pm?d31:f0)? on page 383 general control d0h ? d3h section 9.1.22, ?gen_cntl ? general control register (lpc i/f ? d31:f0)? on page 330 general status d4h section 9.1.23, ?gen_sta?general status register (lpc i/f? d31:f0)? on page 332 backed up control d5h section 9.1.24, ?back_cntl?backed up control register (lpc i/f?d31:f0)? on page 333 real time clock configuration d8h section 9.1.25, ?rtc_conf?real time clock configuration register (lpc i/f?d31:f0)? on page 334 lpc com port decode ranges e0h section 9.1.26, ?com_dec?lpc i/f communication port decode ranges register (lpc i/f?d31:f0)? on page 335 lpc fdd & lpt decode ranges e1h section 9.1.27, ?lpcfdd_dec?lpc i/f fdd and lpt decode ranges register (lpc i/f?d31:f0)? on page 335 table 204. intel ? ich5 pci configuration registers (sheet 4 of 11) register name offset datasheet section and location intel ? 82801eb ich5 / 82801er ich5r datasheet 643 register index flash bios decode enable 1 register e3h section 9.1.28, ?fb_dec_en1?flash bios decode enable 1 register (lpc i/f?d31:f0)? on page 336 lpc generic decode range 1 e4h ? e5h section 9.1.29, ?gen1_dec?lpc i/f generic decode range 1 register (lpc i/f?d31:f0)? on page 337 lpc enables e6h ? e7h section 9.1.30, ?lpc_en?lpc i/f enables register (lpc i/f? d31:f0)? on page 337 flash bios select 1 register e8h ? ebh section 9.1.31, ?fb_sel1?flash bios select 1 register (lpc i/f?d31:f0)? on page 339 lpc generic decode range 2 ech ? edh section 9.1.32, ?gen2_dec?lpc i/f generic decode range 2 register (lpc i/f?d31:f0)? on page 340 flash bios select 2 register ee ? efh section 9.1.33, ?fb_sel2?flash bios select 2 register (lpc i/f?d31:f0)? on page 340 flash bios decode enable 2 register f0h section 9.1.34, ?fb_dec_en2?flash bios decode enable 2 register (lpc i/f?d31:f0)? on page 341 function disable register f2h section 9.1.35, ?func_dis?function disable register (lpc i/ f?d31:f0)? on page 342 ide controller (d31:f1) vendor id 00h ? 01h section 10.1.1, ?vid?vendor identification register (ide? d31:f0)? on page 416 device id 02h ? 03h section 10.1.2, ?did?device identification register (ide? d31:f0)? on page 416 command register 04h ? 05h section 10.1.3, ?pcicmd?pci command register (ide? d31:f1)? on page 417 device status 06h ? 07h section 10.1.4, ?pcists ? pci status register (ide?d31:f1)? on page 418 revision id 08h programming interface 09h section 10.1.5, ?rid?revision identification register (ide? d31:f1)? on page 419 sub class code 0ah section 10.1.7, ?scc?sub class code register (ide? d31:f1)? on page 419 base class code 0bh section 10.1.8, ?bcc?base class code register (ide? d31:f1)? on page 420 master latency timer 0dh section 10.1.9, ?pmlt?primary master latency timer register (ide?d31:f1)? on page 420 header type 0eh primary command block base address 10 ? 13h section 10.1.10, ?pcmd_bar?primary command block base address register (ide?d31:f1)? on page 420 primary control block base address 14 ? 17h section 10.1.11, ?pcnl_bar?primary control block base address register (ide?d31:f1)? on page 421 secondary command block base address 18 ? 1bh section 10.1.12, ?scmd_bar?secondary command block base address register (ide d31:f1)? on page 421 secondary control block base address 1c ? 1fh section 10.1.13, ?scnl_bar?secondary control block base address register (ide d31:f1)? on page 421 bus master base address register 20h ? 23h section 10.1.14, ?bm_base ? bus master base address register (ide?d31:f1)? on page 422 subsystem vendor id 2c ? 2dh section 10.1.15, ?ide_svid ? subsystem vendor identification (ide?d31:f1)? on page 422 table 204. intel ? ich5 pci configuration registers (sheet 5 of 11) register name offset datasheet section and location 644 intel ? 82801eb ich5 / 82801er ich5r datasheet register index subsystem id 2e ? 2fh section 10.1.16, ?ide_sid ? subsystem identification register (ide?d31:f1)? on page 422 interrupt line 3ch section 10.1.17, ?intr_ln?interrupt line register (ide? d31:f1)? on page 423 interrupt pin 3dh section 10.1.18, ?intr_pn?interrupt pin register (ide? d31:f1)? on page 423 primary/secondary ide timing 40h ? 43h section 10.1.19, ?ide_tim ? ide timing register (ide? d31:f1)? on page 424 slave ide timing 44h section 10.1.20, ?slv_idetim?slave (drive 1) ide timing register (ide?d31:f1)? on page 425 synchronous dma control register 48h section 10.1.21, ?sdma_cnt?synchronous dma control register (ide?d31:f1)? on page 427 synchronous dma timing register 4ah ? 4bh section 10.1.22, ?sdma_tim?synchronous dma timing register (ide?d31:f1)? on page 428 ide i/o configuration register 54h section 10.1.23, ?ide_config?ide i/o configuration register (ide?d31:f1)? on page 429 sata controller (d31:f2) vendor id 00h ? 01h section 11.1.1, ?vid?vendor identification register (sata? d31:f2)? on page 434 device id 02h ? 03h section 11.1.2, ?did?device identification register (sata? d31:f2)? on page 434 command register 04h ? 05h section 11.1.3, ?pcicmd?pci command register (sata? d31:f2)? on page 435 device status 06h ? 07h section 11.1.4, ?pcists ? pci status register (sata? d31:f2)? on page 436 revision id 08h programming interface 09h section 11.1.6, ?pi?programming interface register (sata? d31:f2)? on page 437 sub class code 0ah section 11.1.7, ?scc?sub class code register (sata? d31:f2)? on page 437 base class code 0bh section 11.1.8, ?bcc?base class code register (sata? d31:f2)? on page 438 master latency timer 0dh section 11.1.9, ?pmlt?primary master latency timer register (sata?d31:f2)? on page 438 header type 0eh primary command block base address 10 ? 13h section 11.1.10, ?pcmd_bar?primary command block base address register (sata?d31:f2)? on page 438 primary control block base address 14 ? 17h section 11.1.11, ?pcnl_bar?primary control block base address register (sata?d31:f2)? on page 439 secondary command block base address 18 ? 1bh section 11.1.12, ?scmd_bar?secondary command block base address register (ide d31:f1)? on page 439 secondary control block base address 1c ? 1fh section 11.1.13, ?scnl_bar?secondary control block base address register (ide d31:f1)? on page 439 bus master base address register 20h ? 23h section 11.1.14, ?bar ? legacy bus master base address register (sata?d31:f2)? on page 440 subsystem vendor id 2c ? 2dh section 11.1.15, ?svid?subsystem vendor identification register (sata?d31:f2)? on page 440 table 204. intel ? ich5 pci configuration registers (sheet 6 of 11) register name offset datasheet section and location intel ? 82801eb ich5 / 82801er ich5r datasheet 645 register index subsystem id 2e ? 2fh section 11.1.16, ?sid?subsystem identification register (sata?d31:f2)? on page 440 capabilities pointer 34h section 11.1.17, ?cap?capabilities pointer register (sata? d31:f2)? on page 441 interrupt line 3ch section 11.1.18, ?int_ln?interrupt line register (sata? d31:f2)? on page 441 interrupt pin 3dh section 11.1.19, ?int_pn?interrupt pin register (sata? d31:f2)? on page 441 primary/secondary ide timing 40h ? 43h section 11.1.20, ?ide_tim ? ide timing register (sata? d31:f2)? on page 442 slave ide timing 44h section 11.1.21, ?sidetim?slave ide timing register (sata? d31:f2)? on page 444 synchronous dma control register 48h section 11.1.22, ?sdma_cnt?synchronous dma control register (sata?d31:f2)? on page 445 synchronous dma timing register 4ah ? 4bh section 11.1.23, ?sdma_tim?synchronous dma timing register (sata?d31:f2)? on page 446 ide i/o configuration register 54h section 11.1.24, ?ide_config?ide i/o configuration register (sata?d31:f2)? on page 447 pci power management capability id 70 ? 71h section 11.1.25, ?pid?pci power management capability identification register (sata?d31:f2)? on page 448 pci power management capabilities 72 ? 73h section 11.1.26, ?pc?pci power management capabilities register (sata?d31:f2)? on page 448 pci power management control and status 74 ? 77h section 11.1.27, ?pmcs?pci power management control and status register (sata?d31:f2)? on page 449 message signaled interrupt capability id 80 ? 81h section 11.1.28, ?mid?message signaled interrupt identifiers register (sata?d31:f2)? on page 449 message signaled interrupt message control 82 ? 83h section 11.1.29, ?mc?message signaled interrupt message control register (sata?d31:f2)? on page 450 message signaled interrupt message address 84 ? 87h section 11.1.30, ?ma?message signaled interrupt message address register (sata?d31:f2)? on page 450 message signaled interrupt message data 88 ? 89h section 11.1.31, ?md?message signaled interrupt message data register (sata?d31:f2)? on page 450 address map 90h section 11.1.32, ?map?address map register (sata?d31:f2)? on page 451 port status and control 92h section 11.1.33, ?pcs?port control and status register (sata?d31:f2)? on page 451 uhci controller (d29:f0/f1/f2/f3) vendor id 00 ? 01h section 12.1.1, ?vid?vendor identification register (usb? d29:f0/f1/f2/f3)? on page 462 device id 02 ? 03h section 12.1.2, ?did?device identification register (usb? d29:f0/f1/f2/f3)? on page 462 command register 04 ? 05h section 12.1.3, ?pcicmd?pci command register (usb? d29:f0/f1/f2/f3)? on page 462 device status 06 ? 07h section 12.1.4, ?pcists?pci status register (usb?d29:f0/ f1/f2/f3)? on page 463 revision id 08h section 12.1.5, ?rid?revision identification register (usb? d29:f0/f1/f2/f3)? on page 463 programming interface 09h section 12.1.6, ?pi?programming interface register (usb? d29:f0/f1/f2/f3)? on page 464 table 204. intel ? ich5 pci configuration registers (sheet 7 of 11) register name offset datasheet section and location 646 intel ? 82801eb ich5 / 82801er ich5r datasheet register index sub class code 0ah section 12.1.7, ?scc?sub class code register (usb? d29:f0/f1/f2/f3)? on page 464 base class code 0bh section 12.1.8, ?bcc?base class code register (usb? d29:f0/f1/f2/f3)? on page 464 header type 0eh section 12.1.9, ?headtyp?header type register (usb? d29:f0/f1/f2/f3)? on page 465 base address register 20 ? 23h section 12.1.10, ?base?base address register (usb? d29:f0/f1/f2/f3)? on page 465 subsystem vendor id 2c ? 2dh section 12.1.11, ?svid ? subsystem vendor identification register (usb?d29:f0/f1/f2/f3)? on page 466 subsystem id 2e ? 2fh section 12.1.12, ?sid ? subsystem identification register (usb?d29:f0/f1/f2/f3)? on page 466 interrupt line 3ch section 12.1.13, ?int_ln?interrupt line register (usb? d29:f0/f1/f2/f3)? on page 466 interrupt pin 3dh section 12.1.14, ?int_pn?interrupt pin register (usb? d29:f0/f1/f2/f3)? on page 467 serial bus release number 60h section 12.1.15, ?usb_relnum?serial bus release number register (usb?d29:f0/f1/f2/f3)? on page 467 usb legacy keyboard/ mouse control c0 ? c1h section 12.1.16, ?usb_legkey?usb legacy keyboard/ mouse control register (usb?d29:f0/f1/f2/f3)? on page 468 usb resume enable c4h section 12.1.17, ?usb_res?usb resume enable register (usb?d29:f0/f1/f2/f3)? on page 470 ehci controller (d29:f7) vendor id 00 ? 01h device id 02 ? 03h command register 04 ? 05h section 13.1.3, ?pcicmd?pci command register (usb ehci?d29:f7)? on page 481 device status 06 ? 07h section 13.1.4, ?pcists?pci status register (usb ehci? d29:f7)? on page 482 revision id 08h programming interface 09h section 13.1.6, ?pi?programming interface register (usb ehci?d29:f7)? on page 483 sub class code 0ah section 13.1.7, ?scc?sub class code register (usb ehci? d29:f7)? on page 483 base class code 0bh section 13.1.8, ?bcc?base class code register (usb ehci? d29:f7)? on page 483 master latency timer 0dh section 13.1.9, ?pmlt?primary master latency timer register (usb ehci?d29:f7)? on page 484 header type 0eh base address register 20 ? 23h section 13.1.10, ?mem_base?memory base address register (usb ehci?d29:f7)? on page 484 subsystem vendor id 2c ? 2dh section 13.1.11, ?svid?usb ehci subsystem vendor id register (usb ehci?d29:f7)? on page 484 subsystem id 2e ? 2fh section 13.1.12, ?sid?usb ehci subsystem id register (usb ehci?d29:f7)? on page 485 capabilities pointer 34h section 13.1.13, ?cap_ptr?capabilities pointer register (usb ehci?d29:f7)? on page 485 table 204. intel ? ich5 pci configuration registers (sheet 8 of 11) register name offset datasheet section and location intel ? 82801eb ich5 / 82801er ich5r datasheet 647 register index interrupt line 3ch section 13.1.14, ?int_ln?interrupt line register (usb ehci? d29:f7)? on page 485 interrupt pin 3dh section 13.1.15, ?int_pn?interrupt pin register (usb ehci? d29:f7)? on page 485 power management capability id 50h section 13.1.16, ?pwr_capid?pci power management capability id register (usb ehci?d29:f7)? on page 486 next item pointer 51h section 13.1.17, ?nxt_ptr1?next item pointer #1 register (usb ehci?d29:f7)? on page 486 power management capabilities 52 ? 53h section 13.1.18, ?pwr_cap?power management capabilities register (usb ehci?d29:f7)? on page 487 power management control and status 54 ? 55h section 13.1.19, ?pwr_cntl_sts?power management control/status register (usb ehci?d29:f7)? on page 488 debug port capability id 58h section 13.1.20, ?debug_capid?debug port capability id register (usb ehci?d29:f7)? on page 488 next item pointer #2 59h section 13.1.21, ?nxt_ptr2?next item pointer #2 register (usb ehci?d29:f7)? on page 489 debug port base offset 5a ? 5bh section 13.1.22, ?debug_base?debug port base offset register (usb ehci?d29:f7)? on page 489 usb release number 60h section 13.1.23, ?usb_relnum?usb release number register (usb ehci?d29:f7)? on page 489 frame length adjustment 61h section 13.1.24, ?fl_adj?frame length adjustment register (usb ehci?d29:f7)? on page 490 power wake capabilities 62 ? 63h section 13.1.25, ?pwake_cap?port wake capability register (usb ehci?d29:f7)? on page 491 usb 2.0 legacy support extended capability 68 ? 6bh section 13.1.26, ?leg_ext_cap?usb ehci legacy support extended capability register (usb ehci?d29:f7)? on page 491 usb 2.0 legacy support control and status 6c ? 6fh section 13.1.27, ?leg_ext_cs?usb ehci legacy support extended control / status register (usb ehci?d29:f7)? on page 492 intel specific usb 2.0 smi 70 ? 73h section 13.1.28, ?special_smi?intel specific usb 2.0 smi register (usb ehci?d29:f7)? on page 493 access control 80h section 13.1.28, ?special_smi?intel specific usb 2.0 smi register (usb ehci?d29:f7)? on page 493 smbus controller (d31:f3) vendor id 00 ? 01h section 14.1.1, ?vid?vendor identification register (smbus? d31:f3)? on page 515 device id 02 ? 03h section 14.1.2, ?did?device identification register (smbus? d31:f3)? on page 516 command register 04 ? 05h section 14.1.3, ?pcicmd?pci command register (smbus? d31:f3)? on page 516 device status 06 ? 07h section 14.1.4, ?pcists?pci status register (smbus? d31:f3)? on page 517 revision id 08h section 14.1.5, ?rid?revision identification register (smbus?d31:f3)? on page 517 programming interface 09h sub class code 0ah section 14.1.7, ?bcc?base class code register (smbus? d31:f3)? on page 518 table 204. intel ? ich5 pci configuration registers (sheet 9 of 11) register name offset datasheet section and location 648 intel ? 82801eb ich5 / 82801er ich5r datasheet register index base class code 0bh section 14.1.8, ?smb_base?smbus base address register (smbus?d31:f3)? on page 518 smb base address register 20 ? 23h section 14.1.8, ?smb_base?smbus base address register (smbus?d31:f3)? on page 518 interrupt line 3ch section 14.1.11, ?int_ln?interrupt line register (smbus? d31:f3)? on page 519 interrupt pin 3dh section 14.1.12, ?int_pn?interrupt pin register (smbus? d31:f3)? on page 519 host configuration 40h section 14.1.13, ?hostc?host configuration register (smbus?d31:f3)? on page 520 ac?97 audio controller (d31:f5) vendor identification 00h ? 01h section 15.1.1, ?vid?vendor identification register (audio? d31:f5)? on page 534 device identification 02h ? 03h section 15.1.2, ?did?device identification register (audio? d31:f5)? on page 534 pci command 04h ? 05h section 15.1.3, ?pcicmd?pci command register (audio? d31:f5)? on page 535 pci device status 06h ? 07h section 15.1.4, ?pcists?pci status register (audio? d31:f5)? on page 536 revision identification 08h section 15.1.5, ?rid?revision identification register (audio? d31:f5)? on page 537 programming interface 09h section 15.1.6, ?pi?programming interface register (audio? d31:f5)? on page 537 sub class code 0ah section 15.1.7, ?scc?sub class code register (audio? d31:f5)? on page 537 base class code 0bh section 15.1.8, ?bcc?base class code register (audio? d31:f5)? on page 537 header type 0eh section 15.1.9, ?headtyp?header type register (audio? d31:f5)? on page 538 native audio mixer base address 10h ? 13h section 15.1.10, ?nambar?native audio mixer base address register (audio?d31:f5)? on page 538 native audio bus mastering base address 14h ? 17h section 15.1.10, ?nambar?native audio mixer base address register (audio?d31:f5)? on page 538 mixer base address(mem) 18 ? 1bh section 15.1.12, ?mmbar?mixer base address register (audio?d31:f5)? on page 539 bus master base address(mem) 1c ? 1f section 15.1.13, ?mbbar?bus master base address register (audio?d31:f5)? on page 540 subsystem vendor id 2ch ? 2dh section 15.1.14, ?svid?subsystem vendor identification register (audio?d31:f5)? on page 540 subsystem id 2eh ? 2fh section 15.1.15, ?sid?subsystem identification register (audio?d31:f5)? on page 541 capabilities pointer 34h section 15.1.16, ?cap_ptr?capabilities pointer register (audio?d31:f5)? on page 541 interrupt line 3ch section 15.1.17, ?int_ln?interrupt line register (audio? d31:f5)? on page 541 interrupt pin 3dh section 15.1.18, ?int_pn?interrupt pin register (audio? d31:f5)? on page 542 programmable codec id 40h section 15.1.19, ?pcid?programmable codec identification register (audio?d31:f5)? on page 542 table 204. intel ? ich5 pci configuration registers (sheet 10 of 11) register name offset datasheet section and location intel ? 82801eb ich5 / 82801er ich5r datasheet 649 register index configuration 41h section 15.1.20, ?cfg?configuration register (audio? d31:f5)? on page 543 pci power management id 50 ? 51h section 15.1.21, ?pid?pci power management capability identification register (audio?d31:f5)? on page 543 pc -power management capabilities 52 ? 53h section 15.1.22, ?pc?power management capabilities register (audio?d31:f5)? on page 544 power management control and status 54 ? 55h section 15.1.23, ?pcs?power management control and status register (audio?d31:f5)? on page 545 ac?97 modem controller (d31:f6) vendor identification 00h ? 01h section 16.1.1, ?vid?vendor identification register (modem? d31:f6)? on page 560 device identification 02h ? 03h section 16.1.2, ?did?device identification register (modem? d31:f6)? on page 560 pci command 04h ? 05h section 16.1.3, ?pcicmd?pci command register (modem? d31:f6)? on page 561 pci device status 06h ? 07h section 15.1.4, ?pcists?pci status register (audio? d31:f5)? on page 536 revision identification 08h section 16.1.5, ?rid?revision identification register (modem?d31:f6)? on page 562 programming interface 09h section 16.1.6, ?pi?programming interface register (modem? d31:f6)? on page 563 sub class code 0ah section 15.1.7, ?scc?sub class code register (audio? d31:f5)? on page 537 base class code 0bh section 16.1.8, ?bcc?base class code register (modem? d31:f6)? on page 563 header type 0eh section 16.1.9, ?headtyp?header type register (modem? d31:f6)? on page 563 modem mixer base address 10h ? 13h section 16.1.10, ?mmbar?modem mixer base address register (modem?d31:f6)? on page 564 modem base address 14h ? 17h section 16.1.11, ?mbar?modem base address register (modem?d31:f6)? on page 564 subsystem vendor id 2ch ? 2dh section 16.1.12, ?svid?subsystem vendor identification register (modem?d31:f6)? on page 565 subsystem id 2eh ? 2fh section 16.1.13, ?sid?subsystem identification register (modem?d31:f6)? on page 565 capabilities pointer 34h section 16.1.14, ?cap_ptr?capabilities pointer register (modem?d31:f6)? on page 565 interrupt line 3c section 16.1.15, ?int_ln?interrupt line register (modem? d31:f6)? on page 566 interrupt pin 3dh section 16.1.16, ?int_pin?interrupt pin register (modem? d31:f6)? on page 566 pci power management id 50 ? 51h section 16.1.17, ?pid?pci power management capability identification register (modem?d31:f6)? on page 566 pc - power management capabilities 52 ? 53h section 16.1.18, ?pc?power management capabilities register (modem?d31:f6)? on page 567 power management control and status 54 ? 55h section 16.1.19, ?pcs?power management control and status register (modem?d31:f6)? on page 567 table 204. intel ? ich5 pci configuration registers (sheet 11 of 11) register name offset datasheet section and location 650 intel ? 82801eb ich5 / 82801er ich5r datasheet register index table 205. intel ? ich5 fixed i/o registers (sheet 1 of 5) register name port datasheet section and location channel 0 dma base & current address register 00h section 9.2.1, ?dmabase_ca?dma base and current address registers (lpc i/f?d31:f0)? on page 345 channel 0 dma base & current count register 01h section 9.2.2, ?dmabase_cc?dma base and current count registers (lpc i/f?d31:f0)? on page 346 channel 1 dma base & current address register 02h section 9.2.1, ?dmabase_ca?dma base and current address registers (lpc i/f?d31:f0)? on page 345 channel 1 dma base & current count register 03h section 9.2.2, ?dmabase_cc?dma base and current count registers (lpc i/f?d31:f0)? on page 346 channel 2 dma base & current address register 04h section 9.2.1, ?dmabase_ca?dma base and current address registers (lpc i/f?d31:f0)? on page 345 channel 2 dma base & current count register 05h section 9.2.2, ?dmabase_cc?dma base and current count registers (lpc i/f?d31:f0)? on page 346 channel 3 dma base & current address register 06h section 9.2.1, ?dmabase_ca?dma base and current address registers (lpc i/f?d31:f0)? on page 345 channel 3 dma base & current count register 07h section 9.2.2, ?dmabase_cc?dma base and current count registers (lpc i/f?d31:f0)? on page 346 channel 0 ? 3 dma command register channel 0 ? 3 dma status register 08h section 9.2.4, ?dmacmd?dma command register (lpc i/f? d31:f0)? on page 347 section 9.2.5, ?dmasta?dma status register (lpc i/f? d31:f0)? on page 347 channel 0 ? 3 dma write single mask register 0ah section 9.2.6, ?dma_wrsmsk?dma write single mask register (lpc i/f?d31:f0)? on page 348 channel 0 ? 3 dma channel mode register 0bh section 9.2.7, ?dmach_mode?dma channel mode register (lpc i/f?d31:f0)? on page 349 channel 0 ? 3 dma clear byte pointer register 0ch section 9.2.8, ?dma clear byte pointer register (lpc i/f? d31:f0)? on page 349 channel 0 ? 3 dma master clear register 0dh section 9.2.9, ?dma master clear register (lpc i/f?d31:f0)? on page 350 channel 0 ? 3 dma clear mask register 0eh section 9.2.10, ?dma_clmsk?dma clear mask register (lpc i/f?d31:f0)? on page 350 channel 0 ? 3 dma write all mask register 0fh section 9.2.11, ?dma_wrmsk?dma write all mask register (lpc i/f?d31:f0)? on page 350 aliased at 00h ? 0fh 10h ? 1fh master pic icw1 init. cmd word 1 register master pic ocw2 op ctrl word 2 register master pic ocw3 op ctrl word 3 register 20h section 9.4.2, ?icw1?initialization command word 1 register (lpc i/f?d31:f0)? on page 356 section 9.4.8, ?ocw2?operational control word 2 register (lpc i/f?d31:f0)? on page 359 section 9.4.9, ?ocw3?operational control word 3 register (lpc i/f?d31:f0)? on page 360 master pic icw2 init. cmd word 2 register master pic icw3 init. cmd word 3 register master pic icw4 init. cmd word 4 register master pic ocw1 op ctrl word 1 register 21h section 9.4.3, ?icw2?initialization command word 2 register (lpc i/f?d31:f0)? on page 357 section 9.4.4, ?icw3?master controller initialization command word 3 register (lpc i/f?d31:f0)? on page 357 section 9.4.6, ?icw4?initialization command word 4 register (lpc i/f?d31:f0)? on page 358 section 9.4.7, ?ocw1?operational control word 1 (interrupt mask) register (lpc i/f?d31:f0)? on page 359 aliased at 20h ? 21h 24h ? 25h aliased at 20h ? 21h 28h ? 29h intel ? 82801eb ich5 / 82801er ich5r datasheet 651 register index aliased at 20h ? 21h 24h ? 25h aliased at 20h ? 21h 2ch ? 2dh aliased at 20h ? 21h 30h ? 31h aliased at 20h ? 21h 34h ? 35h aliased at 20h ? 21h 38h ? 39h aliased at 20h ? 21h 3ch ? 3dh counter 0 interval time status byte format counter 0 counter access port register 40h section 9.3.2, ?sbyte_fmt?interval timer status byte format register (lpc i/f?d31:f0)? on page 354 section 9.3.3, ?counter access ports register (lpc i/f? d31:f0)? on page 355 counter 1 interval time status byte format counter 1 counter access port register 41h section 9.3.2, ?sbyte_fmt?interval timer status byte format register (lpc i/f?d31:f0)? on page 354 section 9.3.3, ?counter access ports register (lpc i/f? d31:f0)? on page 355 counter 2 interval time status byte format counter 2 counter access port register 42h section 9.3.2, ?sbyte_fmt?interval timer status byte format register (lpc i/f?d31:f0)? on page 354 section 9.3.3, ?counter access ports register (lpc i/f? d31:f0)? on page 355 timer control word register timer control word register read back counter latch command 43h section 9.3.1, ?tcw?timer control word register (lpc i/f? d31:f0)? on page 352 section 9.3.1.1, ?rdbk_cmd?read back command (lpc i/ f?d31:f0)? on page 353 section 9.3.1.2, ?ltch_cmd?counter latch command (lpc i/ f?d31:f0)? on page 353 aliased at 40h ? 43h 50h ? 53h nmi status and control register 61h section 9.7.1, ?nmi_sc?nmi status and control register (lpc i/f?d31:f0)? on page 373 nmi enable register 70h section 9.7.2, ?nmi_en?nmi enable (and real time clock index) register (lpc i/f?d31:f0)? on page 374 real-time clock (standard ram) index register 70h section 147, ?rtc (standard) ram bank (lpc i/f?d31:f0)? on page 369 section 9.7.2, ?nmi_en?nmi enable (and real time clock index) register (lpc i/f?d31:f0)? on page 374 real-time clock (standard ram) target register 71h section 147, ?rtc (standard) ram bank (lpc i/f?d31:f0)? on page 369 extended ram index register 72h extended ram target register 73h aliased at 70h ? 71h 74h ? 75h aliased if u128e bit in rtc configuration register is enabled section 9.1.24, ?back_cntl?backed up control register (lpc i/f?d31:f0)? on page 333 aliased at 72h ? 73h or 70h ? 71h 76h ? 77h aliased to 70h ? 71h if u128e bit in rtc configuration register is enabled section 9.1.24, ?back_cntl?backed up control register (lpc i/f?d31:f0)? on page 333 channel 2 dma memory low page register 81h section 9.2.3, ?dmamem_lp?dma memory low page registers (lpc i/f?d31:f0)? on page 346 table 205. intel ? ich5 fixed i/o registers (sheet 2 of 5) register name port datasheet section and location 652 intel ? 82801eb ich5 / 82801er ich5r datasheet register index channel 3 dma memory low page register 82h section 9.2.3, ?dmamem_lp?dma memory low page registers (lpc i/f?d31:f0)? on page 346 channel 1 dma memory low page register 83h section 9.2.3, ?dmamem_lp?dma memory low page registers (lpc i/f?d31:f0)? on page 346 reserved page registers 84h ? 86h channel 0 dma memory low page register 87h section 9.2.3, ?dmamem_lp?dma memory low page registers (lpc i/f?d31:f0)? on page 346 reserved page register 88h channel 6 dma memory low page register 89h section 9.2.3, ?dmamem_lp?dma memory low page registers (lpc i/f?d31:f0)? on page 346 channel 7 dma memory low page register 8ah section 9.2.3, ?dmamem_lp?dma memory low page registers (lpc i/f?d31:f0)? on page 346 channel 5 dma memory low page register 8bh section 9.2.3, ?dmamem_lp?dma memory low page registers (lpc i/f?d31:f0)? on page 346 reserved page registers 8ch ? 8eh refresh low page register 8fh aliased at 81h ? 8fh 91h ? 9fh (except 92h) fast a20 and init register 92h section 9.7.3, ?port92?fast a20 and init register (lpc i/f? d31:f0)? on page 374 slave pic icw1 init. cmd word 1 register slave pic ocw2 op ctrl word 2 register slave pic ocw3 op ctrl word 3 register a0h section 9.4.2, ?icw1?initialization command word 1 register (lpc i/f?d31:f0)? on page 356 section 9.4.8, ?ocw2?operational control word 2 register (lpc i/f?d31:f0)? on page 359 section 9.4.9, ?ocw3?operational control word 3 register (lpc i/f?d31:f0)? on page 360 slave pic icw2 init. cmd word 2 register slave pic icw3 init. cmd word 3 register slave pic icw4 init. cmd word 4 register slave pic ocw1 op ctrl word 1 register a1 section 9.4.3, ?icw2?initialization command word 2 register (lpc i/f?d31:f0)? on page 357 section 9.4.4, ?icw3?master controller initialization command word 3 register (lpc i/f?d31:f0)? on page 357 section 9.4.6, ?icw4?initialization command word 4 register (lpc i/f?d31:f0)? on page 358 section 9.4.7, ?ocw1?operational control word 1 (interrupt mask) register (lpc i/f?d31:f0)? on page 359 aliased at a0h ? a1h a4h ? a5h aliased at a0h ? a1h a8h ? a9h aliased at a0h ? a1h ach ? adh aliased at a0h ? a1h b0h ? b1h advanced power management control port register b2h section 9.9.1, ?apm_cnt?advanced power management control port register? on page 384 advanced power management status port register b3h section 9.9.2, ?apm_sts?advanced power management status port register? on page 384 aliased at a0h ? a1h b4h ? b5h aliased at a0h ? a1h b8h ? b9h aliased at a0h ? a1h bch ? bdh table 205. intel ? ich5 fixed i/o registers (sheet 3 of 5) register name port datasheet section and location intel ? 82801eb ich5 / 82801er ich5r datasheet 653 register index channel 4 dma base & current address register c0h section 9.2.1, ?dmabase_ca?dma base and current address registers (lpc i/f?d31:f0)? on page 345 aliased at c0h c1h channel 4 dma base & current count register c2h section 9.2.2, ?dmabase_cc?dma base and current count registers (lpc i/f?d31:f0)? on page 346 aliased at c2h c3h channel 5 dma base & current address register c4h section 9.2.1, ?dmabase_ca?dma base and current address registers (lpc i/f?d31:f0)? on page 345 aliased at c4h c5h channel 5 dma base & current count register c6h section 9.2.2, ?dmabase_cc?dma base and current count registers (lpc i/f?d31:f0)? on page 346 aliased at c6h c7h channel 6 dma base & current address register c8h section 9.2.1, ?dmabase_ca?dma base and current address registers (lpc i/f?d31:f0)? on page 345 aliased at c8h c9h channel 6 dma base & current count register cah section 9.2.2, ?dmabase_cc?dma base and current count registers (lpc i/f?d31:f0)? on page 346 aliased at cah cbh channel 7 dma base & current address register cch section 9.2.1, ?dmabase_ca?dma base and current address registers (lpc i/f?d31:f0)? on page 345 aliased at cch cdh channel 7 dma base & current count register ceh section 9.2.2, ?dmabase_cc?dma base and current count registers (lpc i/f?d31:f0)? on page 346 aliased at ceh cfh channel 4 ? 7 dma command register channel 4 ? 7 dma status register d0h section 9.2.4, ?dmacmd?dma command register (lpc i/f? d31:f0)? on page 347 section 9.2.5, ?dmasta?dma status register (lpc i/f? d31:f0)? on page 347 aliased at d0h d1h channel 4 ? 7 dma write single mask register d4h section 9.2.6, ?dma_wrsmsk?dma write single mask register (lpc i/f?d31:f0)? on page 348 aliased at d4h d5h channel 4 ? 7 dma channel mode register d6h section 9.2.7, ?dmach_mode?dma channel mode register (lpc i/f?d31:f0)? on page 349 aliased at d6h d7h channel 4 ? 7 dma clear byte pointer register d8h section 9.2.8, ?dma clear byte pointer register (lpc i/f? d31:f0)? on page 349 aliased at d8h d9h channel 4 ? 7 dma master clear register dah section 9.2.9, ?dma master clear register (lpc i/f?d31:f0)? on page 350 aliased at dah dbh channel 4 ? 7 dma clear mask register dch section 9.2.10, ?dma_clmsk?dma clear mask register (lpc i/f?d31:f0)? on page 350 aliased at dch deh channel 4 ? 7 dma write all mask register deh section 9.2.11, ?dma_wrmsk?dma write all mask register (lpc i/f?d31:f0)? on page 350 table 205. intel ? ich5 fixed i/o registers (sheet 4 of 5) register name port datasheet section and location 654 intel ? 82801eb ich5 / 82801er ich5r datasheet register index note: when the pos_dec_en bit is set, additional i/o ports get positively decoded by the ich5. aliased at deh dfh coprocessor error register f0h section 9.7.4, ?coproc_err?coprocessor error register (lpc i/f?d31:f0)? on page 375 pio mode command block offset for secondary drive 170h ? 177h see the at attachment - 6 with packet interface (ata/atapi - 6) for detailed register description pio mode command block offset for primary drive 1f0h ? 1f7h see the at attachment - 6 with packet interface (ata/atapi - 6) for detailed register description pio mode control block offset for secondary drive 376h see the at attachment - 6 with packet interface (ata/atapi - 6) for detailed register description pio mode control block offset for primary drive 3f6h see the at attachment - 6 with packet interface (ata/atapi - 6) for detailed register description master pic edge/level triggered register 4d0h section 9.4.10, ?elcr1?master controller edge/level triggered register (lpc i/f?d31:f0)? on page 361 slave pic edge/level triggered register 4d1h section 9.4.11, ?elcr2?slave controller edge/level triggered register (lpc i/f?d31:f0)? on page 362 reset control register cf9h section 9.7.5, ?rst_cnt?reset control register (lpc i/f? d31:f0)? on page 375 table 205. intel ? ich5 fixed i/o registers (sheet 5 of 5) register name port datasheet section and location intel ? 82801eb ich5 / 82801er ich5r datasheet 655 register index table 206. intel ? ich5 variable i/o registers (sheet 1 of 6) register name offset datasheet section and location lan control/status registers (csr) may be mapped to either i/o space or memory space. lan csr at csr_io_base + offset or csr_mem_base + offset. csr_mem_base set in section 7.1.11, ?csr_mem_base ? csr memory-mapped base address register (lan controller? b1:d8:f0)? on page 281 csr_io_base set in section 7.1.12, ?csr_io_base ? csr i/o-mapped base address register (lan controller?b1:d8:f0)? on page 281 scb status word 01h ? 00h section 7.2.1, ?scb_sta?system control block status word register (lan controller?b1:d8:f0)? on page 288 scb command word 03h ? 02h section 7.2.2, ?scb_cmd?system control block command word register (lan controller?b1:d8:f0)? on page 289 scb general pointer 07h ? 04h section 7.2.3, ?scb_genpnt?system control block general pointer register (lan controller?b1:d8:f0)? on page 291 port obh ? 08h section 7.2.4, ?port?port interface register (lan controller?b1:d8:f0)? on page 291 eeprom control register 0fh ? 0eh section 7.2.5, ?eeprom_cntl?eeprom control register (lan controller?b1:d8:f0)? on page 292 mdi control register 13h ? 10h section 7.2.6, ?mdi_cntl?management data interface (mdi) control register (lan controller?b1:d8:f0)? on page 293 receive dma byte count 17h ? 14h section 7.2.7, ?rec_dma_bc?receive dma byte count register (lan controller?b1:d8:f0)? on page 293 early receive interrupt 18h section 7.2.8, ?erec_intr?early receive interrupt register (lan controller?b1:d8:f0)? on page 294 flow control register 1ah ? 19h section 7.2.9, ?flow_cntl?flow control register (lan controller?b1:d8:f0)? on page 295 pmdr 1bh section 7.2.10, ?pmdr?power management driver register (lan controller?b1:d8:f0)? on page 296 general control 1ch section 7.2.11, ?gencntl?general control register (lan controller?b1:d8:f0)? on page 297 general status 1dh section 7.2.12, ?gensta?general status register (lan controller?b1:d8:f0)? on page 297 power management i/o registers at pmbase+offset pm1 status 00 ? 01h section 9.10.1, ?pm1_sts?power management 1 status register? on page 386 pm1 enable 02 ? 03h section 9.10.2, ?pm1_en?power management 1 enable register? on page 388 pm1 control 04 ? 07h section 9.10.3, ?pm1_cnt?power management 1 control? on page 389 pm1 timer 08 ? 0bh section 9.10.4, ?pm1_tmr?power management 1 timer register? on page 390 processor control 10h ? 13h section 9.10.5, ?proc_cnt?processor control register? on page 390 general purpose event 0 status 28 ? 2bh section 9.10.6, ?gpe0_sts?general purpose event 0 status register? on page 392 general purpose event 0 enables 2c ? 2fh section 9.10.7, ?gpe0_en?general purpose event 0 enables register? on page 394 smi# control and enable 30 ? 31h section 9.10.8, ?smi_en?smi control and enable register? on page 396 smi status register 34 ? 35h section 9.10.9, ?smi_sts?smi status register? on page 398 alternate gpi smi enable 38 ? 39h section 9.10.10, ?alt_gp_smi_en?alternate gpi smi enable register? on page 400 alternate gpi smi status 3a ? 3bh section 9.10.11, ?alt_gp_smi_sts?alternate gpi smi status register? on page 400 656 intel ? 82801eb ich5 / 82801er ich5r datasheet register index monitor smi status 40h section 9.10.12, ?mon_smi?device monitor smi status and enable register? on page 400 device activity status 44h section 9.10.13, ?devact_sts ? device activity status register? on page 401 device trap enable 48h section 9.10.14, ?devtrap_en?device trap enable register? on page 402 tco i/o registers at tcobase + offset tcobase = pmbase + 40h tco_rld: tco timer reload and current value 00h section 9.11.1, ?tco_rld?tco timer reload and current value register? on page 403 tco_tmr: tco timer initial value 01h section 9.11.2, ?tco_tmr?tco timer initial value register? on page 404 tco_dat_in: tco data in 02h section 9.11.3, ?tco_dat_in?tco data in register? on page 404 tco_dat_out: tco data out 03h section 9.11.4, ?tco_dat_out?tco data out register? on page 404 tco1_sts: tco status 04h ? 05h section 9.11.5, ?tco1_sts?tco1 status register? on page 405 tco2_sts: tco status 06h ? 07h section 9.11.6, ?tco2_sts?tco2 status register? on page 406 tco1_cnt: tco control 08h ? 09h section 9.11.7, ?tco1_cnt?tco1 control register? on page 407 tco2_cnt: tco control 0ah ? 0bh section 9.11.8, ?tco2_cnt?tco2 control register? on page 408 gpio i/o registers at gpiobase + offset gpio use select 00 ? 03h section 9.12.1, ?gpio_use_sel?gpio use select register? on page 410 gpio input/output select 04 ? 07h section 9.12.2, ?gp_io_sel?gpio input/output select register? on page 410 gpio level for input or output 0c ? 0fh section 9.12.3, ?gp_lvl?gpio level for input or output register? on page 411 gpio blink enable 18 ? 1bh section 9.12.4, ?gpo_blink?gpo blink enable register? on page 411 gpio signal invert 2c ? 2fh section 9.12.5, ?gpi_inv?gpio signal invert register? on page 412 table 206. intel ? ich5 variable i/o registers (sheet 2 of 6) register name offset datasheet section and location intel ? 82801eb ich5 / 82801er ich5r datasheet 657 register index bmide i/o registers at bm_base + offset bm_base is set at section 10.1.12, ?scmd_bar?secondary command block base address register (ide d31:f1)? on page 421 command register primary 00 section 10.2.1, ?bmic[p,s]?bus master ide command register (ide?d31:f1)? on page 431 status register primary 02 section 10.2.2, ?bmis[p,s]?bus master ide status register (ide?d31:f1)? on page 432 descriptor table pointer primary 04 ? 07 section 10.2.3, ?bmid[p,s]?bus master ide descriptor table pointer register (ide?d31:f1)? on page 432 command register secondary 08 section 10.2.1, ?bmic[p,s]?bus master ide command register (ide?d31:f1)? on page 431 status register secondary 0a section 10.2.2, ?bmis[p,s]?bus master ide status register (ide?d31:f1)? on page 432 descriptor table pointer secondary 0c ? 0f section 10.2.3, ?bmid[p,s]?bus master ide descriptor table pointer register (ide?d31:f1)? on page 432 usb i/o registers at base address + offset usb base address is set at section 12.1.10, ?base?base address register (usb?d29:f0/f1/f2/f3)? on page 465 usb command register 00 ? 01 section 12.2.1, ?usbcmd?usb command register? on page 471 usb status register 02 ? 03 section 12.2.2, ?usbsts?usb status register? on page 474 usb interrupt enable 04 ? 05 section 12.2.3, ?usbintr?usb interrupt enable register? on page 475 usb frame number 06 ? 07 section 12.2.4, ?frnum?frame number register? on page 475 usb frame list base address 08 ? 0b section 12.2.5, ?frbaseadd?frame list base address register? on page 476 usb start of frame modify 0c section 12.2.6, ?sofmod?start of frame modify register? on page 476 port 0, 2, 4 status/control 10 ? 11 section 12.2.7, ?portsc[0,1]?port status and control register? on page 477 port 1, 3, 5 status/control 12 ? 13 section 12.2.7, ?portsc[0,1]?port status and control register? on page 477 loop back test data 18h smbus i/o registers at smb_base + offset smb_base is set at section 14.1.8, ?smb_base?smbus base address register (smbus?d31:f3)? on page 518 host status 00h section 14.2.1, ?hst_sts?host status register (smbus? d31:f3)? on page 522 host control 02h section 14.2.2, ?hst_cnt?host control register (smbus? d31:f3)? on page 523 host command 03h section 14.2.3, ?hst_cmd?host command register (smbus?d31:f3)? on page 525 transmit slave address 04h section 14.2.4, ?xmit_slva?transmit slave address register (smbus?d31:f3)? on page 525 host data 0 05h section 14.2.5, ?hst_d0?host data 0 register (smbus? d31:f3)? on page 525 host data 1 06h section 14.2.6, ?hst_d1?host data 1 register (smbus? d31:f3)? on page 525 block data byte 07h section 14.2.7, ?host_block_db?host block data byte register (smbus?d31:f3)? on page 526 table 206. intel ? ich5 variable i/o registers (sheet 3 of 6) register name offset datasheet section and location 658 intel ? 82801eb ich5 / 82801er ich5r datasheet register index packet error check 08h section 14.2.8, ?pec?packet error check (pec) register (smbus?d31:f3)? on page 526 receive slave address 09h section 14.2.9, ?rcv_slva?receive slave address register (smbus?d31:f3)? on page 527 receive slave data 0ah section 14.2.10, ?slv_data?receive slave data register (smbus?d31:f3)? on page 527 auxiliary status 0ch section 14.2.11, ?aux_sts?auxiliary status register (smbus?d31:f3)? on page 527 auxiliary control 0dh section 14.2.12, ?aux_ctl?auxiliary control register (smbus?d31:f3)? on page 528 ac?97 audio i/o registers at nambar + offset nambar is set at section 15.1.11, ?nabmbar?native audio bus mastering base address register (audio?d31:f5)? on page 539 pcm in buffer descriptor list base address register 00h section 15.2.1, ?x_bdbar?buffer descriptor base address register (audio?d31:f5)? on page 549 pcm in current index value 04h section 15.2.2, ?x_civ?current index value register (audio? d31:f5)? on page 550 pcm in last valid index 05h section 15.2.3, ?x_lvi?last valid index register (audio? d31:f5)? on page 550 pcm in status register 06h section 15.2.4, ?x_sr?status register (audio?d31:f5)? on page 551 pcm in position in current buffer 08h section 15.2.5, ?x_picb?position in current buffer register (audio?d31:f5)? on page 552 pcm in prefetched index value 0ah section 15.2.6, ?x_piv?prefetched index value register (audio?d31:f5)? on page 552 pcm in control register 0bh section 15.2.7, ?x_cr?control register (audio?d31:f5)? on page 553 pcm out buffer descriptor list base address register 10h section 15.2.1, ?x_bdbar?buffer descriptor base address register (audio?d31:f5)? on page 549 pcm out current index value 14h section 15.2.2, ?x_civ?current index value register (audio? d31:f5)? on page 550 pcm out last valid index 15h section 15.2.3, ?x_lvi?last valid index register (audio? d31:f5)? on page 550 pcm out status register 16h section 15.2.4, ?x_sr?status register (audio?d31:f5)? on page 551 pcm out position in current buffer 18h section 15.2.5, ?x_picb?position in current buffer register (audio?d31:f5)? on page 552 pcm out prefetched index value 1ah section 15.2.6, ?x_piv?prefetched index value register (audio?d31:f5)? on page 552 pcm out control register 1bh section 15.2.7, ?x_cr?control register (audio?d31:f5)? on page 553 mic. in buffer descriptor list base address register 20h section 15.2.1, ?x_bdbar?buffer descriptor base address register (audio?d31:f5)? on page 549 mic. in current index value 24h section 15.2.2, ?x_civ?current index value register (audio? d31:f5)? on page 550 mic. in last valid index 25h section 15.2.3, ?x_lvi?last valid index register (audio? d31:f5)? on page 550 mic. in status register 26h section 15.2.4, ?x_sr?status register (audio?d31:f5)? on page 551 mic in position in current buffer 28h section 15.2.5, ?x_picb?position in current buffer register (audio?d31:f5)? on page 552 table 206. intel ? ich5 variable i/o registers (sheet 4 of 6) register name offset datasheet section and location intel ? 82801eb ich5 / 82801er ich5r datasheet 659 register index mic. in prefetched index value 2ah section 15.2.6, ?x_piv?prefetched index value register (audio?d31:f5)? on page 552 mic. in control register 2bh section 15.2.7, ?x_cr?control register (audio?d31:f5)? on page 553 global control 2ch section 15.2.8, ?glob_cnt?global control register (audio? d31:f5)? on page 554 global status 30h section 15.2.9, ?glob_sta?global status register (audio? d31:f5)? on page 556 codec access semaphore register 34h section 15.2.10, ?cas?codec access semaphore register (audio?d31:f5)? on page 558 ac?97 audio i/o registers at mbbar + offset mbbar is set at section 15.1.13, ?mbbar?bus master base address register (audio?d31:f5)? on page 540 mic. 2 buffer descriptor list base address register 40 ? 43h section 15.2.1, ?x_bdbar?buffer descriptor base address register (audio?d31:f5)? on page 549 mic. 2 current index value 44h section 15.2.2, ?x_civ?current index value register (audio? d31:f5)? on page 550 mic. 2 last valid index 45h section 15.2.3, ?x_lvi?last valid index register (audio? d31:f5)? on page 550 mic. 2 status register 46 ? 47h section 15.2.4, ?x_sr?status register (audio?d31:f5)? on page 551 mic 2 position in current buffer 48 ? 49h section 15.2.5, ?x_picb?position in current buffer register (audio?d31:f5)? on page 552 mic. 2 prefetched index value 4ah section 15.2.6, ?x_piv?prefetched index value register (audio?d31:f5)? on page 552 mic. 2 control register 4bh section 15.2.7, ?x_cr?control register (audio?d31:f5)? on page 553 pcm in 2 buffer descriptor list base address register 50 ? 53h section 15.2.1, ?x_bdbar?buffer descriptor base address register (audio?d31:f5)? on page 549 pcm in 2 current index value 54h section 15.2.2, ?x_civ?current index value register (audio? d31:f5)? on page 550 pcm in 2 last valid index 55h section 15.2.3, ?x_lvi?last valid index register (audio? d31:f5)? on page 550 pcm in 2 status register 56 ? 57h section 15.2.4, ?x_sr?status register (audio?d31:f5)? on page 551 pcm in 2 position in current buffer 58 ? 59h section 15.2.5, ?x_picb?position in current buffer register (audio?d31:f5)? on page 552 pcm in 2 prefetched index value 5ah section 15.2.6, ?x_piv?prefetched index value register (audio?d31:f5)? on page 552 pcm in 2 control register 5bh section 15.2.7, ?x_cr?control register (audio?d31:f5)? on page 553 s/pdif buffer descriptor list base address register 60 ? 63 section 15.2.1, ?x_bdbar?buffer descriptor base address register (audio?d31:f5)? on page 549 s/pdif current index value 64h section 15.2.2, ?x_civ?current index value register (audio? d31:f5)? on page 550 s/pdif last valid index 65h section 15.2.3, ?x_lvi?last valid index register (audio? d31:f5)? on page 550 s/pdif status register 66 ? 67h section 15.2.4, ?x_sr?status register (audio?d31:f5)? on page 551 s/pdif position in current buffer 68 ? 69h section 15.2.5, ?x_picb?position in current buffer register (audio?d31:f5)? on page 552 table 206. intel ? ich5 variable i/o registers (sheet 5 of 6) register name offset datasheet section and location 660 intel ? 82801eb ich5 / 82801er ich5r datasheet register index s/pdif prefetched index value 6ah section 15.2.6, ?x_piv?prefetched index value register (audio?d31:f5)? on page 552 s/pdif control register 6bh section 15.2.7, ?x_cr?control register (audio?d31:f5)? on page 553 sdata_in map register 80 section 15.2.11, ?sdm?sdata_in map register (audio? d31:f5)? on page 558 ac?97 modem i/o registers at mbar + offset mbar is set in section 16.1.11, ?mbar?modem base address register (modem?d31:f6)? on page 564 modem in buffer descriptor list base address register 00h section 16.2.1, ?x_bdbar?buffer descriptor list base address register (modem?d31:f6)? on page 570 modem in current index value register 04h section 16.2.2, ?x_civ?current index value register (modem?d31:f6)? on page 570 modem in last valid index register 05h section 16.2.3, ?x_lvi?last valid index register (modem? d31:f6)? on page 571 modem in status register 06h section 16.2.4, ?x_sr?status register (modem?d31:f6)? on page 572 modem in position in current buffer register 08h section 16.2.5, ?x_picb?position in current buffer register (modem?d31:f6)? on page 573 modem in prefetch index value register 0ah section 16.2.6, ?x_piv?prefetch index value register (modem?d31:f6)? on page 573 modem in control register 0bh section 16.2.7, ?x_cr?control register (modem?d31:f6)? on page 574 modem out buffer descriptor list base address register 10h section 16.2.1, ?x_bdbar?buffer descriptor list base address register (modem?d31:f6)? on page 570 modem out current index value register 14h section 16.2.2, ?x_civ?current index value register (modem?d31:f6)? on page 570 modem out last valid register 15h section 16.2.3, ?x_lvi?last valid index register (modem? d31:f6)? on page 571 modem out status register 16h section 16.2.4, ?x_sr?status register (modem?d31:f6)? on page 572 modem in position in current buffer register 18h section 16.2.5, ?x_picb?position in current buffer register (modem?d31:f6)? on page 573 modem out prefetched index register 1ah section 16.2.6, ?x_piv?prefetch index value register (modem?d31:f6)? on page 573 modem out control register 1bh section 16.2.7, ?x_cr?control register (modem?d31:f6)? on page 574 global control 3ch section 16.2.8, ?glob_cnt?global control register (modem?d31:f6)? on page 575 global status 40h section 16.2.9, ?glob_sta?global status register (modem? d31:f6)? on page 576 codec access semaphore register 44h section 16.2.10, ?cas?codec access semaphore register (modem?d31:f6)? on page 578 table 206. intel ? ich5 variable i/o registers (sheet 6 of 6) register name offset datasheet section and location intel ? 82801eb ich5 / 82801er ich5r datasheet 661 register bit index b numerics 12-clock retry enable 314 position in current buffer 573 64 bit address capable 450 64-bit addressing capability 498 66 mhz capable 278, 304, 308, 320, 463, 482, 517, 536, 562 66mhz capable 418, 436 a a20gate pass-through enable 469 ac '97 interrupt routing 542 ac ?97 cold reset# 555, 575 ac ?97 warm reset 555, 575 ac_sdin0 codec ready 557, 577 ac_sdin0 interrupt enable 554 ac_sdin0 resume interrupt 557, 577 ac_sdin0 resume interrupt enable 575 ac_sdin1 codec ready 557, 577 ac_sdin1 interrupt enable 554 ac_sdin1 resume interrupt 557, 577 ac_sdin1 resume interrupt enable 575 ac_sdin2 codec ready 556, 576 ac_sdin2 interrupt enable 554, 575 ac_sdin2 resume interrupt 556, 576 ac97_en 395 ac97_sts 393 aclink shut off 554, 575 acpi enable 323 ad3 556, 576 address 450, 525 address increment/decrement select 349 address of descriptor table 432, 459 adi 356 afterg3_en 379 alarm flag 372 alarm interrupt enable 371 alternate a20 gate 374 alternate access mode enable 331 alternate gpi smi enable 400 alternate gpi smi status 400 apic data 364 apic enable 331 apic id 365 apic index 363 apm_sts 399 apmc_en 396 asf enabled 296 asynchronous schedule enable 500 asynchronous schedule park capability 498 asynchronous schedule status 502 autoinitialize enable 349 automatic end of interrupt 358 automatically append crc 528 auxiliary current 284, 448, 487, 544, 567 b bar number 489 base address 281, 322, 325, 420, 421, 422, 438, 439, 440, 465, 476, 484, 518, 538, 539, 540, 564 base address (low) 506 base and current address 345 base and current count 346 base class code 279, 305, 321, 420, 438, 464, 483, 518, 537, 563 binary/bcd countdown select 352 bios lock enable 324 bios release 396 bios write enable 324 bios_en 397 bios_sts 399 bioswr_sts 405 bist fis failed 454 bist fis parameters 454 bist fis successful 454 bist fis transmit data 1 455 bist fis transmit data 2 455 bit 1 of slot 12 577 bit 1 of slot 12 557 bit 2 of slot 12 557, 577 bit 3 of slot 12 557, 577 bit clock stopped 556, 576 block data 526 boot_sts 406 buffer completion interrupt status 551, 572 buffer descriptor base address(31-3) 549 buffer descriptor list base address (31-3) 570 buffered mode 358 bus master enable 277, 303, 319, 417, 435, 462, 662 intel ? 82801eb ich5 / 82801er ich5r datasheet 481, 516, 535, 561 bus master ide active 432, 458 bus_err 522 byte done status 522 c cache line size 280 capabilities list 278, 436, 463, 482, 562 capabilities list exists 536 capabilities list indicator 517 capabilities pointer 282, 441, 485, 541, 565 capability id 283, 448, 449, 491, 543, 566 capability register length value 496 cascaded interrupt controller irq connection 357 channel 0 select 329 channel 1 select 329 channel 2 select 329 channel 3 select 329 channel 5 select 329 channel 6 select 329 channel 7 select 329 channel mask bits 350 channel mask select 348 channel request status 347 channel terminal count status 347 clear byte pointer 349 clear mask register 350 cna mask 289 cnf1_lpc_en 337 cnf2_lpc_en 337 codec access semaphore 558, 578 coma decode range 335 coma_lpc_en 338 comb decode range 335 comb_lpc_en 338 command unit 288 command unit command 290 command unit status 288 configuration layout 465 configure flag 471, 507 connect status change 478, 511 coprocessor error 375 coprocessor error enable 330 count register status 354 count_size_cap 581 countdown type status 354 counter 0 select 353 counter 1 select 353 counter 2 select 353 counter latch command 353 counter mode selection 352 counter out pin state 354 counter port 355 counter select 352 counter selection 353 counter value 582 cpu configuration 330 cpu frequency strap 333 cpu power failure 378 cpu slp# enable 377 cpu thermal trip status 378 crc error 527 cu not active 288 current connect status 478, 511 current equals last valid 551, 572 current index value (4-0) 550, 570 cx mask 289 d d1 support 284, 448, 487 d2 support 284, 448, 487 d29_f0_disable 342 d29_f1_disable 342 d29_f2_disable 342 d29_f3_disable 342 d29_f7_disable 342 d31_f1_disable 343 d31_f2_disable 343 d31_f3_disable 343 d31_f5_disable 343 d31_f6_disable 342 data 293, 450, 452 data message byte 0 527 data message byte 1 527 data mode 371 data parity error detected 278, 320, 418, 436, 463, 517, 536, 562 data scale 285, 488 data select 285, 488 data_high_byte 531 data_len_cnt 513 data_low_byte 531 data0/count 525 data1 525 databuffer(63-0) 514 date alarm 372 daylight savings enable 371 debug port capability id 488 debug port number 497 debug port offset 489 intel ? 82801eb ich5 / 82801er ich5r datasheet 663 deep power-down on link down enable 297 delayed transaction enable 331 delivery mode 368 delivery status 367 destination 367 destination mode 368 detected parity error 278, 304, 308, 320, 418, 436, 482, 517, 536, 562 dev(7-4)_trap_en 400 dev(7-4)_trap_sts 400 dev_err 523 device connects 224 device id 276, 302, 318, 416, 434, 462, 480, 516, 534, 560 device monitor status 398 device partial/slumber request port 0 453 device partial/slumber request port 1 453 device specific initialization 284, 448, 487, 544, 567 device_address 530 devsel# timing status 278, 304, 308, 320, 418, 436, 463, 482, 517, 536, 562 diagnose result 292 discard timer serr# enable 311 discard timer status 311 division chain select 370 dma channel group enable 347 dma channel select 348, 349 dma collection buffer enable 331 dma controller halted 551, 572 dma group arbitration priority 347 dma low page 346 dma transfer mode 349 dma transfer type 349 done_sts 512 dram initialization bit 378 drive 0 dma capable 432, 458 drive 0 dma timing enable 425, 443 drive 0 fast timing bank 425, 443 drive 0 iordy sample point enable 425, 443 drive 0 prefetch/posting enable 425, 443 drive 1 dma capable 432, 458 drive 1 dma timing enable 424, 442 drive 1 fast timing bank 425, 443 drive 1 iordy sample point enable 424, 442 drive 1 prefetch/posting enable 424, 442 drive 1 timing register enable 424, 442 duplex mode 297 dynamic data 285 e early receive 288 early receive count 294 edge/level bank select (ltim) 356 eeprom chip select 292 eeprom serial clock 292 eeprom serial data in 292 eeprom serial data out 292 ehc initialization 215 ehc resets 216 ehci extended capabilities pointer 498 enable 32-byte buffer 528 enable special mask mode 360 enabled_cnt 512 enables cpu bist 333 end of smi 397 enter global suspend mode 471 er mask 289 error 432, 458 error_good#_sts 513 exception_sts 513 extended destination id 367 f failed 522 fast back to back capable 278, 304, 308, 320, 418, 436, 463, 482, 517, 536, 562 fast back to back enable 277, 303, 311, 319, 417, 435, 462, 516, 535, 561 fast primary drive 0 base clock 429, 447 fast primary drive 1 base clock 429, 447 fast secondary drive 0 base clock 429, 447 fast secondary drive 1 base clock 429, 447 fb_40_en 341 fb_40_idsel 340 fb_50_en 341 fb_50_idsel 340 fb_60_en 341 fb_60_idsel 340 fb_70_en 341 fb_70_idsel 340 fb_c0_en 336 fb_c0_idsel 339 fb_c8_en 336 fb_c8_idsel 339 fb_d0_en 336 fb_d0_idsel 339 fb_d8_en 336 fb_d8_idsel 339 fb_e0_en 336 664 intel ? 82801eb ich5 / 82801er ich5r datasheet fb_e0_idsel 339 fb_e8_en 336 fb_e8_idsel 339 fb_f0_en 336 fb_f0_idsel 339 fb_f8_en 336 fb_f8_idsel 339 fc full 295 fc paused 295 fc paused low 295 fcp mask 289 fdd decode range 335 fdd_lpc_en 338 fifo error 551, 572 fifo error interrupt enable 553, 574 flow control pause 288 flow control threshold 295 force global resume 471 force port resume 510 force thermal throttling 390 fr mask 289 frame length timing value 490 frame list current index/frame number 475, 505 frame list rollover 503 frame list rollover enable 504 frame list size 501 frame received 288 full reset 375 g gameh_lpc_en 337 gamel_lpc_en 337 gbl_smi_en 397 general self-test result 292 generic decode range 1 enable 337 generic i/o decode range 1 base address 337 generic i/o decode range 2 base address 340 generic i/o decode range 2 enable 340 global enable 388 global release 389 global reset 472 global status 387 go_cnt 513 gp_blink(n) 411 gp_inv(n) 412 gp_io_sel2(32) 413 gp_io_sel2(34) 413 gp_lvl(32) 414 gp_lvl(34) 414 gp_lvl(41-40) 414 gp_lvl(49-48) 414 gp_lvl(n) 411 gpe0_sts 399 gpi interrupt enable 555, 575 gpi status change interrupt 557, 577 gpi0 route 381 gpi1 route 381 gpi15 route 381 gpi2 route 381 gpin_en 394 gpin_sts 392 gpio enable 325 gpio(n)_sel 410 gpio_use_sel(23-21, 15-14, 11-9, 5-0) 410 gpio_use_sel2(49-48, 41-40) 412 gpio11_alert_disable 408 h hc bios owned semaphore 491 hc os owned semaphore 491 hchalted 474, 502 header type 280, 306, 322, 538, 563 hide device 0 313 hide device 1 313 hide device 2 313 hide device 3 313 hide device 4 313 hide device 5 313 hide device 8 313 hide isa bridge 330 high priority pci enable 314 hole enable 314 host controller process error 474 host controller reset 472, 501 host system error 474, 502 host system error enable 504 host_busy 523 host_notify_intren 530 host_notify_sts 529 host_notify_wken 530 hour format 371 hp unsupported 312 hpet address enable 330 hpet address select 330 hub interface rate 312 hub interface rate valid 312 hub interface timeslice 312 hub interface width 312 hubnmi_sts 405 hubsci_sts 405 intel ? 82801eb ich5 / 82801er ich5r datasheet 665 hubserr_sts 405 hubsmi_sts 405 i i/o address base bits 307 i/o address base upper 16 bits (31-16) 310 i/o address limit bits 307 i/o address limit upper 16 bits (31-16) 310 i/o addressing capability 307 i/o space enable 277, 303, 319, 417, 435, 462, 481, 516, 535, 543, 561 i/o space indicator 281 i2c 240, 242 i2c_en 520 i64_en 377 icw/ocw select 356 icw4 write required 356 ide decode enable 424, 442 idep0_act_sts 401 idep0_trp_en 402 idep1_act_sts 401 idep1_trp_en 402 ides0_act_sts 401 ides0_trp_en 402 ides1_act_sts 401 ides1_trp_en 402 in_use_cnt 513 index 452 init_now 374 integrated sata raid configuration 380 intel_usb2_en 396 intel_usb2_sts 398 interesting packet 296 internal lan master request status 315 internal pci master request status 315 interrupt 432, 458 interrupt disable 277, 417, 435, 462, 481, 516, 535, 561 interrupt enable 293 interrupt input pin polarity 367 interrupt level select 359 interrupt line 282, 423, 441, 466, 485, 519, 541, 566 interrupt line routing 310 interrupt mask 289 interrupt on async advance 502 interrupt on async advance doorbell 500 interrupt on async advance enable 504 interrupt on complete enable 475 interrupt on completion enable 553, 574 interrupt pin 519 interrupt pin 283, 423, 441, 467, 485, 566 interrupt request flag 372 interrupt request level 357 interrupt request mask 359 interrupt rout 583 interrupt routing enable 326, 328 interrupt status 278, 418, 436, 463, 482, 517, 536, 562 interrupt threshold control 500 interrupt vector base address 357 intr 523 intrd_sel 408 intren 524 intruder detect 406 inuse_sts 522 io space indicator 518 iochk# nmi enable 373 iochk# nmi source status 373 iordy sample point 424, 442 irq number 364 irq routing 326, 328 irq1_cause 409 irq10 ecl 362 irq11 ecl 362 irq12 ecl 362 irq12_cause 409 irq14 ecl 362 irq15 ecl 362 irq3 ecl 361 irq4 ecl 361 irq5 ecl 361 irq6 ecl 361 irq7 ecl 361 irq9 ecl 362 isa enable 311 k kbc_act_sts 401 kbc_lpc_en 337 kbc_trp_en 402 keyboard irq1 latch enable 330 kill 524 l lan connect address 293 lan connect register address 293 lan connect software reset 297 last codec read data input 558 last valid buffer completion interrupt 551, 572 last valid buffer interrupt enable 553, 574 666 intel ? 82801eb ich5 / 82801er ich5r datasheet last valid index (4-0) 550, 571 last_byte 523 latch count of selected counters 353 latch status of selected counters 353 leg_act_sts 401 leg_io_trp_en 402 legacy rout 581 legacy rout capable 581 legacy_usb_en 397 legacy_usb_sts 399 legacy_usb2_en 396 legacy_usb2_sts 398 light host controller reset 500 line status 478, 509 link pointer low 507 link status change indication 296 link status indication 297 link_id_sts 513 loop back test mode 471 low speed device attached 477 lower 128-byte lock 334 lpc bridge disable 342 lpt decode range 335 lpt_lpc_en 338 m magic packet 296 main counter tick period 581 management data interrupt 288 map value 451 mask 367 master abort mode 311 master abort status 278, 320, 536, 562 master clear 350 master data parity error detected 304, 308, 482 master latency timer count 280, 305, 307, 420, 438, 484 master/slave in buffered mode 358 max data 312 max packet 471 maximum latency 283 maximum redirection entries 366 mc_lpc_en 337 mcsmi_enmicrocontroller smi enable 396 md3 556, 576 memory address base 309 memory address limit 309 memory space enable 277, 303, 319, 417, 435, 462, 481, 516, 535, 561 memory write and invalidate enable 277, 303, 535, 561 memory-space indicator 281 microcontroller smi# status 399 microphone 2 in interrupt 556, 576 microphone in interrupt 557, 577 microprocessor mode 358 minimum grant 283 minimum slp_s4# assertion width violation status 378 mode selection status 354 modem in interrupt 557, 577 modem out interrupt 557, 577 mon(n)_trap_base 383 mon4_fwd_en 382 mon4_mask 383 mon5_fwd_en 382 mon5_mask 383 mon6_fwd_en 382 mon6_mask 383 mon7_fwd_en 382 mon7_mask 383 mouse irq12 latch enable 330 msi enable 450 multichannel capabilities 556, 576 multi-function device 280, 306, 322, 465 multiple message capable 450 multiple message enable 450 multi-transaction timer count value 315 n n_ports 497 newcentury_sts 405 next capability 448, 543, 566 next ehci capability pointer 491 next item pointer 284 next item pointer 1 value 486 next item pointer 2 capability 489 next pointer 449 nmi enable 374 nmi_now 407 nmi2smi_en 407 nmi2smi_sts 406 no reboot 332 number of companion controllers 497 number of ports per companion controller 497 number of timer capability 581 o ocw2 select 359 ocw3 select 360 opcode 293 intel ? 82801eb ich5 / 82801er ich5r datasheet 667 overall enable 581 overcurrent active 477, 510 overcurrent change 510 overcurrent indicator 477 owner_cnt 512 p parity error response 277, 303, 319, 417, 435, 462, 481, 516, 535, 561 parity error response enable 311 pass through state 469 pci interrupt enable 468 pci master request status 315 pci parity inversion state 316 pci serr# enable 373 pcisml_scli 298 pcisml_sclo 298 pcisml_sdai 298 pcisml_sdao 298 pcisml_sgnt 298 pcisml_sreq 298 pcm 4/6 enable 554 pcm in 1, microphone in 1 data in line 558 pcm in 2 interrupt 556, 576 pcm in 2, microphone in 2 data in line 558 pcm in interrupt 557, 577 pcm out interrupt 557, 577 pcm out mode 554 pec_data 526 pec_en 523 periodic interrupt capable 583 periodic interrupt enable 371 periodic interrupt flag 372 periodic list execution 216 periodic schedule enable 500 periodic schedule status 502 periodic smi# rate select 377 periodic_en 396 periodic_sts 398 pirqae_act_sts 401 pirqbf_act_sts 401 pirqcg_act_sts 401 pirqdh_act_sts 401 pm1_sts_reg 399 pme clock 284, 448, 487, 544, 567 pme enable 285, 449, 488, 567 pme status 285, 296, 449, 488, 545, 567 pme support 284, 448, 487, 544, 567 pme_b0_en 394 pme_b0_sts 392 pme_en 395 pme_sts 392 pointer field 291 poll mode command 360 pop_mode_cap 419, 437 pop_mode_sel 419, 437 port 0 bist fis initiate 454 port 0 enabled 451 port 0 present 451 port 1 bist fis initiate 454 port 1 enabled 451 port 1 present 451 port change detect 503 port change interrupt enable 504 port enable/disable change 478, 510 port enabled/disabled 478, 511 port function selection 291 port owner 509 port power 509 port reset 477, 509 port test control 509 port wake implemented 491 port wake up capability mask 491 port0en 470 port1en 470 position in current buffer (15-0) 552 positive decode enable 331 postable memory write enable 319, 417, 435, 462, 481, 516 power button enable 388 power button override status 386 power button status 387 power failure 379 power management capability id 486 power management data 286 power management event enable 545 power sequencing 617 power state 285, 449, 488, 545, 567 prd interrupt status 458 prefetch flush enable 314 prefetchable 281, 484 prefetchable memory address base 309 prefetchable memory address limit 310 prefetched index value (4-0) 552, 573 prim_sig_mode 429, 447 primary bus number 306 primary discard timer 311 primary drive 0 base clock 430, 448 primary drive 0 cycle time 428, 446 primary drive 0 synchronous dma mode enable 668 intel ? 82801eb ich5 / 82801er ich5r datasheet 427, 445 primary drive 1 base clock 430, 448 primary drive 1 cycle time 428, 446 primary drive 1 iordy sample point 426, 444 primary drive 1 recovery time 426, 444 primary drive 1 synchronous dma mode enable 427, 445 primary master channel cable reporting 429 primary slave channel cable reporting 429 programmable frame list flag 498 programming interface 321, 464, 483, 537, 563 prq 366 pwrbtn_lvl 377 pwrok failure 378 r rate select 370 read / write control 431, 457 read back command 353 read completion status 557, 577 read policies for periodic dma 217 read/write select 352 read/write selection status 354 ready 293 real time clock index address 374 receive dma byte count 293 receive not ready 288 receive unit command 290 receive unit status 289 received master abort 304, 308, 418, 436, 463, 482, 517 received system error 308 received target abort 278, 304, 308, 320, 482, 517 received_pid_sts(23-16) 514 reclamation 502 recovery time 424, 442 redirection entry clear 365 refresh cycle toggle 373 register read command 360 register result 292 remote irr 367 req(5)#/gnt(5)# pc/pci protocol select 330 reset cpu 375 reset registers 553, 574 resource type indicator 322, 325, 420, 421, 422, 438, 439, 440, 465, 484, 538, 539, 540, 564 resume detect 474, 477 resume interrupt enable 475 revision id 279, 305, 321, 419, 437, 463, 483, 537, 562 revision identificaiton 581 ri_en 395 ri_sts 393 rnr mask 289 rom content result 292 rotate and eoi codes 359 rtc event enable 388 rtc status 386 rtc_pwr_stsrtc power status 379 run/pause bus master 553, 574 run/stop 472, 501 rw 525 s s/pdif interrupt 556, 576 s/pdif slot map 554 safe mode 332 sample capabilities 556, 576 sata setup data a 452 sata setup data b 453 scb general pointer 291 sci enable 389 sci irq select 323 scratchpad bit 365 sec_sig_mode 429, 447 second_to_sts 406 secondary bus number 306 secondary bus reset 311 secondary codec id 542 secondary discard timer 311 secondary drive 0 base clock 430, 448 secondary drive 0 cycle time 428, 446 secondary drive 0 synchronous dma mode enable 427, 445 secondary drive 1 base clock 429, 447 secondary drive 1 cycle time 428, 446 secondary drive 1 iordy sample point 425, 444 secondary drive 1 recovery time 426, 444 secondary drive 1 synchronous dma mode enable 427, 445 secondary master channel cable reporting 429 secondary slave channel cable reporting 429 send_now 407 send_pid_cnt(15-8) 514 serial bus release number 467 serial irq enable 327 serial irq frame size 327 serial irq mode select 327 intel ? 82801eb ich5 / 82801er ich5r datasheet 669 serirq_smi_sts 398 serr# due to delayed transaction timeout 329 serr# due to received target abort 316, 329 serr# enable 277, 303, 311, 319, 417, 435, 462, 481, 516, 535, 561 serr# enable on receiving target abort 316 serr# nmi source status 373 serr# on delayed transaction timeout enable 328 serr# on received target abort enable 328 short packet interrupt enable 475 signaled system error 278, 304, 320, 418, 436, 482, 517, 536, 562 signaled target abort 278, 304, 308, 320, 418, 436, 463, 482, 517, 536, 562 single or cascade 356 slave identification code 358 slave_addr 527 sleep enable 389 sleep type 389 slp_s4# assertion stretch enable 379 slp_s4# minimum assertion width 379 slp_smi_en 396 slp_smi_sts 399 smb_cmd 524 smb_for_bios 343 smb_smi_en 520 smbalert_dis 530 smbalert_sts 522 smbclk_ctl 529 smbclk_cur_sts 529 smbdata_cur_sts 529 smbus host enable 520 smbus smi status 398 smbus tco mode 527 smbus wake status 393 smi at end of pass-through enable 469 smi caused by end of pass-through 468 smi caused by port 60 read 468 smi caused by port 60 write 468 smi caused by port 64 read 468 smi caused by port 64 write 468 smi caused by usb interrupt 468 smi on async 493 smi on async advance 492 smi on async advance enable 493 smi on async enable 494 smi on bar 492 smi on bar enable 492 smi on cf 494 smi on cf enable 494 smi on frame list rollover 492 smi on frame list rollover enable 493 smi on hchalted 494 smi on hchalted enable 494 smi on hcreset 494 smi on hcreset enable 494 smi on host system error 492 smi on host system error enable 493 smi on os ownership change 492 smi on os ownership enable 493 smi on pci command 492 smi on pci command enable 492 smi on periodic 494 smi on periodic enable 494 smi on pmcsr 493 smi on pmscr enable 494 smi on port 60 reads enable 469 smi on port 60 writes enable 469 smi on port 64 reads enable 469 smi on port 64 writes enable 469 smi on port change detect 492 smi on port change enable 493 smi on portowner 493 smi on portowner enable 494 smi on usb complete 492 smi on usb complete enable 493 smi on usb error 492 smi on usb error enable 493 smi on usb irq enable 469 smi_lock 377 smlink slave smi status 406 smlink_clk_ctl 528 smlink0_cur_sts 528 smlink1_cur_sts 528 sof timing value 476 software debug 471 software generated interrupt 289 software interrupt 288 software smi# timer enable 396 sop_mode_cap 419, 437 sop_mode_sel 419, 437 speaker data enable 373 special cycle enable 277, 303, 319, 417, 435, 462, 481, 516, 535, 561 special fully nested mode 358 special mask mode 360 speed 297 square wave enable 371 start 523 start frame pulse width 327 670 intel ? 82801eb ich5 / 82801er ich5r datasheet start/stop bus master 431, 457 steer enable 558 stpclk_del 380 sub class code 279, 305, 321, 419, 437, 464, 483, 518, 537, 563 subordinate bus number 306 subsystem id 282, 422, 440, 466, 485, 519, 541, 565 subsystem vendor id 281, 422, 440, 466, 484, 518, 540, 565 suspend 477, 510 sw_tco_smi 406 swsmi_rate_sel 379 swsmi_tmr_sts 399 system bus message disable 331 system reset 375 system reset status 378 t tco data in value 404 tco data out value 404 tco interrupt enable 324 tco interrupt select 324 tco request 296 tco timer halt 407 tco timer initial value 404 tco timer value 403 tco_en 396 tco_int_sts 406 tco_lock 407 tco_message(n) 408 tco_sts 398 tcosci_en 395 tcosci_sts 393 tertiary codec id 542 thermal interrupt override status 394 thermal interrupt status 394 thrm#_pol 395 thrm_dty 391 thrm_en 395 throttle status 390 thtl_dty 391 thtl_en 391 timeout 405 timeout/crc interrupt enable 475 timer 0 interrupt active 582 timer 1 interrupt active 582 timer 2 interrupt active 582 timer counter 2 enable 373 timer counter 2 out status 373 timer interrupt rout capability 583 timer interrupt type 584 timer n 32-bit mode 583 timer n interrupt enable 584 timer n size 583 timer n type 584 timer n value set 583 timer overflow interrupt enable 388 timer overflow statu 387 timer value 390 token_pid_cnt(7-0) 514 top_swap lock-down 331 top-block swap mode 333 transient disconnect detect 380 trigger mode 367 type 281, 484, 539, 540 u udf supported 536 uhci v/s ehci 215 unimplemented asynchronous park mode bits 500 update cycle inhibit 371 update in progress 370 update-ended flag 372 update-ended interrupt enable 371 upper 128-byte enable 334 upper 128-byte lock 334 upper address(43-32) 506 upper address(63-44) 506 usb error interrupt 474, 503 usb error interrupt enable 504 usb interrupt 474, 503 usb interrupt enable 504 usb release number 489 usb_address_cnf 514 usb_endpoint_cnf 514 usb1_en 395 usb1_sts 393 usb2_en 395 usb2_sts 393 usb3_en 394 usb3_sts 392 usb4_en 394 usb4_sts 392 user definable features 278, 320, 418, 436, 463, 482, 517, 562 v valid ram and time bit 372 vector 368 vendor id 276, 302, 318, 416, 434, 462, 480, intel ? 82801eb ich5 / 82801er ich5r datasheet 671 515, 534, 560 vendor id capability 581 version 284, 366, 448, 487, 544, 567 vga 16-bit decode 311 vga enable 311 vga palette snoop 277, 303, 319, 417, 435, 462, 481, 516, 535, 561 w wait cycle control 277, 303, 319, 417, 435, 462, 481, 516, 535, 561 wake on connect enable 508 wake on disconnect enable 508 wake on overcurrent enable 508 wake status 386 watchdog status 408 write policies for periodic dma 218 write_read#_cnt 513 wrt_rdonly 495 x xoff 295 xon 295 |
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